EE6502 MICROPROCESSORS AND MICROCONTROLLERS OBJECTIVES: To study the Architecture of P8085 & C 8051 To study the addressing modes & instruction set of 8085 & 8051. To introduce the need & use of Interrupt structure 8085 & 8051. To develop skill in simple applications development with programming 8085 & 8051 To introduce commonly used peripheral / interfacing

UNIT I 8085 PROCESSOR 9Hardware Architecture, pin outs Functional Building Blocks of Processor Memory organization I/O ports and data transfer concepts Timing Diagram Interrupts.

UNIT II PROGRAMMING OF 8085 PROCESSOR 9Instruction -format and addressing modes Assembly language format Data transfer, data manipulation & control instructions Programming: Loop structure with counting & Indexing Look up table - Subroutine instructions - stack.

UNIT III 8051 MICRO CONTROLLER 9Hardware Architecture, pin outs Functional Building Blocks of Processor Memory organization I/O ports and data transfer concepts Timing Diagram Interrupts-Comparison to Programming concepts with 8085.

UNIT IV PERIPHERAL INTERFACING 9Study on need, Architecture, configuration and interfacing, with ICs: 8255, 8259, 8254,8237,8251,8279, - A/D and D/A converters &Interfacing with 8085 & 8051.

UNIT V MICRO CONTROLLER PROGRAMMING & APPLICATIONS 9Data Transfer, Manipulation, Control Algorithms& I/O instructions Simple programming exercises key board and display interface Closed loop control of servo motor- stepper motor control Washing Machine Control.TOTAL: 45 PERIODSOUTCOMES: Ability to understand and analyse, linear and digital electronic circuits. To understand and apply computing platform and software for engineering problems.

TEXT BOOKS:1. Krishna Kant, Microprocessor and Microcontrollers, Eastern Company Edition, Prentice Hall of India, New Delhi, 2007.2. R.S. Gaonkar, Microprocessor Architecture Programming and Application, with 8085, Wiley Eastern Ltd., New Delhi, 2013.3. Soumitra Kumar Mandal, Microprocessor & Microcontroller Architecture, Programming & Interfacing using 8085,8086,8051,McGraw Hill Edu,2013.

REFERENCES:1. Muhammad Ali Mazidi & Janice Gilli Mazidi, R.D.Kinely The 8051 Micro Controller and Embedded Systems, PHI Pearson Education, 5th Indian reprint, 2003.2. N.Senthil Kumar, M.Saravanan, S.Jeevananthan, Microprocessors and Microcontrollers, Oxford, 2013.3. Valder Perez, Microcontroller Fundamentals and Applications with Pic, Yeesdee Publishers, Tayler & Francis, 2013.

UNIT I 8085 PROCESSOR 9Hardware Architecture, pin outs Functional Building Blocks of Processor Memory organization I/O ports and data transfer concepts Timing Diagram Interrupts.

1.1 Hardware Architecture & Functional Building Blocks of Processor 1.2 Pin Outs 1.3 Memory organization 1.4 I/O ports and data transfer concepts 1.5 Timing Diagram 1.6 Interrupts

1.1 Hardware ArchitectureMICROPROCESSOR 8085 Hardware Architecture

8085 Bus StructureAddress Bus The address bus is a group of 16 lines generally identified as A0 to A15. The address bus is unidirectional: bits flow in one directionfrom the MPU to peripheral devices. The MPU uses the address bus to perform the first function: identifying a peripheral or a memory location.

8085 Bus StructureData Bus The data bus is a group of eight lines used for data flow. These lines are bi-directional - data flow in both directions between the MPU and memory and peripheral devices. The MPU uses the data bus to perform the second function: transferring binary information. The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 = 256 numbers). The largest number that can appear on the data bus is 11111111.

Control Bus The control bus carries synchronization signals and providing timing signals. The MPU generates specific control signals for every operation it performs. These signals are used to identify a device type with which the MPU wants to communicate.

Registers of 8085

The 8085 have six general-purpose registers to store 8-bit data during program execution. These registers are identified as B, C, D, E, H, and L. They can be combined as register pairsBC, DE, and HLto perform some 16-bit operations.

Accumulator (A) The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator.

Flags The ALU includes five flip-flops that are set or reset according to the result of an operation. The microprocessor uses the flags for testing the data conditions. They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags are Sign, Zero, and Carry. The bit position for the flags in flag register is,D7D6D5D4D3D2D1D0

SZACPCY

1. Sign Flag (S):i. After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag is set. Otherwise it is reset. ii. D7 is reserved for indicating the sign; the remaining is the magnitude of number.iii. If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be viewed as positive number.2. Zero Flag (z): If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is reset.3. Auxiliary Carry Flag (AC): If D3 generates any carry when doing any arithmetic and logical operation, this flag is set. Otherwise it is reset.4. Parity Flag (P): If the result of arithmetic and logical operation contains even number of 1s then this flag will be set and if it is odd number of 1s it will be reset.5. Carry Flag (CY): If any arithmetic and logical operation result have any carry then carry flag is set otherwise it is reset.

Arithmetic and Logic Unit (ALU) It is used to perform the arithmetic operations like addition, subtraction, multiplication, division, increment and decrement and logical operations like AND, OR and EX-OR. It receives the data from accumulator and registers. According to the result it set or reset the flags.

Program Counter (PC) This 16-bit register sequencing the execution of instructions. It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The function of the program counter is to point to the memory address of the next instruction to be executed. When op code is being fetched, the program counter is incremented by one to point to the next memory location.

Stack Pointer (SP) The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading a 16-bit address in the stack pointer (register).

Temporary Register: It is used to hold the data during the arithmetic and logical operations.

Instruction Register: When an instruction is fetched from the memory, it is loaded in the instruction register.

Instruction Decoder: It gets the instruction from the instruction register and decodes the instruction. It identifies the instruction to be performed.

Serial I/O Control: It has two control signals named SID and SOD for serial data transmission.

Timing and Control unit It has three control signals ALE, RD (Active low) and WR (Active low) and three status signals IO/M (Active low), S0 and S1. ALE is used for provide control signal to synchronize the components of microprocessor and timing for instruction to perform the operation. RD (Active low) and WR (Active low) are used to indicate whether the operation is reading the data from memory or writing the data into memory respectively. IO/M (Active low) is used to indicate whether the operation is belongs to the memory or peripherals. If,IO/M(Active Low)S1S2Data Bus Status(Output)

000Halt

001Memory WRITE

010Memory READ

101IO WRITE

110IO READ

011Opcode fetch

111Interrupt acknowledge

Interrupt Control Unit: It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt signal.

1.2 Pin Outs & Signals PIN DETAILS OF 8085 The signals can be grouped as follows1. Power supply and clock signals2. Address bus3. Data bus4. Control and status signals5. Interrupts and externally initiated signals6. Serial I/O ports

1. Power supply and Clock frequency signals: Vcc+ 5 volt power supply VssGround X1, X2: Crystal or R/C network or LC network connections to set the frequency of internal clock generator. The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally. CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor.

Pin Diagram of 8085Logical Schematics of 80852. Address Bus A8 A15 (output; 3-state) It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address;

3. Multiplexed Address / Data Bus AD0 AD7 (input/output; 3-state) These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus. During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 - A7. In the subsequent IO / memory, read / write clock cycle the lines are used as data bus. The CPU may read or write out data through these lines.

4. Control and Status signals ALE (output) - Address Latch Enable. This signal helps to capture the lower order address presented on the multiplexed address / data bus. RD (output 3-state, active low) Read memory or IO device. This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device. WR (output 3-state, active low) - Write memory or IO device. This indicates that the data on the data bus is to be written into the selected memory location or I/O device. IO/M (output) - Select memory or an IO device. This status signal indicates that the read / write operation relates to whether the memory or I/O device. It goes high to indicate an I/O operation. It goes low for memory operations.

5. Status Signals It is used to know the type of current operation of the microprocessor.

IO/M(Active Low)S1S2Data Bus Status (Output)

000Halt

001Memory WRITE

010Memory READ

101IO WRITE

110IO READ

011Op code fetch

111Interrupt acknowledge

6. Interrupts and externally initiated operations: They are the signals initiated by an external device to request the microprocessor to do a particular task or work. There are five hardware interrupts called,

On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low INTA (Interrupt Acknowledge) signal.

Reset In (input, active low) This signal is used to reset the microprocessor. The program counter inside the microprocessor is set to zero. The buses are tri-stated.

Reset Out (Output) It indicates CPU is being reset. Used to reset all the connected devices when the microprocessor is reset.

7. Direct Memory Access (DMA)Tri state devices:

3 output states are high & low states and additionally a high impedance state. When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high impedance state.EAQState

1(high)01High

110Low

0(low)00High impedance

010High impedance

For both high and low states, the output Q draws a current from the input of the OR gate. When E is low, Q enters a high impedance state; high impedance means it is electrically isolated from the OR gates input, though it is physically connected. Therefore, it does not draw any current from the OR gates input. When 2 or more devices are connected to a common bus, to prevent the devices from interfering with each other, the tri state gates are used to disconnect all devices except the one that is communicating at a given instant. The CPU controls the data transfer operation between memory and I/O device. Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly. The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control circuits. HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. After the HLDA signal the DMA controller starts the direct transfer of data.

READY (input) Memory and I/O devices will have slower response compared to microprocessors. Before completing the present job such a slow peripheral may not be able to handle further data or control signal from CPU. The processor sets the READY signal after completing the present job to access the data. The microprocessor enters into WAIT state while the READY pin is disabled.

8. Single Bit Serial I/O ports: SID (input) - Serial input data line SOD (output) - Serial output data line These signals are used for serial communication.

1.3 Memory interfacing

Interfacing Memory with 8085

A microprocessor will have its own address space for accessing physical memory. The memory locations that are directly addressed by the microprocessor is called physical memory space. For example a microprocessor like 8085 has 16 address lines, and it can access a physical memory space of 64K starting from 0000H to FFFFH as shown in Table 1.3.1. The process of interfacing memories to microprocessor and allocating address to each memory location is called memory mapping. The complete address space may be considered as a single memory block. But practically, when ICs are used as memory devices, instead of a single IC (Integrated Chip), few devices that fit into the address space will be used. This is due to the fact a microprocessor based system requires at least one ROM/EPROM and a RAM. For example instead of using a memory device of size 64KB (Kilo Bytes), we can use 8 memory devices with a capacity of 8KB each. This will reduce the chip replacement cost while servicing the microprocessor-based system. When memory blocks are used, to access all the locations in a block n address lines are needed so that

2n = 8 K= 23 K= 23 x 210= 213Therefore n = 13

Address Decoding and memory mapping

Memory address decoding is nothing but to assign an address for each location in the memory chip. The data stored in the memory is accessed by specifying its address. Memory address can be decoded in two waysi)Absolute or Fully decodingand

ii)Linear Select or Partial decoding

There are many advantages in absolute address decoding. They are1. Each memory location has only one address, there is no duplication in the address1. Memory can be placed contiguously in the address space of the microprocessor1. Future expansion can be made easily without disturbing the existing circuitryThere are few disadvantages in this method1. Extra decoders are necessary1. Some delay will be produced by these extra decoders.

The main advantage of linear select decoding is its simplified decoding circuit. This reduces the hardware design cost. But there are many disadvantages in this decoding.1. Multiple addresses are provided for the same location1. Complete memory space of the microprocessor is not efficiently used1. Adding or interfacing ICs with already existing circuitry is difficult.

0. 0. Absolute Address DecodingThe 8085 microprocessor has 16 address lines. Therefore it can access 216 locations in the physical memory. If all these lines are connected to a single memory device, it will decode these 16 address lines internally and produces 216 different addresses from 0000H to FFFFH so that each location in the memory will have a unique address as shown in table 1.3.1 and figure 1.3.1. This is called absolute address decoding. Figure 1.3.1 is called the memory map of 8085 address space and it shows how each location in the physical memory gets an address from the address space of the microprocessor.

A15 A14 A13 A12A11A10 A9 A8A7A6A5A4A3A2 A1A0Hex Address

00000000000000000000H

00000000000000010001H

00000000000000100002H

------------- - -

------------- - -

1111111111111110FFFEH

1111111111111111FFFFH

Table 1.3.1: Memory Address

Figure 1.3.1: 64KB Memory Map (Single Block)Instead of connecting all the 16 address lines to a single 64 KB memory device, we can also use memory devices of lower capacity. In such cases the physical memory space of the microprocessor is divided into smaller memory spaces or memory blocks. Each block is selected by a block select address signal and the memory locations with in a block are accessed by the processors address lines. This is called address portioning. For example if the memory device (memory block) has only 13 address lines, we can use the lower 13 address lines (A0 A12) to access the locations with in a memory block and the remaining 3 lines (A13, A14 and A15) to access 8 such blocks. These three lines are called the block select address signals and this is called address partitioning. Depending on the number of memory blocks, the number of block select address lines will change. The starting address and ending address of each block can be found as shown in Table 1.3.2. Since each block is an Integrated Chip (IC), and each chip has a Chip Select signal, the block select address lines must be used to select the ICs. We have to produce eight chip select signals from the three address lines. Therefore we have to decode these lines using a 3 to 8 decoder or 1 of 8 decoder. In this case the lower thirteen address lines of the processor are connected to the 13 address lines of the memory chip and hence they are internally decoded in the memory. The higher 3 address lines (A13, A14 and A15) are externally decoded by a 3 to 8 decoder. Since three lines can provide a maximum of 8 addresses, in this case they are said to be fully decoded and hence each location in each block has a specific unique address as shown in table 1.3.2. This is called as absolute address decoding. The diagrammatic representation of each block with its address range shown in figure 1.3.2 is called the memory map of the microprocessor system.

Block NoA15A14A13 A12A11 A10 A9A8A7A6A5A4A3 A2A1 A0Hex Address range

10 00000000000000 00000H to

00011111111111111FFFH

20 01000000000000 02000H to

001111111111111 13FFFH

3010000000000000 04000H to

010111111111111 15FFFH

4011000000000000 06000H to

011111111111111 17FFFH

5100000000000000 08000H to

100111111111111 19FFFH

6101000000000000 0A000H to

101111111111111 1BFFFH

7110000000000000 0C000H to

110111111111111 1DFFFH

8111000000000000 0E000H to

111111111111111 1FFFFH

Table 1.3.2: Address Space for Memory Blocks

Figure 3.2: 64KB Memory Map (Eight Blocks)

We use 74LS138 address decoder to generate the chip select signals for each memory block. In this decoder when the address lines A13, A14 and A15 are 000, the output line Y0 will be activated as shown in figure 3.3. This in turn selects the first memory block. Similarly when these lines are 001 (C=0, B=0 and A=1) Y1 will be activated and the second memory block will be selected. When the 8085 microprocessor is reset the contents of the program counter will be 0000H. Since this content is placed on the address bus while accessing the memory, the microprocessor will start executing the program from the address 0000H. A monitor program must be placed starting from this address, so that it reads the inputs and takes action based on that program. The input may even be a function key that requires a specific action to be carried over. Since this program is fixed and developed by the manufactures of the product it is called as firmware and it is stored in a ROM or in an EPROM. Therefore, in any microprocessor based system an EPROM should be placed at the reset address (0000H). In addition to EPROM, any microprocessor based system would require at least few RAM locations to store temporary data. Specifically there should be a RAM for stack operations. So, though we are using eight memory chips of 8KB size each, at least one of the eight ICs must be an EPROM and it should be placed at the starting address of 0000H. The memory map for this case can be given as shown in figure 1.3.2. The EPROM chip must be selected using the chip select signal CS1 and the RAM1 chip must be selected using CS2. The memory interface diagram may be given as shown in Figure 1.3.4.

Figure 1.3.3: Memory Block Decoder

In this type of memory interfacing, all the address lines (A0 to A15) have been used. Each location in the memory will have a single address. This type of address decoding is called as absolute or fully decoded addressing.

Most of the microprocessor based systems do not use the complete 64 KB memory space. Even one EPROM and a RAM will be sufficient. For example in the memory map shown in figure 1.3.2, if only the EPROM and RAM 2 are used in the practical system, the memory map of such a system can be given as shown in figure 1.3.5. Still each location has single address. Therefore it is also called absolute address decoding. The main advantage of this type of decoding is, you can add memory devices for this system without disturbing the already connected devices. The memory interface diagram for this case is given in figure 1.3.6.

1.3.4 Memory interface diagram.

Figure 1.3.5: Memory Map with EPROM and RAM 2

Figure 1.3.6: Interfacing EPROM and RAM

Instead of using 3 to 8 decoder, NAND/AND/OR gates can also be used to generate chip select signals as shown in figure 3.7. In this case, CS1 will be activated to select the EPROM, when all the three inputs to the OR gate (OR1) are zero. Similarly the chip select signal CS3 will be activated to select RAM 2 only when A13 = 0, A14 = 1 and A15 = 0. This is also an absolute address decoding method. But, here we need more decoders (gates) when we want to add more memory chips. The main advantage of the absolute address decoding is the contiguous placement of the memory locations. So no memory space of the microprocessor is wasted without being used.

Figure 1.3.7: Address Decoding using OR Gates

Linear Select Address Decoding

In the circuit given in figure 1.3.8, the address line A15 of the microprocessor has not been used for decoding the chip select signals. The outputs Y0 and Y2 of the 74LS138 decoder will be activated as given in table 1.3.3. Since the address line A15 is not connected to the decoder and the pin C of the decoder has been grounded, irrespective of the signal A15 (i.e.A15 is 0 or 1), the pin C is 0. So, you will get Y0 selected twice i.e. when A15 = 0 and when A15 = 1. Similarly Y2 will also be selected twice. Therefore the address map for the EPROM and RAM is found as shown in Table 1.3.4.A15CA14A13Y0Y2

BA

000001

001010

100001

101010

Table 1.3.3: Linear Select Address Decoding Chip Select Signals

Figure 1.3.8: Linear Select Address Decoding - Circuit Diagram

Block NoA15 A14A13A12A11A10A9A8A7A6A5A4A3 A2A1A0Hex Address range

100000000000000000000H

to

00011111111111111FFFH

301000000000000004000H

to

01011111111111115FFFH

510000000000000008000H

to

10011111111111119FFFH

71100000000000000C000H

to

1101111111111111DFFFH

Table 3.4: Linear Select Decoding Memory Address Ranges

The same EPROM is selected both for the address range 0000H to 1FFFH and 8000H to 9FFFH. This is due to the signals A13 and A14 which have same values in both the cases and hence activates the same chip select signal CS1. Similarly the RAM is selected both for the address range 4000H to 5FFFH and C000H to DFFFH. The memory map for this case is as shown in figure 1.3.9.

Figure 1.3.9: Linear Select Address Decoding Memory Map

Figure 1.3.10: Linear Select Address Decoding using OR gates

In this type of address decoding, if we want to add a RAM chip at the address space 8000H to 9FFFH, which was unnecessarily occupied by the first EPROM, we have to change the decoding circuit. We may not simply add additional circuitry without disturbing the already existing circuit. In this method each location in the physical memory is accessed by more than one address (here two addresses) i.e. address space is wasted. This type of address decoding is called as Linear Select or partially decoded addressing. This happens when we have few address lines without being used for decoding. The same circuit can also be implemented using OR gates as shown in figure1.3.10. In this circuit the OR gates require only two inputs. This is possible, since we have left A15 address line unconnected. Therefore, linear select addressing reduces the hardware requirements.

1.3 . 2B u s C o n t e n t i o nConsider the timing diagram shown in figure 1.3.11 that reads a byte (opcode) from the memory. At the end of the ALE signal, all the 16 bits of the address will be available on the bus. The decoder (74LS138) produces the chip select signals from these address lines after a small decoding delay. The chip select signal will be generated with in 30 ns after the trailing edge of ALE signal. When the chip select signal enables the memory chip, since the address has been already placed on the address pins of the memory, the memory will place the data on the data lines after a small access delay called the memory access time. The output buffer of the memory will be enabled within 20 ns after getting CS signal. The memory access time is the time delay between the address placed on the address bus by the address decoder and the data placed by the memory on the data bus. If the data are placed before the end of the T1 state, both the lower order address and the data from the memory will be placed on the AD0 AD7 lines i.e. both the microprocessor and the memory try to access the same lines as shown in figure 1.3.11 by hashed lines. If the microprocessor tries to place 1 (+5V) and the memory tries to place 0 (0 V or Ground), then the microprocessor pin will be shorted through the memory. This may even damage the processor. This is called bus contention. So, the bus contention will occur when two ICs try to place data on the same bus at the same instant of time. This effect will be very adverse in the case of high speed memories interfaced with slow processors. Since the RD or WR signal is issued by the processor only after the first T- state, if these signals are used along with the output of the address decoders to select the chip, the content of the memory will not be placed before the start of the T2 state.

Figure 1.3.11: Bus Contention Reading Opcode from the Memory

Figure 1.3.12: Avoiding Bus Contention

By using a standard 3 to 8 decoder as shown in figure 1.3.12, the CS signal can be delayed until the end of T1 state. The address decoder is enabled by the G3 signal and hence the CS signal is generated only when RD or WR is low. In figure 1.3.11, point A activates point B and point B in turn activates point C to avoid bus contention.

If you are using logic gates to decode the addresses, bus contention may be avoided by combining the output of the final stage of the decoder with RD or WR signal to produce an active low chip select signal.

NB: Instead of connecting the RD or WR signals to the input or output of the address decoder, the best practice to avoid bus contention is to connect the RD signal to the OE pin of EPROM/RAM and WR signal to R/W pin of RAM.

Example 1.3.1:Interface a 4K EPROM, one 4K RAM and one 8K RAM to a microprocessor with the following Memory Map.

Figure 3.13: Memory MapExample 1.2:

How many memory locations will be available if the memory has 16 address lines?The number of locations that can be accessed by using 16 address lines will be216 = 65536 locations

Example 1.3:

A memory chip has 10 address lines. What is its storage capacity?The memory chip which has 10 address lines will have 210 locations. Since each location can store only one byte of data, the memory capacity will be 210 bytes or 1024 bytes or 1 Kilo Bytes.

Example 1.4:

A memory chip has 16 address lines. What is its storage capacity?The memory chip which has 16 address lines will have 216 locations. Since each location can store only one byte of data, the memory capacity will be 216 bytes or (216 = 26 x 210 = 26 KB = 64 KBNB: 210 = 1024 = 1 Kilo Bytes = 1 KB.26 = 64

A memory chip select decoder is used to provide chip select signal for each memory device (IC). This will decide the address range that is allotted for each memory IC. 74LS138 is a 3 to 8 decoder and it can be used for this purpose. In this example the minimum memory block size is 4K. To access 1K locations 10 address lines must be used (210 =1K = 1024 locations). So to access 4K locations (4 X 1K = 22 X 210 = 212) 12 address lines (A0 A11) must be used. Since 8085 has 16 address lines the decoding can be indicated as shown below.

Figure 1.3.14: Variable Address Lines

While accessing 4 K locations the lower 12 bits (A0 A11) can have either 0 or 1. If all the 12 bits are 0 then that will be the starting address of that memory block if all 12 bits are 1 that will be the end address of the block. The remaining 4 address lines (A12 - A15) are the block select address signals, which decide the memory block number. For example, if A15 A12 is 0000 then memory block that can be accessed by the remaining address lines is block 0. If it is 0001 the memory block that can be accessed is 1. Note that the memory blocks 5 and 6 are combined because a 8-K RAM is to be placed there. The following table shows the starting and ending address of each memory block.

Block NoA15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0Hex Address Range

000000000000000000000H

to

00001111111111110FFFH

100010000000000001000H

to

00011111111111111FFFH

200100000000000002000H

to

00101111111111112FFFH

300110000000000003000H

to

00111111111111113FFFH

401000000000000004000H

to

01001111111111114FFFH

501010000000000005000H

to

01011111111111115FFFH

:

:

15111100000 0000 0 00F000H

to

1111111111111 1 11FFFFH

Table 3.5: Memory MapThe 74LS138 decoder has three input pins marked as CBA when all these three pins are 0 then the output pin O0 will be activated i.e. O0 becomes zero. When CBA is 001 the O1 will be activated and all other output pins will be at high state. i.e. any one of the output pins O0 to O7 is selected based on the input A, B and C and this will happen only if the control pins G1, G2 and G3 are properly activated. Table 3.5 shows that address line A15 is always zero for the address range 0000H to 6FFFH. So this can be connected to G3 pin of the 74LS138. The output pins of 74LS138 must be selected only for memory operations. During memory operations IO/M = 0. So IO/ M is connected to G2 pin of the 74LS138 and hence for any IO operation the chip 74LS138 will not activate any of the output pins. The pin G1 is connected to +5V through a resistor to enable 74LS138.The O0 pin of 74LS138 is connected to the chip select (CS) signal of the 4K EPROM. This allows selecting this EPROM chip when the microprocessor sends address in the range 0000H to 0FFFH. Similarly O1 pin of 74LS138 is connected to the CS of 4K RAM. Since no memory chip is connected in the address range 2000H to 3FFFH, the output pin Q2 is left free. The 8K RAM requires address from 4000H to 5FFFH and these addresses are covered by Q4 and Q5 pins. So these two pins are connected to a two input AND gate. The output of the AND gate is connected to the chip select pin of the RAM and this CS will be activated (active low) if either Q4 or Q5 is low.i.e. the output of the AND gate will be 0 for the addresses 4000H to 5FFFH and hence the 8K RAM chip is selected for this address range.C B AOutput pin Activated

0 0 0O0

0 0 1O1

0 1 0O2

0 1 1O3

1 0 0O4

1 0 1O5

1 1 0O6

1 1 1O7

Table 3.1: Function Table of 74LS138The address lines A0 to A11 of 8085 MPU must be connected to the corresponding address pins of the memory chip and the data lines D0 to D7 of MPU must be connected to the corresponding data pins of all the memory chips. Since 8K RAM has 13 address lines in addition to the twelve address lines (A0 to A11) A12 of MPU must also be connected to the A12 pin of the 8K RAM. You note that bus contention is not addressed in this circuit.

Figure1.3.15: Memory Interfacing

1.3 . 3I n t e r f a c i n g l o w s p e e d m e m o r y

To avoid bus contention, the RD or WR signal of the microprocessor is used along with the address decoding to produce the CS signal for the memory. The RD or WR signal starts approximately in the middle of the T2 state and available up to the end T3 state. If the microprocessor operates at 3 MHz, these signals are available for approximately 1.5 T state or 500 ns (1.5 / 3 MHz = 0.5 micro seconds) and hence the memory access time should be less than 500 ns. If the memory access time is more than this value the data cannot be read. If a low speed memory has access time greater than this value, Wait cycles are introduced between T2 and T3. In such a case, the CS select signal need not be delayed until RD or WR signals are issued by the microprocessor. The memory can decode the address as soon as it gets the address from the microprocessor. In this case the total delay introduced will be equal to the sum of the delays introduced by the decoder, wait cycles and the delay introduced due to memory access time. For example 2716 EPROM has access time of 450 ns and therefore it can be directly interfaced with 3 MHz 8085, but one wait cycle is necessary if it is interfaced with a microprocessor operating at 5 MHz. A low speed memory can also be interfaced with a high speed processor by using low frequency crystal but this will slow down not only the memory read/write operation but all activities of the processor.

The READY pin of 8085 processor is used to introduce wait states. For normal operations of the processor this pin should be connected to logic high. When this pin is made low, the processor will enter into wait state until it is made high again. A special circuitry called Wait State Generator as shown in figure 1.3.16 is required for this purpose. This circuit will introduce a wait state equal to one T-state of the processor cycle as shown in figure 1.3.17. The ALE signal fed to the clock input of the first D-type flip-flop will transfer the logic high input (+5V) placed on its D0 pin to Q0 during its positive edge. The Q0 output is connected to D1 input of the second flip-flop. So, the logic high output on Q0 will be transferred to the output Q1 of the second flip-flop during the positive edge of T2 state. The complement value of Q1 is available on Q1 pin of the second flip-flop. This will reset the first flip-flop i.e. Q0 will become logic 0 as shown in figure 1.3.17. At the same time since Q1 has been connected to the READY pin of the processor, the processor enters into wait state. It will remain in that state until Q1 becomes high. This extends the length of the RD signal as shown in figure 1.3.17 and allows memory to take one more clock period time to place the contents on the bus. The logic 0 placed on D1 pin during this time will be transferred to Q1 in the positive edge of the next clock cycle (T3 state). This will make Q1 logic high and hence the READY signal becomes high and the processor continues its work. It should be noted that wait state can be introduced in any machine cycle of 8085 except in bus idle cycle. The 8085 checks the READY signal at the second T-state of every machine cycle.

Figure 1.3.16: Wait State Generator

I n t e r f a c i n g M o r e t h a n 6 4 K M e m o r y

The 8085 microprocessor can address only 64K memory at a time, if you want to interface more than 64K memory; you can use a jumper or an IO port bit as shown in figure 1.3.18. the chip select signal CS3 will select RAM 2 if the jumper connects B and C and it will select RAM 3 if the jumper connects A and B. Similarly CS4 will select RAM 4 if the port bit is zero and RAM 5 if the port bit is one. The main difference between jumper selection and port bit selection is the manual selection in the first case and automatic or program activated selection in the second case.

Figure 3.18: Interfacing more than 64 K Memory

A microprocessor has address space for memory. Any memory chip that is being interfaced with processor must fit into this memory space. A memory map diagram shows the address boundary for each memory chip interfaced with the processor and an address decoder decides the address range for each chip. There are two types of address decoding viz absolute address decoding and linear select address decoding. When high speed memories are interfaced with slow processors bus contention may occur and when a low speed memory is to be accessed by a fast processors wait state must be introduced using external circuitry.

1.4 I/O ports and data transfer concepts

8085A family includes memory components, which are directly compatible to the 8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and 8355 will have the following features: 2K Bytes ROM 256 Bytes RAM 1 Timer/Counter 4 8bit l/O Ports 1 6bit l/O Port 4 Interrupt Levels Serial In/Serial Out Ports In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing technique. With this technique, an area of memory address space is assigned for l/O address, thereby, using the memory address for I/O manipulation. The 8085A CPU can also interface with the standard memory that does not have the multiplexed address/data bus.

1.5 Timing Diagram

The sequence of operations that a processor has to carry out for executing the instruction is called Instruction cycle. Each instruction cycle of a processor consists of a number of machine cycles. The machine cycle also called as processor cycle is the basic operation performed by the processor. To execute an instruction, the processor will run one or more machine cycles in a specific order. A machine cycle will do only one operation such as memory read, memory write, input port read and output port write. The 8085 microprocessor uses seven types of machine cycles i.e. opcode fetch cycle, memory read, memory write, I/O read, I/O write, interrupt acknowledge and bus idle machine cycles as shown in table 2.2. In general, the instruction cycle of an instruction can be divided into fetch and execute cycles. The fetch cycle reads the opcode from memory. The execute cycle is executed to decode the instruction and to perform the work instructed by the instruction. A system designer uses the status signals to track the internal operations of the processor and to expand the memory of the system. It differentiates an opcode from address or data. It is also used to identify whether a machine cycle is read cycle or write cycle. In 8085 microprocessor, a machine cycle can have maximum of 6 T-states and an instruction cycle can have a maximum of 5 machine cycles.Machine CycleStatusNo. of T statesControl Signals

IO/MS1S0

Opcode Fetch0114RD=0

Memory Read0103RD=0

Memory Write0013WR=0

I/O Read1103RD=0

I/O Write1013WR=0

INTR Acknowledge1113INTA=0

Bus Idle0003

Let the instruction MVI A, 9AH be stored in the memory as follows.

AddressOpcodeMnemonic

41003EMVI A, 9AH

41019A

The Timing diagram shown in figure 2.8 indicates that the MVI A, 9AH instruction stored at the address 4100H is executed with two machine cycles i.e. one Opcode Fetch cycle and one Memory Read cycle. The opcode fetch cycle uses 4 clock signals (T1, T2, T3 and T4) and memory read cycle uses 3 clock signals. Each clock signal (a logic low part and a logic high part) is called a T-State. So an opcode fetch machine cycle has 4T states. Generally the opcode fetch cycle of any 8085 instruction uses 4T states. But some instructions like INX H uses 6T states for opcode fetch.All operations with in 8085 are synchronized with the clock signal. The frequency of the clock signal depends on the crystal connected with 8085. If a 6 MHz crystal is connected, a 3 MHz clock will be generated i.e. the clock is internally divided by 2. This 3 MHz clock is called the operating frequency of the Microprocessor. In the above example the instruction is executed using 7 T-stats. If F is the operating frequency in Hertz and T is the time taken by a T-state then,T = 1/ F Seconds2.1

If an instruction has N number of T-states, then the execution time for that instruction is given byExecution Time = N x T Seconds2.2

In the above example the operating frequency is 3MHz; therefore each T-state will have a time equal to 1/3MHz i.e. 1/3x106 seconds or 1/3 micro seconds. Hence this instruction will be executed in 7 x 1/3 microseconds.The table given below shows the status signals for each type of machine cycle and the number of T-stats required for each machine cycle.

0. Opcode Fetch Cycle

At T1 state of figure 2.8, the microprocessor starts the process of reading the first byte of an instruction (opcode) stored in the memory and it sets the signals IO/M=0, S1=1, S0=1 to indicate an Opcode Fetch cycle (refer Table 2.2 for the states of these signals for other operations). The Microprocessor places the higher order byte of the address (41H) on the address lines A15 A8 and the lower order address on the multiplexed lines AD7 - AD0. Since this address exists only during T1 period this address must be captured and stored using an external latch as explained in section 2.3.1. So the ALE (Address Latch Enable) signal is generated during this T1 time, which is used to enable the external latch to capture the address and this signal is disabled at the end of the T1 as shown in figure 2.8.At T2 state, the processor issues a RD signal which enables the memory to place the data (stored in the address provided during T1 state) on AD7 - AD0 lines. This data goes in to the instruction register. At T2 state the program counter is incremented by one. The RD signal extends up to the end of T3 state. The arrow marks indicate that the point at the tail activates point at the head i.e. until the tail point occurs the head point is blocked. This is necessary because the memory should not place the opcode immediately after it receives the address; it should be sufficiently delayed otherwise both address and opcode will be placed at the same time on the same lower order data lines during T1 state.At T4 state 8085 microprocessor decodes the opcode and finds out that a second byte (data 9AH) is to be read from the memory. During this time the contents of the bus A15 A8 are not important and the data bus AD7 AD0 goes in to high impedance state (Hi Z state). High impedance state indicates that AD7 AD0 pins of the Microprocessor isolates it from other ICs such as memory and ports.The status signals for opcode fetch cycle will be set to IO/M =0 S0 = 1 and S1 =1 as per the details given in table 2.2.

0. Memory Read cycle0. The second machine cycle of this instruction is Memory Read cycle. This cycle consists of 3T states.At T1 state of this cycle, Microprocessor issues IO/M=0, S1=1, S0=0. Microprocessor places the next memory address 4101H on the bus i.e. the microprocessor places the higher order address 41H on the bus lines A15 A8 and the lower order address 01H on AD7 AD0 lines and makes ALE signal high to latch the lower order address.At T2 state ALE will be in deactivated state. So the lower order address latched already will be available on the output of the latch but the lines AD7 AD0 need not have that address. At the rising edge of T2 state the memory places the data (9AH) stored in the corresponding address (4101H) on AD7 AD0 lines. At the same time the Microprocessor issues read signal (RD becomes 0) and the program counter is automatically incremented by one.At T3 state 8085microprocessor reads the data from AD7 AD0 bus and stores it in the accumulator.The status signals for memory read cycle will be set to IO/M =0 S1 = 1 and S0 =0 as per the details given in table 2.2.

NB: Memory Write machine cycle will be generated when the microprocessor wants to store any byte in the memory. In this cycle instead of RD signal, the microprocessor issues WR signal and data flows from microprocessor to memory. Other operations are same. You note that when RD signal becomes active i.e. 0, the WR signal will be at logic high and vice versa. During T1 and T4 states both RD and WR signals will be at logic 1. For I/O operations IO/M signal will be at logic high, the status signals S0 and S1 will also change as per the details given in table 2.2. More examples on timing diagram can be found in chapter 5.

Generally to draw the timing diagram of an 8085 instruction, the following information is needed.0. Number of bytes in the instruction0. Type of machine cycles0. Number of T-states in the opcode fetch cycle

Table 2.3 shows some of the important instructions and the machine cycles used for executing those instructions.

Instruction (Mnemonic)OpcodeMachine CyclesTotal no. of T states

STA 4100H32 00 41Opcode Fetch Memory Read Memory Read Memory Write4+3+3+3=13

LXI H, 4567H21 67 45Opcode Fetch Memory Read Memory Read4+3+3=10

MVI A, 80H3E 80Opcode fetch Memory Read4+3=8

LHLD 4200H

2A 00 42Opcode Fetch Memory Read Memory Read Memory Read Memory Read

4+3+3+3+3=16

OUT 80HD3 80HOpcode Fetch Memory Read I/O Write4+3+3=10

Call 4300H

CD 00 43Opcode Fetch Memory Read Memory Read Memory Write Memory Write

4+3+3+3+3=16

RETC9Opcode Fetch Memory Read Memory Read4+3+3=10

DAD B09Opcode Fetch Bus IdleBus Idle4+3+3=10

Table 2.3 Instructions and T-states

The Instruction decoder, ALU, General Purpose Registers, and Timing and Control Unit are the major logical blocks of any microprocessor architecture. Flags are used for conditional execution of the program. The 8085 processor has five hardware interrupts and it also has two pins for implementing serial data transfer. The data and the lower order address are time multiplexed. The status signals indicate the type of operation the processor is executing. The 8085 microprocessor has a different memory and I/O address spaces.

1.6 Interrupt structure

An interrupt is a signal or condition that causes processor to stop its normal execution flow and makes it to jump to some other location for processing the interrupt.

8085 has 4 mask-able interrupts and 1 non-mask-able interrupts. Mask able interrupts can be disabled be DI instruction. Among four mask-able interrupts one is non-vectored interrupt, that is processor cannot go to a fixed location as in case of vectored interrupt, the external device which caused interrupts needs to specify the vector address.

8085 interrupt response process: Interrupts should be enabled by using EI instruction, then only processor responds to all mask able interrupts. When microprocessor is executing a program, it checks for INTR line during execution of each instruction. If INTR is high then processor completes executing the current instruction, disables the interrupts and sends a INTA signal INTA is used by the external hardware to specify the restart instruction to processor( since INTR is a non-vectored interrupt). When microprocessor receives the RST instruction, it saves PC content on stack and PC is loaded with the vector address. Microprocessor executes the instructions at vector address. The interrupts should be enabled if required in the ISR(interrupt service routine) At the end of interrupt service routine, RET instruction loads the PC from the stack. So processor comes back to the instruction where it was interrupted previously.Restart instructions:RST nThese instructions are like software interrupts to 8085. When these instructions are executed processor vectors(jumps) to a specific location called restart location. The following list gives restart location for different RST instructions.'n' value -- Vector location -- hex codeRST 0 -- 0000H -- C7RST 1 -- 0008H -- CFRST 2 -- 0010H -- D7RST 3 -- 0018H -- DFRST 4 -- 0020H -- E7RST 5 -- 0028H -- EFRST 6 -- 0030H --F7RST 7 -- 0038H --FFTo get the vector location 'n' value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 3 instruction, multiply 3*8=24. 24 in hexadecimal notation is 18H. So vector address is 0018H.8085 has 5 external interrupts. As already mentioned in this 4 are vectored interrupts and 1 is non-vectored interrupt.RST 5.5, RST 6.5, RST 7.5, TRAP are vectored interrupts. INTR is non-vectored interrupt. TRAP is a non mask able interrupt.

Interrupt Priority:when more than one interrupts occur at the same time, then processor responds to them according to the following priorityTRAP(highest)RST 7.5RST 6.5RST 5.5INTR (lowest)

Interrupt vector locations:TRAP 0024H(it is same as RST 4.5)RST 5.5 002CHRST 6.5 0034HRST 7.5 003CHTo get the vector location for RST interrupts, interrupt value is multiplied by 8 and the result is converted to hexadecimal notation. For example RST 5.5 instruction, multiply 5.5*8=44. 44 in hexadecimal notation is 2CH. So vector address is 002CH.

Trigger levels:TRAP is level and edge triggeredRST 7.5 is positive edge triggeredRST 6.5, RST 5.5 are level triggered.

Masking of interrupts:SIM instruction sets mask pattern for RST 5.5, RST 6.5, RST 7.5.SIM instructions reads accumulator bit pattern and accordingly masks the interrupts. The bit pattern is shown in below figure. It also resets D flip-flop of RST 7.5 interrupt. And it also implements serial I/O.

Hardware interrupts:

An external device initiates the hardware interrupts and placing an appropriate signal at the interrupt pin of the processor. If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

TRAP: This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable. TRAP bas the highest priority and vectored interrupt. TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain high until it is acknowledged. In sudden power failure, it executes a ISR and send the data from main memory to backup memory. The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD and TRAP at the same time then HOLD is recognized first and then TRAP is recognized). There are two ways to clear TRAP interrupt. 1.By resetting microprocessor (External signal) 2.By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5: The RST 7.5 interrupt is a maskable interrupt. It has the second highest priority. It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized. Maskable interrupt. It is disabled by, 1.DI instruction 2.System or processor reset. 3.After reorganization of interrupt.

Enabled by EI instruction.

RST 6.5 and 5.5: The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it recognized. Maskable interrupt. It is disabled by, 1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.

Enabled by EI instruction. The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR: INTR is a maskable interrupt. It is disabled by,

1.DI, SIM instruction 2.System or processor reset. 3.After reorganization of interrupt.

Enabled by EI instruction. Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of ISR. It has lowest priority. It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain high state until it recognized. The following sequence of events occurs when INTR signal goes high.1. The 8085 checks the status of INTR signal during execution of each instruction.

2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled.

3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated by the 8085 to transfer the additional bytes into the microprocessor.

4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.

SIM and RIM for interrupts:

The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIM instruction. The status of these interrupts can be read by executing RIM instruction. The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be performed by moving an 8-bit data to accumulator and then executing SIM instruction. The format of the 8-bit data is shown below.

The status of pending interrupts can be read from accumulator after executing RIM instruction. When RIM instruction is executed an 8-bit data is loaded in accumulator, which can be interpreted as shown in fig.

UNIT II PROGRAMMING OF 8085 PROCESSOR 9Instruction - format and addressing modes Assembly language format Data transfer, data manipulation & control instructions Programming: Loop structure with counting & Indexing Look up table - Subroutine instructions - stack.

Instruction cycle, Machine cycle, fetch and execute cycles

Instruction cycle

An instruction is a command given to the microprocessor to perform a specific operation on the given data. Sequence of instructions written for a processor to perform a particular task is called a program. Program & data are stored in the memory. The microprocessor fetches one instruction from the memory at a time & executes it. It executes all the instructions of the program one by one to produce the final result. The necessary steps that a microprocessor carries out to fetch an instruction & necessary data from the memory & to execute it constitute an instruction cycle. In other words, an instruction cycle is defined as the time required completing the execution of an instruction. An instruction cycle consists of a fetch cycle and an execute cycle. The time required to fetch an opcode (fetch cycle) is a fixed slot of time while the time required to execute an instruction (execute cycle) is variable which depends on the type of instruction to be executed. Instruction cycle(IC) = Fetch cycle (FC) + Execute cycle (EC)

This is shown diagrammatically in the Fig.3.11

Figure 11 Instruction cycle

Machine cycle:

Machine cycle is defined as the time required for completing the operation of accessing either memory or I/O device. In the 8085, the machine cycle may consist of three to six T states. The T-state is defined as one sub-division of the operation performed in one clock period. These sub-divisions are internal states synchronized with the system clock. In every machine cycle the first operation is op-code fetch and the remaining will be read or write from memory or IO devices.

Fetch operation:

The first byte of an instruction is its op-code. An instruction may be more than one byte long. The other bytes are data or operand address. The program counter (PC) keeps the memory address of the next instruction to be executed. In the beginning of a fetch cycle the content of the program counter, which is the address of the memory location where op-code is available, is sent to the memory. The memory places the op-code on the data bus so as to transfer it to the microprocessor. The entire operation of fetching an op-code takes three clock cycles.

Execute operation:

The op-code fetched from the memory goes to the instruction register (IR). From the instruction register it goes to the decoder circuitry which decodes the instruction. After the instruction is decoded, execution begins. If the operand is in general purpose registers execution is immediately performed. The time taken for decoding and execution is one clock cycle. If an instruction contains data or operand and address which are still in the memory, the microprocessor has to perform some read operations to get the desired data. After receiving the data it performs execute operation. A read cycle is similar to a fetch cycle. In case of a read cycle the quantity received from the memory are data or operand address instead of an op-code. In some instructions write operation is performed. In write cycle data are sent from the microprocessor to the memory or an output device. Thus we see that in some cases an execute cycle may involve one or more read or write cycles or both.

Instruction set of 8085

An Instruction is a command given to the microprocessor to perform a given task on specified data. Each instruction has two parts one is the task to be performed called the operation code (op-code) and the second is the data to be operated on, known as operand. The operand or data can be specified in various ways.

Instruction and data formats:

The format of a typical instruction is composed of two parts: an operation code or op-code and an operand. Every instruction needs an op-code to specify what the operation of the instruction is and then an operand that gives the appropriate data needed for that particular operation code. According to the word or byte size the 8085 instructions are classified into three types. They area) One byte (single) instructionsb) Two byte instructionsc) Three byte instructions

Onebyte instructions: An instruction with only opcode and do not require any dat or address is called a one byte instruction.

Ex: 1. MOV C, A Hex code = 4FH (one byte) 2. ADD B Hex code = 80H (one byte) 3. CMA Hex code = 2FH (one byte)

Twobyte instructions: At two byte instruction is one which contains an 8-bit op-code and 8-bit operand (Data).

Ex: 1. MVI A, 09 Hex code = 3E, 09 (two bytes) 2. ADD B, 07 Hex code = 80, 07 (two bytes) 3. SUB A, 05 Hex code = 97, 05 (two bytes)

Threebyte instructions: A three byte instruction contains an opcode plus a 16 bit address.

Ex: 1.LXI H, 8509 Hex code = 21, 09, 85 (Three bytes) 2 .LDA 8509 Hex code = 3A, 09, 85 (Three bytes) 3. JMP 9567 Hex code = C3, 67, 95 (Three bytes) 4. STA 3525 Hex code = 32, 35, 25 (Three bytes)

DATA FORMATS: The 8085 is an 8-bit microprocessor which process only binary numbers. But it is very difficult to understand these binary numbers by a common user. So, we have to code these binary numbers into different data formats. The commonly known data formats are ASCII, BCD, signed integers and unsigned integers. The ASCII code is a 7-bit alpha-numeric code that represents decimal numbers, English alphabets and certain special characters. The ASCII stands for American Standard code for Information Interchange

The term BCD stands for binary coded decimal, used for decimal numbers from 0-9.An 8-bit register can store two BCD numbers. A signed integer is either a positive or a negative number. In 8085 microprocessor the most significant bit is used for the sign. Here 0 denotes positive sign and 1 denotes the negative sign. An integer without a sign can be represented by all the 8-bits in a microprocessor register. So, the largest number that can be processed at one time is FFH. The numbers larger than 8-bits like 16, 24, 32 bits can be processed by dividing them in groups of 8-bits.

CLASSIFICATION OF INSTRUCTIONSAn instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. The 8085 microprocessor instruction set has 74 operation codes that result in 246 instructions. This instruction set includes all the 8080A instructions plus two additional instructions namely SIM and RIM.The instruction set of 8085 microprocessor is classified into five groups. They are:1. Data transfer (copy) group.2. Arithmetic group3. Logic group4. Branch control group5. Machine control and I/O group.

Data transfer (copy) instructions The data transfer instructions are used to transfer data from one register to another register, from memory to register or register to memory but not from one memory location to another memory location. Actually this data transfer instruction copies the data from source to destination and the contents of the source are not altered. So, the data transfer instruction performs basically copy operation.Examples of data transfer instructions are MOV, MVI (Move Immediate), LXI (Load Immediate H-L Pair), LDA (Load Accumulator), STA (Store Accumulator), LHLD (Load H-L pair direct), SHLD (Store H-L pair direct), XCHG (Exchange the contents of H-L pair with D-E pair) etc

Ex: MVI A, 55H ; Move the data 55H into Accumulator MOV B, C ; Copies the contents of C register into B register IN 00H ; Read the Input port(00H is the port address) OUT 01H ; write data to an output port(01H is the port address) LXIH 8570H ; Load H-L pair by address 8570H.In the 8085 microprocessor, data transfer instructions do not affect any flags.

Arithmetic InstructionsThe arithmetic operations like addition, subtraction, increment and decrement are performed by the 8085 microprocessor using the following arithmetic instructions.ADD, ADI (Add Immediate), SUB (Subtract), SUI (Subtract Immediate), INR (Increment), DCR (Decrement) etcThe arithmetic operations Add and subtract are performed in relation to the contents of the accumulator. But, the increment or the decrement operations can be performed in any register.

Ex:ADD B, C ; Add the contents of B register to the B register contents ADI 08 ; Add the data 08 to the accumulator. SUB A, B ; Subtract the contents of B register from accumulator. SUI 05 ;Subtract immediate the 8-bit data from accumulator INR B ; Increment the B register contents by one bit DCR C ; Decrement the C register contents by one bit.

Arithmetic instructions modify all the flags according to the data conditions of the result. The INR and DCR instructions affect all flags except the carry flag.

Logical Group of Instructions: Since the microprocessor is a programmable logic chip, it can be perform all the logic functions of the hard-wired logic through its instruction set. The 8085 processor can perform the logic instructions like, AND, OR, NOT (Complement) and X-OR (Exclusive OR) etc The mnemonics of these instructions are given below.

ANA : Logically AND the contents of a register ANI : Logically AND immediate the 8-bit data. ORA : Logically OR the contents of a register. OR : Logically OR immediate the 8-bit data. XRA : Exclusive-OR the contents of a register. XRI : Immediate Exclusive-OR the 8-bit data CMA : Complement the accumulator

All the logic operations are performed in relation to the contents of the accumulator. The CMA instruction does not affect any flags. The executions of the logical instruction do not affect the contents of the operand register.

Branch InstructionsThese instructions are very important because they allow the microprocessor to change the sequence of a program either conditionally or unconditionally. The conditional branch instructions transfer the program to the specified label when certain condition is satisfied. The unconditional branch instructions transfer the program to the specified location unconditionally.We know that the microprocessor is a sequential machine. So, it executes machine codes from one memory location to the next. Branch instructions instruct the microprocessor to go to a different memory location and the processor continues executing machine codes from the new location. The address of the new locations either specified explicitly or provided by the microprocessor or some times by additional hardware. The Branch instructions are classified into three categories. They are

(a). Jump instructions(b). Call and return instructions(c). Restart instructions.Jump instructions specify memory locations explicitly and they are 3-byte instructions. These Jump instructions are of two types. They are , Unconditional Jump and Conditional Jump.

Unconditional Jump:This is similar to Unconditional Go to statement in BASIC. When this instruction is executed the 16-bit address available immediately in the instruction is loaded into the program counter , so that the next sequence of instruction execution starts from this location. This Unconditional Jump instruction enables the programmer to create continuous loops.JMP (16 bit address). So, this is a 3-byte instruction where the first byte is op-code and the second, third bytes specify memory address.For example, the instruction JMP 8500H, instructs the microprocessor to go to the memory location8500H unconditionally. Sometimes, the jump location is specified using a label also.

Conditional Jump:

This instruction allows the microprocessor to make decision depending on certain conditions indicated by flags. The 8085 processor Jump instruction is associated with four flags. Namely Carry flag (CY), Zero flag (Z), Sign flag (S) and Parity flag (P). The following instructions shown in Table 3.3 transfer the program sequence to the memory location specified under the given conditions.S. NoInstructionDescription

1JC (16 bit Addr)Jump on carry (if CY=1)

2JNC (16 bit Addr)Jump on no carry (if CY=0)

3JZ (16 bit Addr)Jump on Zero (if Z=1)

4JNZ (16 bit Addr)Jump on no Zero (if Z=0)

5JP (16 bit Addr)Jump on plus (if D7=0; S=0)

6JM (16 bit Addr)Jump on minus (if D7=1; S=1)

7JPE (16 bit Addr)Jump on Even Parity (if P=1)

8JPO (16 bit Addr)Jump on Odd Parity (if P=0)

Table 3 various conditional jump instructions

To understand the instructions, let us consider the instruction JC (16 bit address). The meaning of this instruction is, the microprocessor is instructed to jump the specified 16 bit memory location if there exists a carry after the arithmetic operation else it will execute the next instruction in the sequence.

CALL and RETURN InstructionsThe microprocessor uses the two instructions CALL and RETURN to implement subroutines. Here CALL instruction calls a subroutine program which is not a part of the main program and the RET instruction at the end of the subroutine program to return the control to the main program.

Ex: CALL (16 bit memory address) RETRESET (RST) InstructionThe 8085 processor provides eight RST instructions to transfer the program control to a specific location on page 00H. These instructions are 1-byte instructions. The various RST instructions and their call locations are given in the following Table 3.4

S. NoMnemonicsHex codeCall location In Hex

1RST 0C70000

2RST1CF0008

3RST2D70010

4RST3DF0018

5RST4E70020

6RST5EF0028

7RST6F70030

8RST7FF0038

Table 4 Various RST instructions and their call locations Machine control and I/O Instructions

There are six basic machine control instructions. They are EI (Enable Interrupt) DI (Disable Interrupt) NOP (No Operation) SIM (Set Interrupt Mask) RIM (Read Interrupt Mask) HLT (Halt)

EI (Enable Interrupt): This is a one byte instruction used to enable the interrupt. This instruction is used to enable the interrupts when the microprocessor is reset or the interrupt enable flag is reset after interrupt acknowledge. This instruction takes one machine cycle with four states. The op-code is FBH.

DI (Disable Interrupt): This is a one byte instruction which resets the interrupt enable flag to disable all the interrupts except TRAP. It takes one machine cycle with four states. The op-code is F3H.

NOP (No Operation): when this instruction is executed, the microprocessor performs nothing. Microprocessor spends four states doing nothing. It is a one byte instruction whose op-code is 00H.This instruction is normally used to generate very small time delays of the order of few micro seconds. This NOP instruction is also very useful when we are required to insert a few instructions in the main program additionally .

SIM (Set Interrupt Mask): This instruction masks the interrupt as desired. This is a dual purpose instruction. The first purpose is to set or reset the mask of the maskable interrupt. The second purpose is to send the data out through the SOD pin at pin number 4 of the microprocessor.

RIM (Read Interrupt Mask): This instruction copies the status of the interrupts into the accumulator. It is also used to read the serial data through the SID pin

HLT (Halt): After execution of this instruction the microprocessor goes into the halt state. The processor can be restarted by a valid interrupt or by applying a RESET signal. The microprocessor takes 5T states to implement the halt instruction.

I/O instructions: There are two important instructions to input the data into the microprocessors accumulator through the input port and output the data from the accumulator to the output port. They are

IN (port address) OUT (port address)

This port address is an 8-bit address. In both these instructions the default register is Accumulator.

Ex: (i) IN 01H. This instruction will copy the contents into the Accumulator through the port whose address is 01H. It takes three machine cycles and takes 10 states. The op-code is DBH. (ii)OUT 02H. This instruction sends the contents of Accumulator to the outport whose address is 02H. It is a two byte instruction which requires 10 states. The op-code for this instruction is D3H.

ADDRESSING MODES

Majority of the instructions of 8085 microprocessor requires an operand (either data or address) on which the intended operation can be performed. Some instructions may require only one operand and some other instructions require two operands for its instruction execution. The speed of execution mainly depends on the position of the operand in the instruction. The scheme involved in identifying the position of operands in an instruction is known as addressing mode.

There are five addressing modes 8085 processor. They arei. Immediate addressing modeii. Direct addressing modeiii. Register addressing mode.iv. Register indirect addressing mode.v. Implicit addressing mode.

(i). Immediate Addressing mode: The mode of addressing in which the operand is a part of the instruction itself is known as Immediate Addressing mode. If the immediate data is 8-bit, the instruction will be of two bytes. If the immediate data is 16 bit, the instruction is of 3 bytes.Ex: (1). ADI DATA ; Add immediate the data to the contents of the accumulator. (2).LXIH 8500H : Load immediate the H-L pair with the operand 8500H (3). MVI 08H ; Move the data 08 H immediately to the accumulator (4). SUI 05H ; Subtract immediately the data 05H from the accumulator

(ii) Direct Addressing mode: The mode of addressing in which the 16-bit address of the operand is directly available in the instruction itself is called Direct Addressing mode. i.e., the address of the operand (data) is available in the instruction itself. This is a 3-byte instruction.Ex: (1). LDA 9525H ; Load the contents of memory location into Accumulator. (2). STA 8000H ; Store the contents of the Accumulator in the location 8000H (3). IN 01H ; Read the data from port whose address is 01H.

(iii). Register addressing modes: The mode, in which the operand is in one of the general purpose registers, is known as the register addressing mode.Ex: (1). MOV A, B; Move the contents of B register to A register. (2). SUB D; Subtract the contents of D register from Accumulator. (3). ADD B, C; Add the contents of C register to the contents of B register.

(iv). Register indirect addressing modes: The 16-bit address location of the operand stored in a register pair (H-L) is given in the instruction. The address of the operand is given in an indirect way with the help of a register pair. Hence it is called Register indirect addressing mode

Ex: (1).LXIH 9570H; Load immediate the H-L pair with the address of the location 9570H MOV A, M; Move the contents of the memory location pointed by the H-L pair to accumulator

(v). Implicit Addressing mode: The mode of instruction which do not specify the operand in the instruction but it is implicated is known as implicit addressing mode. i.e., the operand is automatically considered to be in the Accumulator.Ex: (1).CMA; complement the contents of Accumulator (2).CMC; Complement carry (3). RLC; Rotate Accumulator left by one bit (4). RRC; Rotate Accumulator right by one bit (5). STC; Set carry.

Beginning to use 8085 Assembly LanguageThe Intel 8085 microprocessor has 7 eight bit registers. These registers can hold a quantity as large as 0FF H, 11111111 B, or 255 Decimal. These are 8 bit registers A, B, C, D, E, H, and L.An 8 bit register is loaded or initialized with the MVI instruction. Variations on this are MVI A, byte ; MVI B, byte; etc.The coding for MVI B, 4CH would be 06 4C, a 2 byte instruction.You can copy (duplicate) the contents of one 8 bit register to another 8 bit register with the MOV instruction. The format for this is MOV to, from. An example is MOV A, E with the one byte code of 7BH. Here the contents of E is duplicated in the A register.Certain of these registers can be used as pairs. These are BC, DE, and HL. A register pair acts as though it is a 16 bit register. A 16 bit register can hold a quantity as large as 0FFFF H, 65535 Decimal, or 1111111111111111 B. These 16 bit registers are known by their first letter only. BC is designated B, DE is designated D, HL is designated as H.The register pairs are initialized with the LXI instruction. LXI B, 1234H would load the B register with 12H and the C register with 34H. The coding for this would be 01 34 12. 01 represents LXI B, with 3412 being the data in Intel byte swapped form. Of course, you could also initialize BC with separate MVI B, 12H and MVI C, 34H instructions.Review:Load an 8 Bit register, use MVI r, byte. (r = A,B,C,D,E,H,L)Load a 16 Bit register with LXI rp, 2 bytes. (rp = B, D, H)Duplicate an 8 bit register into another with MOV r1, r2.The Increment ( INR, INX) instructions are used to add 1 to the contents of a register. INR is for the 8 bit registers, INX is for the 16 bit paired registers. INR C adds one to the contents of C. INX B adds 1 to the contents of the BC 16 bit register pair.The Decrement (DCR, DCX) instructions work the same way except 1 is subtracted.Example: If DE contains 2237H and you INX D, DE gets one added to become 2238H. D still contains 22 and E contains 38.If you now do INR D followed by DCR E, the new contents of DE is 2337. The registers were treated separately since we used the 8 bit versions of increment and decrement.The Zero Flag, is a part of the flag (F) register. When an 8 bit register hits zero as the result of an increment, decrement, arithmetic or logical operation, the zero flag becomes active. This allows some decision making to be done by the JNZ or JZ or CNZ or CZ instructions.For example, if the H register contains 01 and we decrement with DCR H, the register now contains 0 and the zero flag goes active. We make use of this with the conditional jump and conditional call instructions. These are JZ, jump if zero, JNZ, jump if not zero, etc.In the delay loop discussed in class, the conditional jump depends on the B register being zero or non zero depending on your viewpoint.

THE next instruction is here if B=0 and we don't do the jump back up to loop.Not all instructions have an effect on the ZERO flag. DCR, INR, ORA, ANA, ADD, SUB, XRA, CMP, CMA all work because they are 8 bit instructions.Simply loading a register does not affect the zero flag. For instance, MVI B, 0 does not set the zero flag into operation. MOV instructions don't affect the zero flag either.Certain 16 bit instructions also don't do anything to the zero flag. These include DCX, INX, LXI. We use the 16 bit instructions in longer delay loops. For example, if we write a delay program using the BC register pair, we get a whole lot more delay since a double register can hold a much larger number. 65535 in fact. That's 0FFFFH. ( 4 F's )A double register delay loop requires aTRICKto discover if the pair is empty. JNZ isn't good enough by itself to work with a 16 bit decrement (DCX).......A 16 bit double register delay loop looks like this:

A 16 bit Decrement (DCX) or Increment (INX) doesn't affect the zero flag so we cannot use the JNZ instruction directly. We must use this software test or trick to discover if we have emptied BC and finished 65535 decrements.The idea behind the 'trick' is that if we OR B with C the result will only be zero if both B and C are already zero. Since there is no instruction that directly OR's B with C, we move one of these into A and use the ORA instruction to accomplish OR ing B with C. That's how we learn if BC is zero having done 65535 decrements.The 16 bit delay loop provides much more delay than the 8 bit delay loop. 255 decrements vs 65535 decrements. We will be using both of these programming structures. Memorize them; study them to be sure you understand how they operate.SUBROUTINESSubroutines are easy with the CALL and the RET instructions. A delay subroutine is easily created by beginning with the NAME and ending with the RET instruction. The main program then CALLs the subroutine and return is automatic when the job is done. One thing though......The Stack Pointer register (SP) must be initialized for any CALL or RET instruction to work reliably. This is done with the LXI SP instruction. We load the SP with an address from valid memory, away from our software, for use by the CPU. The processor will store return addresses in its stack area. A counter program that uses a subroutine would look like this:

ASSEMBLY LANGUAGE PROGRAMMING EXAMPLES:

Addition Programs

Address of the memory locationHex codeLabelMnemonicsComments

Op-codeOperand

800021,00,90LXIH, 9000Initialise memory pointer to point the first data location 9000.

80033EMVIA, 00Clear accumulator

800400

800586ADDA, MThe first number is added to accumulator [A] [A] + M

800623INXHIncrement the memory pointer to next location of the Data.

800786ADDA, MThe 2nd number is added to contents of accumulator

800832STA9002The contents of accumulator are stored in memory location 9002.

800902

800A90

800B76HLTStop the execution

Example 1: Addition of two 8-bit numbers whose sum is 8-bits.

Explanation: This assembly language program adds two 8-bit numbers stored in two memory locations .The sum of the two numbers is 8-bits only. The necessary algorithm and flow charts are given below.

ALGORITHM:Step1. : Initialize H-L pair with memory address XX00 (say: 9000).Step2. : Clear accumulator.Step3. : Add contents of memory location M to accumulator.Step4. : Increment memory pointer (i.e. XX01).Step5. : Add the contents of memory indicated by memory pointer to accumulator.Step6. : Store the contents of accumulator in 9002.Step7. : Halt PROGRAM:

Ex: Input: Ex: (i) 9000 29 H Ex :(ii) 9000 49 H 9001 16 H 9001 32 H

Result: Ex: (i) 9002 3F H Ex :( ii) 9002 7B

Flow Chart StartClear Accumulator(00) AStopCopy the contents of Reg. A to memory location XX02

Initialise H-L Pair with XX00

Add contents of M to Accumulator

# Increment memory pointer(XX01) # Add contents of M to A

Fig 3.18

Example 2: Addition of two 8-bit numbers whose sum is 16 bits.

Explanation: The first 8-bit number is stored in one memory location (say 8500) and the second 8-bit number is stored in the next location (8501).Add these two numbers and check for carry. Store the LSB of the sum in one memory location (8502) and the MSB (carry) in the other location(8503).

ALGORITHM:

Step1. : Initialize H-L pair with memory address X (say: 8500).Step2. : Clear accumulator.Step3. : Add contents of memory location M to accumulator.Step4. : Increment memory pointer (i.e. 8501).Step5. : Add the contents of memory indicated by memory pointer to accumulator.Step6. : Check for CarryStep 7 : Store the sum in 8502.Step8 : Store the Carry in 8503 locationStep 9 : Halt

Start

Flow Chart Initialise H-L Pair with XX00Clear Accumulator(00) AAdd contents of M to Accumulator# Increment memory pointer(XX01) & # Add contents of M to AStore the sum in the location xx02 Is Carry exists ?

YesStore carry in the XX03 location

No

Store Zero in the XX03 location

Stop

Fig 3.19

PROGRAM:

Address of the memory locationHex codeLabelMnemonicsComments

Op-codeOperand

800021,00,85LXIH, 8500 HInitialise memory pointer to point the first data location 9000.

80033EMVIA,00Clear accumulator

800400

800586ADDA, MThe first number is added to accumulator [A] [A]+M

80060EMVIC,00Initial value of Carry is 0

800700

800823INXHIncrement the memory pointer to next location of the Data.

800986ADDA, MThe 2nd number is added to contents of accumulator

800A32JNCFWDIs Carry exists ? No,go to the label FWD

800B0E

800C80

800D0CINRCMake carry =1

800E32FWDSTA8502 HThe sum is stored in memory location 8502.

800F02

801085

801179MOVA,C

801232STA8503 HStore the carry at 8503 location

801303

801485

801576HLTStop the execution

Ex: Input: Ex : 8500 97 H RESULT: 8502 32 H 8501 98H 8503 -- 01 H

Example 3: Decimal addition of two 8-bit numbers whose sum is 16 bits.

Explanation: Decimal addition of two 8-bit numbers is same as that of two 8-bit numbers program. Except that the use of DAA instruction. The first 8-bit number is stored in one memory location (say 8500) and the second 8-bit number is stored in the next location(8501).Add these two numbers and use the DAA instruction to get the result in decimal. Also check for carry. Store the LSB of the sum in one memory location(8502) and the MSB (carry) in the other location(8503).

ALGORITHM:Step1. : Initialize H-L pair with memory address XXXX (say: 8500).Step2. : Clear Carry register C.Step3. : Move contents of memory location M to accumulator.Step4. : Increment memory pointer (i.e. 8501).Step5. : Add the contents of memory indicated by memory pointer to accumulator.Step6. : Apply the instruction DAA (Decimal adjust after addition)Step7: Check for CarryStep8: Store the sum in XX02.Step9: Store the Carry in XX03 locationStep10: Halt

Flow Chart Start

Initialize H-L Pair with XX00Apply DAA instruction to convert Hex data to decimal formClear Carry register(00) CAdd contents of M to Accumulator# Increment memory pointer(XX01) & # Add contents of M to A

Store the sum in the location XX02

Is Carry Exists?

Yes Stores carry in the XX03 location

No Store Zero in the XX03 location

Stop

Fig .20PROGRAM

Address of the memory locationHex codeLabelMnemonicsComments

Op-codeOperand

800021, 00,85LXIH, 8500 HInitialise memory pointer to point the first data location 9000.

80030EMVIC, 00Clear accumulator

800400

80057EMOVA, MThe first number is added to accumulator [A] [A]+M

800623INXHIncrement the memory pointer to next location of the Data.

800786ADDA, MThe 2nd number is added to contents of accumulator

800827DAA

8009D2JNCFWDIs Carry exists? No, go to the label FWD

0D

80

800C0CINRCMake carry =1

800D32FWDSTA8502 HThe contents of accumulator are stored in memory location 8502.

800E02

800F85

801079MOVA, CCarry is moved to accumulator

801132STA8503 HA Carry is stored in the location 8503

801203

801385

801476HLTStop the execution

Ex: Input: Ex : 8500 67 D RESULT: 8502 52 D 8501 85 D 8503 01 (Carry)

Stack and Subroutines

Stack is a set of memory locations in the Read/Write memory which is used for temporary storage of binary information during the execution of a program. It is implemented in the Last-in-first-out (LIFO) manner. i.e., the data written first can be accessed last; One can put the data on the top of the stack by a special operation known as PUSH. Data can be read or taken out from the top of the stack by another special instruction known as POP. Stack is implemented in two ways. In the first case, a set of registers is arranged in a shift register organization. One can PUSH or POP data from the top register. The whole block of data moves up or down as a result of push and pop operations respectively. In the second case, a block of RAM area is allocated to the stack. A special purpose register known as stack pointer (SP) points to the top of the stack. Whenever the stack is empty, it points to the bottom address. If a PUSH operation is performed, the data are stored at the location pointed to by SP and it is decremented by one. Similarly if the POP operation is performed, the data are taken out of the location pointed at by SP and SP is incremented by one. In this case the data do not move but SP is incremented or decremented as a result of push or pop operations respectively.

Application of Stack: Stack provides a powerful data structure which has applications in many situations. The main advantage of the stack is that, we can store data (PUSH) in it without destroying previously stored data. This is not true in the case of other registers and memory locations. Stack operations are also very fast, the stack may also be used for storing local variables of subroutine and for the transfer of parameter addresses to a subroutine. This facilitates the implementation of re-entrant subroutines which is a very important software property. The disadvantage is, as the stack has no fixed address, it is difficult to debug and document a program that uses stack.

Stack operation: Operations on stack are performed using the two instructions namely PUSH and POP. The contents of the stack are moved to certain memory locations after PUSH instruction. Similarly, the contents of the memory are transferred back to registers by POP instruction. For example let us consider a Stack whose stack top is 4506 H. This i