EE534 VLSI Design System Summer 2004 Lecture 06: Static CMOS inverter (CHAPTER 5)
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Transcript of EE534 VLSI Design System Summer 2004 Lecture 06: Static CMOS inverter (CHAPTER 5)
EE534VLSI Design System
Summer 2004
Lecture 06: Static CMOS inverter
(CHAPTER 5)
Review: CMOS Inverter VTC
0
0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin (V)
Vou
t (V
)
NMOS offPMOS res
NMOS satPMOS res
NMOS satPMOS sat
NMOS resPMOS sat NMOS res
PMOS off
VDD
Vout
CL
NMOS offPMOS in non sat
NMOS in sat
PMOS in non sat
NMOS in sat
PMOS in sat
NMOS in non sat
PMOS in sat
NMOS in nonsat
PMOS off
Vout = VDS
Dra
in c
urre
nt I D
S
Vin=2V
VCC
Vin=1V
Vin=3V
Vin=4V
Review: CMOS Inverter: VTC
Vout = VDS
Dra
in c
urre
nt I D
S
Vin=2V
VCC
Vin=1V
Vin=3V
Vin=4V
Vou
t
Vin1 2 3 40
VCC
PMOS NMOS
• Output goes completely to Vcc and Gnd• Sharp transition region
CMOS Inverter: Switch Model of Dynamic Behavior
VDD
Rn
Vout
CL
Vin = V DD
VDD
Rp
Vout
CL
Vin = 0
Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn)
CMOS inverter operation
NMOS transistor: Cutoff if Vin < VTN
Linear if Vout < Vin – VTN
Saturated if Vout > Vin – VTN
PMOS transistor Cutoff if (Vin-VCC) < VTP → Vin < Vcc+VTP
Linear if (Vout-VCC)>Vin-Vcc-VTP → Vout>Vin - VTP
Sat. if (Vout-VCC)<Vin-Vcc-VTP → Vout < Vin-VTP
Vin Vout
Vcc
CMOS Static Inverter design
consideration
CMOS inverter design consideration
The CMOS inverter usually design to have, (i) VTN =|VTP|(ii) K´n(W/L)=K´p(W/L)
But K´n> K´p (because n>p)How equation (ii) can be satisfied?This can be achieved if width of the PMOS is made
two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.
VCC
VCC
Vin
Vout
kp=kn
kp=5kn
kp=0.2kn
• Increase W of PMOS kp increases VTC moves to right
• Increase W of NMOS kn increases VTC moves to left
• For VTH = Vcc/2 kn = kp
Wn 2Wp
CMOS inverter design consideration (cont.)
CMOS inverter design consideration (cont.)
VscmVScm
LWLW
p
n
n
p2
2
580/230
np LW
LW
5.2
1
invertersymmetricn
pR k
kK
CMOS inverter design consideration (cont.)
Impact of Process Variation on VTC Curve
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0.5
1
1.5
2
2.5
0 0.5 1 1.5 2 2.5
Vin (V)
Vou
t (V
)
Nominal
Good PMOSBad NMOS
Bad PMOSGood NMOS
Process variations (mostly) cause a shift in the switching threshold
Effects of Vth adjustment Result from changing kp/kn ratio:
Inverter threshold VTH Vcc/2 Rise and fall delays unequal Noise margins not equal
Reasons for changing inverter threshold Want a faster delay for one type of
transition (rise/fall) Remove noise from input signal:
increase one noise margin at expense of the other
Symmetrical properties of the CMOS inverter
Example:
Definition of Noise Margins
VIH
VIL
UndefinedRegion
"1"
"0"
VOH
VOL
NMH
NML
Gate Output Gate Input
Noise Margin High
Noise Margin Low
Concept of Noise Margins
NML=VIL-VOL (noise margin for low input)NMH=VOH-VIH (noise margin for high input)
VI
ILOLILL VVVNM ILIHCCIHOHH VVVVVNM
Noise margin calculations
Vout = VDS
Dra
in c
urre
nt I D
S
Vin=2V
VCC
Vin=1V
Vin=3V
Vin=4V
CMOS inverter: VIL
KCL: IDp=IDn
Differentiate and set dVout/dVin to –1
Solve simultaneously with KCL to find VIL
2,,,0,
2,0, 2
22 pDSpDSpTpGSp
nTnGSn VVVV
kVVk
2,0
2,0 2
22 CCoutCCoutpTCCinp
nTinn VVVVVVV
kVVk
in
outCCoutCCout
in
outpTCCinpnTinn dV
dVVVVVdVdVVVVkVVk ,0,0
CCpTILoutpnTILn VVVVkVVk ,0,0 2
R
nTRCCpToutIL k
VkVVVV
1
2 ,0,0 p
nR k
kk
CMOS inverter: VIH
KCL:
Differentiate and set dVout/dVin to –1
Solve simultaneously with KCL to find VIH
2,0,2
,,,0, 22
2 pTpGSp
nDSnDSnTnGSn VV
kVVVVk
2,02
,0 22
2 pTCCinp
outoutnTinn VVV
kVVVVk
pTCCinpin
outoutout
in
outnTinn VVVk
dVdVVV
dVdVVVk ,0,0
pTCCIHppTIHoutn VVVkVVVk ,0,02
R
nToutRpTCCIH k
VVkVVV
1
2 ,0,0
p
nR k
kk
CMOS inverter: VIL and VIH for Ideal VTH
(Symmetrical, Kn=Kp) Assuming VT0,n=-VT0,p, and kR = 1,
02381
TCCIL VVV
02581
TCCIH VVV
DDIHIL VVV
ILOLILL VVVNM
ILIHCCIHOHH VVVVVNM
(symmetrical inverter)
Example 5.4
CMOS inverter: VTH
KCL:
Solve for VTH = Vin = Vout
2,0,2
,0, 22 pTpGSp
nTnGSn VV
kVVk
2,02
,0 22 pTCCinp
nTinn VVV
kVVk
R
pTCCR
nT
TH
k
VVk
VV
11
1,0,0
p
nR k
kk
CMOS inverter: Ideal VTH (Symmetrical, Kn=Kp)
Ideally, Vth = VCC/2
Assuming VT0,n = VT0,p,
R
pTCCR
nT
TH
k
VVk
VV
11
1,0,0
p
nR k
kk
2
,0
,0, 2
2
nTCC
pTCCidealR VV
VVk
1, idealRk
5.2
p
n
n
p
LWLW
nn LW
LW
5.2
For ideal symmetrical inverter required that