EE4800 CMOS Digital IC Design & Analysis
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Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.11
EE4800 CMOS Digital IC Design & Analysis
Lecture 4 DC and Transient Responses, Circuit Delays
Zhuo Feng
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.22
Outline■Pass Transistors■DC Response■Logic Levels and Noise Margins■Transient Response■RC Delay Models■Delay Estimation
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.33
Activity1) If the width of a transistor increases, the current will
increase decrease not change 2) If the length of a transistor increases, the current will
increase decrease not change3) If the supply voltage of a chip increases, the
maximum transistor current willincrease decrease not change
4) If the width of a transistor increases, its gate capacitance willincrease decrease not change
5) If the length of a transistor increases, its gate capacitance willincrease decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each transistor willincrease decrease not change
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.44
Activity1) If the width of a transistor increases, the current will
increase decrease not change 2) If the length of a transistor increases, the current will
increase decrease not change3) If the supply voltage of a chip increases, the
maximum transistor current willincrease decrease not change
4) If the width of a transistor increases, its gate capacitance willincrease decrease not change
5) If the length of a transistor increases, its gate capacitance willincrease decrease not change
6) If the supply voltage of a chip increases, the gate capacitance of each transistor willincrease decrease not change
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.55
Pass Transistors■ We have assumed source is grounded■ What if source > 0?
► e.g. pass transistor passing VDD
■ Vg = VDD
► If Vs > VDD-Vt, Vgs < Vt
► Hence transistor would turn itself off
■ NMOS pass transistors pull no higher than VDD-Vtn
► Called a degraded “1”
► Approach degraded value slowly (low Ids)
■ PMOS pass transistors pull no lower than Vtp
VDDVDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.66
Pass Transistor Ckts
VDDVDD Vs = VDD-Vtn
VSS
Vs = |Vtp|
VDD
VDD-Vtn VDD-Vtn
VDD-Vtn
VDD
VDD VDD VDD
VDD
VDD-Vtn
VDD-2Vtn
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.77
DC Response■DC Response: Vout vs. Vin for a gate
■Ex: Inverter►When Vin = 0 -> Vout = VDD
►When Vin = VDD -> Vout = 0
► In between, Vout depends on
transistor size and current►By KCL, must settle such that
Idsn = |Idsp|
►We could solve equations►But graphical solution gives more insight
Idsn
Idsp Vout
VDD
Vin
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.88
Transistor Operation■ Current depends on region of transistor
behavior
■ For what Vin and Vout are NMOS and PMOS in► Cutoff?► Linear?► Saturation?
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.99
NMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Idsn
Idsp Vout
VDD
Vin
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1010
NMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn
Vdsn < Vgsn – Vtn
Vgsn > Vtn
Vdsn > Vgsn – Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1111
NMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn
Vin < Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
Idsn
Idsp Vout
VDD
Vin
Vgsn = Vin
Vdsn = Vout
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1212
PMOS Operation
Cutoff Linear Saturated
Vgsp > Vgsp <
Vdsp >
Vgsp <
Vdsp <
Idsn
Idsp Vout
VDD
Vin
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1313
PMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Idsn
Idsp Vout
VDD
Vin
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1414
PMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp
Vdsp > Vgsp – Vtp
Vgsp < Vtp
Vdsp < Vgsp – Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1515
PMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
Idsn
Idsp Vout
VDD
Vin
Vgsp = Vin - VDD
Vdsp = Vout - VDD
Vtp < 0
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1616
I-V Characteristics■Make PMOS is wider than NMOS such
that n = pVgsn5
Vgsn4
Vgsn3
Vgsn2Vgsn1
Vgsp5
Vgsp4
Vgsp3
Vgsp2
Vgsp1
VDD
-VDD
Vdsn
-Vdsp
-Idsp
Idsn
0
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1717
Current vs. Vout, Vin
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1818
Load Line Analysis
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
■For a given Vin:►Plot Idsn, Idsp vs. Vout
►Vout must be where |currents| are equal in
Idsn
Idsp Vout
VDD
Vin
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.1919
Load Line Analysis
Vin0
Vin0
Idsn, |Idsp|
VoutVDD
■Vin = 0
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2020
Load Line Analysis
Vin1
Vin1Idsn, |Idsp|
VoutVDD
■Vin = 0.2VDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2121
Load Line Analysis
Vin2
Vin2
Idsn, |Idsp|
VoutVDD
■Vin = 0.4VDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2222
Load Line Analysis
Vin3
Vin3
Idsn, |Idsp|
VoutVDD
■Vin = 0.6VDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2323
Load Line Analysis
Vin4
Vin4
Idsn, |Idsp|
VoutVDD
■Vin = 0.8VDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2424
Load Line Analysis
Vin5Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
■Vin = VDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2525
Load Line Summary
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
Idsn, |Idsp|
VoutVDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2626
DC Transfer Curve■Transcribe points onto Vin vs. Vout plot
Vin5
Vin4
Vin3
Vin2Vin1
Vin0
Vin1
Vin2
Vin3Vin4
VoutVDD
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2727
Operating Regions■Revisit transistor operating regions
CVout
0
Vin
VDD
VDD
A B
DE
Vtn VDD/2 VDD+Vtp
Region NMOS PMOS
A Cutoff Linear
B Saturation Linear
C Saturation Saturation
D Linear Saturation
E Linear Cutoff
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2828
Beta Ratio■ If p / n 1, switching point will move from
VDD/2
■ Called skewed gate■ Other gates: collapse into equivalent inverter
Vout
0
Vin
VDD
VDD
0.51
2
10p
n
0.1p
n
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.2929
Noise Margins■How much noise can a gate input see
before it does not recognize the input?
IndeterminateRegion
NML
NMH
Input CharacteristicsOutput Characteristics
VOH
VDD
VOL
GND
VIH
VIL
Logical HighInput Range
Logical LowInput Range
Logical HighOutput Range
Logical LowOutput Range
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3030
Logic Levels■ To maximize noise margins, select logic levels
at ► unity gain point of DC transfer characteristic
VDD
Vin
Vout
VOH
VDD
VOL
VIL VIHVtn
Unity Gain PointsSlope = -1
VDD-|Vtp|
p/n > 1
Vin Vout
0
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3131
Transient Response■ DC analysis tells us Vout if Vin is constant
■ Transient analysis tells us Vout(t) if Vin(t) changes
► Requires solving differential equations
■ Input is usually considered to be a step or ramp
► From 0 to VDD or vice versa
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3232
Inverter Step Response■ Ex: find step response of inverter driving load
cap0
0
( )
( )
( )
( )
ou
DDin
t
out
u t t V
d
d
t
t t
V t
V
V
t
Vin(t) Vout(t)Cload
Idsn(t)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3333
Inverter Step Response■ Ex: find step response of inverter driving load
cap0
0(
( ))
(
(
)
)
DD
Do
i
D
o t
n
ut
u
V t
u t t V
V
d
d
t
t
V
V
t
t
Vin(t) Vout(t)Cload
Idsn(t)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3434
Inverter Step Response■ Ex: find step response of inverter driving load
cap
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
0
( ) DD tout
ou
ds
t DD t
nI t V V
VV V
V
t t
Vin(t) Vout(t)Cload
Idsn(t)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3535
Inverter Step Response■ Ex: find step response of inverter driving load
cap
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
0
2
2
0
2)
)
( ( )
( DD DD t
DD
out
outout out D t
n
t
ds
D
I V
t t
V V V V
V V V VV
t
V t V t
Vin(t) Vout(t)Cload
Idsn(t)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3636
Inverter Step Response■ Ex: find step response of inverter driving load
cap
0
0
( )
( )
( )
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
t t
V t
V
d
dt C
t
I t
0
2
2
0
2)
)
( ( )
( DD DD t
DD
out
outout out D t
n
t
ds
D
I V
t t
V V V V
V V V VV
t
V t V t
Vout(t)
Vin(t)
t0t
Vin(t) Vout(t)Cload
Idsn(t)
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3737
Delay Definitions■ tpdr: rising propagation delay
► From input to rising output crossing VDD/2
■ tpdf: falling propagation delay► From input to falling output crossing VDD/2
■ tpd: average propagation delay► tpd = (tpdr + tpdf)/2
■ tr: rise time► From output crossing 0.2 VDD to 0.8 VDD
■ tf: fall time► From output crossing 0.8 VDD to 0.2 VDD
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3838
Delay Definitions■ tcdr: rising contamination delay
► From input to rising output crossing VDD/2
■ tcdf: falling contamination delay► From input to falling output crossing VDD/2
■ tcd: average contamination delay► tpd = (tcdr + tcdf)/2
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.3939
Simulated Inverter Delay■ Solving differential equations by hand is too hard■ SPICE simulator solves the equations numerically
► Uses more accurate I-V models too!
■ But simulations take time to write
(V)
0.0
0.5
1.0
1.5
2.0
t(s)0.0 200p 400p 600p 800p 1n
tpdf = 66ps tpdr = 83psVin Vout
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4040
Delay Estimation■ We would like to be able to easily estimate delay
► Not as accurate as simulation► But easier to ask “What if?”
■ The step response usually looks like a 1st order RC response with a decaying exponential.
■ Use RC delay models to estimate delay► C = total capacitance on output node► Use effective resistance R► So that tpd = RC
■ Characterize transistors by finding their effective R
► Depends on average current as gate switches
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4141
Effective Resistance■ Shockley models have limited value
► Not accurate enough for modern transistors► Too complicated for much hand analysis
■ Simplification: treat transistor as resistor► Replace Ids(Vds, Vgs) with effective resistance R
▼ Ids = Vds/R
► R averaged across switching of digital gate
■ Too inaccurate to predict current at any given time
► But good enough to predict RC delay
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4242
RC Delay Model■ Use equivalent circuits for MOS transistors
► Ideal switch + capacitance and ON resistance► Unit NMOS has resistance R, capacitance C► Unit PMOS has resistance 2R, capacitance C
■ Capacitance proportional to width■ Resistance inversely proportional to width
kg
s
d
g
s
d
kCkC
kCR/k
kg
s
d
g
s
d
kC
kC
kC
2R/k
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4343
RC Values■ Capacitance
► C = Cg = Cs = Cd = 2 fF/m of gate width
► Values similar across many processes
■ Resistance► R 6 K*m in 0.6um process► Improves with shorter channel lengths
■ Unit transistors► May refer to minimum contacted device (4/2 )► Or maybe 1 m wide device► Doesn’t matter as long as you are consistent
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4444
Inverter Delay Estimate■ Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1A
Y
C
2C
C
2C
C
2C
RY
2
1
Delay = 6RC
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4545
Delay Model Comparison
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4646
Example: 3-input NAND■ Sketch a 3-input NAND with transistor widths
chosen to achieve effective rise and fall resistances equal to a unit inverter (R).
3
3
222
3
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4747
3-input NAND Caps■ Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
3
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4848
3-input NAND Caps■ Annotate the 3-input NAND gate with gate and
diffusion capacitance.
2 2 2
3
3
33C
3C
3C
3C
2C
2C
2C
2C
2C
2C
3C
3C
3C
2C 2C 2C
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.4949
3-input NAND Caps■ Annotate the 3-input NAND gate with gate and
diffusion capacitance.
9C
3C
3C3
3
3
222
5C
5C
5C
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5050
A B C
Inv 1 Inv 2
( ) 1
t
RCV t e
R
C
V(t)1v
What is the time constant for more complex circuits?
Time Constant=RC
Elmore Delay
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5151
Elmore Delay (Cont.)■ ON transistors look like resistors■ Pullup or pulldown network modeled as RC ladder■ Elmore delay of RC ladder
R1 R2 R3 RN
C1 C2 C3 CN
nodes
1 1 1 2 2 1 2... ...
pd i to source ii
N N
t R C
RC R R C R R R C
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5252
,T R Cdelay i downstream ii on path
Tdelay,4=R1(C1+C2+C3+C4+C5)+R2(C2+C4+C5)+R4C4
Elmore Delay (Cont’d)
Resistance-oriented Formula:
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5353
Example: 2-input NAND■ Estimate worst-case rising and falling delay of
2-input NAND driving h identical gates.
h copies2
2
22
B
Ax
Y
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5454
Example: 2-input NAND■ Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
h copies6C
2C2
2
22
4hC
B
Ax
Y
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5555
Example: 2-input NAND■ Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
h copies
6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CY
6 4pdrt h RC
RisingDelayRisingDelay
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5656
Example: 2-input NAND■ Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
h copies
6C
2C2
2
22
4hC
B
Ax
Y
2 2 22 6 4 7 4R R Rpdft C h C h RC
(6+4h)C2CR/2
R/2x YFallingDelayFallingDelay
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5757
Delay Components■ Delay has two parts
► Parasitic delay▼ 6 or 7 RC▼ Independent of load
► Effort delay▼ 4h RC▼ Proportional to load capacitance
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5858
Contamination Delay■ Best-case (contamination) delay can be
substantially less than propagation delay.■ Ex: If both inputs fall simultaneously
6C
2C2
2
22
4hC
B
Ax
Y
R
(6+4h)CYR
3 2cdrt h RC
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.5959
■ We assumed contacted diffusion on every s / d.■ Good layout minimizes diffusion area■ Ex: NAND3 layout shares one diffusion contact
► Reduces output capacitance by 2C► Merged un-contacted diffusion might help too
7C
3C
3C3
3
3
222
3C
2C2C
3C3C
IsolatedContactedDiffusionMerged
UncontactedDiffusion
SharedContactedDiffusion
Diffusion Capacitance
Z. Feng MTU EE4800 CMOS Digital IC Design & Z. Feng MTU EE4800 CMOS Digital IC Design & AnalysisAnalysis
4.4.6060
Layout Comparison■ Which layout is better?
AVDD
GND
B
Y
AVDD
GND
B
Y