Ee325 cmos design lab 3 report - loren k schwappach

EE325, CMOS Design, Lab 3: NMOS Inverter Characteristics

1

Colorado Technical University

P-Spice, IRF-150 Power MOSFET Inverter Analysis

Lab 3 Report Submitted to Professor R. Hoffmeister

In Partial Fulfillment of the Requirements for EE 325-CMOS Design

By Loren Karl Robinson Schwappach

Student Number: 06B7050651

Colorado Springs, Colorado Due: 5 May 2010

Completed: 19 May 2010


2

Table of Contents

Lab Objectives ........................................................................................................................................................................................ 3

Requirements and Design Approaches/Trade-Offs................................................................................................................... 3

Characteristic Curves for the IRF-150 Power MOSFET ............................................................................................................ 4

Circuit Layout......................................................................................................................................................................... 4

PSpice Simulation Results.............................................................................................................................................. 5-6

Voltage Transfer Function of the IRF-150 Power MOSFET .................................................................................................... 6

Circuit Layout......................................................................................................................................................................... 7

PSpice Simulation Results.................................................................................................................................................. 8

Truth Table ............................................................................................................................................................................. 8

Power Consumption of the IRF-150 Power MOSFET................................................................................................................ 9

PSpice Simulation Results.................................................................................................................................................. 9

Small Signal Characteristics of the IRF-150 Power MOSFET............................................................................................... 10

Circuit Layout...................................................................................................................................................................... 10

PSpice Simulation Results............................................................................................................................................... 10

Frequency Response of the IRF-150 Power MOSFET ............................................................................................................ 11

Circuit Layout...................................................................................................................................................................... 11


Propagation Delay and Rise/Fall Times of the IRF-150 Power MOSFET ........................................................................ 12

Circuit Layout...................................................................................................................................................................... 12


Digital Frequency Response of the IRF-150 Power MOSFET .............................................................................................. 14

PSpice Simulation Results......................................................................................................................................... 14-15

Maximum Frequency of the circuit using the IRF-150 Power MOSFET .......................................................................... 16


Summary of Results ........................................................................................................................................................................... 17

Conclusion and Recommendations .............................................................................................................................................. 17


3

Lab Objectives

This objective of this lab is to introduce the user into the use and features of one of the most

popular analog and digital simulation software packages, PSpice (specifically OrCAD Capture

CIS Demo Version 15.7). As an added bonus the user should complete this lab assignment with

a greater understanding of the common characteristics of a commercially available n-channel

MOSFET. This lab is designed around the IRF-150 Power MOSFET. The lab will evaluate the

inverter characteristics of the IRF-150 by generating device characteristic curves, voltage

transfer function, frequency response diagram (bode plot), and time domain analysis of specific

frequencies needed to compute the IRF-150’s characteristic rise/fall times, and propagation

delays.

Requirements and Design Approaches / Trade-offs

There are no specific design requirements for this project since it is not a design project, but a

PSpice learning lab. The primary objective of this lab is to learn the procedures and methods in

using the PSpice simulation software to identify and analyze key characteristics of the IRF-150

inverter circuit. This circuit and data collected through this lab will be compared against in later

labs.


4

Characteristic Curves for the IRF-150 Power MOSFET

In order to begin analyzing the IRF-150 inverter, you must have OrCAD 15.7 Demo installed (or a later, working variant). Next open OrCAD Capture CIS and create a new project using Analog / Mixed (A/D). After the project space is ready a design schematic should be built as shown in figure 1 below. Building a schematic is as simple as laying down parts and connecting the components with wire. The main PSpice parts/components we will use in this lab are (IRF-150, VDC, VAC, VPULSE, 0Ground, C/ANALOG, R/ANALOG, and Net Alias). Once you have everything pieced together, you are ready to run a PSpice simulation. First, create a new simulation profile for testing the transistors Id-Vd relationships. Next, set the simulation settings to use a DC Sweep, with a Primary Sweep of “Vdrain” from 0 V to 10 V in small 1 mV increments (figure 2), and a Secondary Sweep of “Vgate” from 0 V to 10 V (Note, 2 V to 10 V also works) in 1 V increments (figure 3). I also simulated sweeping Primary and Drain from 0 V to 5 V for future inverter comparisons. The results of these simulations are seen in figures 4 and 5.

Figure 1: PSpice circuit used for IRF-150 Id-Vd curves.

M1

IRF150

Vdrain

5Vdc

Circuit used for generating the IRF-150

transistor curves (Id-Vd curves)

Vgate

5Vdc

0

0

0


5

Figure 4: Characteristic curves for IRF-150. (0-5V Sweeps).

V_Vdrain

0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

ID(M1)

0A

4.0A

8.0AI

D

r

a

i

n

Secondary Sweep: VDrain (0-5 Vdc)

Primary Sweep: VDrain (0-5 Vdc)

Characteristic Curves for the IRF-150

Note: V_Vgate < 3V curves are not visableV_Vgate = 3V

V_Vgate = 4V

V_Vgate = 5V

Figure 2: DC Sweep, Primary Sweep Config. Figure 3: DC Sweep, Secondary Sweep Config.


6

Voltage Transfer Function for the IRF-150 Power MOSFET

To generate the voltage transfer function (Vout vs. Vin) of the IRF-150 Power MOSFET, the circuit design was updated to include a 1 kΩ resister after the VDC source “Vdrain”, and a 1 pF capacitor after the 1 kΩ resister going to ground. Two net aliases “Vout” and “Vin” were then added until the circuit finally matched the circuit shown by figure 6. Next the circuit simulation settings were again adjusted. After the Secondary Sweep was removed, the Primary Sweep was updated to sweep “Vgate” from 0 V to 5 V in small 1mV increments (figure 7). The new simulation was run with the results shown by the bottom half of figure 8. You may need to add a trace of “V(Vout)” if you didn’t attach a voltage probe to Vout. Next, a line with a slope of 1 was drawn originating from (0 V, 0 V) to (4 V, 4 V). The intersection of this line with the voltage transfer function graph of V(Vout) was noted as the IRF-150 Power MOSFET’s logic threshold or switching point. This threshold voltage is the point where Vin = Vout, and was determined to be approximately 2.868 V. Next a new plot was added to graph the slope (derivative) of “Vout” (Top half of figure 8). Creating a new plot is as simple as clicking plot/new plot and giving the new plot a trace (In this case d(V(Vout))). The points where the new slope = -1 are used to define the noise margins of this inverter. An easy way to find these locations is by using the search command and typing “search forward level(-1)”. Using this technique twice to find both

V_Vdrain

0V 1V 2V 3V 4V 5V 6V 7V 8V 9V 10V

ID(M1)

0A

40A

80AI

D

r

a

i

n

V_Vgate = 4V

V_Vgate = 5V

V_Vgate = 6V

V_Vgate = 7V

V_Vgate = 8V

V_Vgate = 9V

V_Vgate = 10V

Note: V_Vgate <= 3V curves are not visable

Secondary Sweep: VDrain (0-10 Vdc)

Primary Sweep: VDrain (0-10 Vdc)

Characteristic Curves for the IRF-150

Figure 5: Characteristic curves for IRF-150. (0-10V Sweeps).


7

locations where the slope = -1 the following could be defined. Once found you can identify the specific x-value with the “search forward xvalue(###)” command, where ### is the x-value you are searching for. After adding these coordinates the following data was obtained.

VIH = minimum HIGH input voltage = 2.8965 V VIL = maximum LOW input voltage = 2.8311 V

VOH = minimum HIGH output voltage = 4.9886 V VOL = maximum LOW output voltage = 32.908 mV

Using these values the noise margins of the IRF-150 Power MOSFET were calculated as:

Noise Margin Low = NML = VIL – VOL = 2.798 V Noise Margin High = NMH = VOH – VIH = 2.092 V

For an Ideal Inverter:

NML = VDD/2 – 0 = 2.5 V NMH = VDD – VDD/2 = 2.5 V

So IRF-150 NML is approx. +12% of Ideal, and IRF-150 NMH is approx. -16% of Ideal.

M1

IRF150

Circuit used for generating the IRF-150

voltage transfer function (Vout vs. Vin)

Vgate

5Vdc

0

0

0

Vdrain

5Vdc

R1

1k

C1

1pF

Vout

Vin

0

V

Figure 6: PSpice circuit for generating the IRF-150 voltage transfer function (Vout vs. Vin).

Figure 7: PSpice simulation setup parameters for

voltage transfer function.


8

Figure 8: PSpice simulation results displaying voltage transfer characteristics of IRF-150 Power MOSFET.

The top plot is a graph of the slope of V(Vout) the points where slope = -1 identify the points needed to

calculate the noise thresholds of the device.

Vin Vout

0 1

1 0

After analyzing figure 8 the truth table above (table 1) can be developed. It is obvious from this truth table that this circuit is acting as an inverter. A Vin < 2.8311 V (Low) results in a Vout of 5 V (High), while a Vin > 2.8965 V (High) results in a Vout of 0 V (Low).

V_Vgate

0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

V(VOUT)

0V

2.5V

5.0VV

o

u

t

And.. NMH is approx -16% of Ideal

So.. NML is approx +12% of Ideal

Ideal NMH = 2.5V

Ideal NML = 2.5V

NMH = Vout(high) - Vin(high) = 2.092V

NML = Vin(low) - Vout(low) = 2.798V

Voltage Transfer Function (Vout vs. Vin (V_Vgate))

It was used to find Logic Theshold

This line is a drawn strait line. Vin(high),Vout(low)

Vin(low),Vout(high)

Logic Threshold or Switching Point

(2.8965,32.908m)

(2.8311,4.9886)

(2.8682,2.8650)

D(V(Vout))

-100

-50

0

-175

S

l

o

p

e

SEL>>

Used for finding Low and High Noise Margins

These points determine Vin(low) and Vout(low)

Interesting points are where Slope = -1

Graph of V(Vout)'s Slope

Point of Max Slope

(2.8860,-168.922)

Slope of V(Vout) = -1Slope of V(Vout) = -1

(2.8965,-1.0000)(2.8311,-1.0000)

Table 1: Truth table for IRF-150 Power MOSFET.


9

Power Consumption of the IRF-150 Power MOSFET

Modifications to the circuit used in generating the voltage transfer function (figure 6) are not required (other than switching the V-probe at “Vout” for a W-probe at “Vdrain”) for finding the power consumed, nor are modifications to the simulation settings. By running a simulation using a W-probe at “Vdrain” the following results were obtained as shown by figure 9.

As observed from figure 9, minimum power (56 µW) is consumed when the transistor is inverting an input (Vin) logic Low (0) into an output (Vout) logic High (1), however maximum power (25 mW) is consumed when the transistor is inverting an input (Vin) logic High (1) into an output (Vout) logic Low (0). The power consumed at Vin = 0 V is 56µW, while the power consumed at Vin = 5 V is 25 mW.

A complex logic circuit composed of 2000 such inverters, where half have a logic 0, and the other half have a logic 1 could consume approx 25W of power (1000 * 56 µW + 1000 * 25 mW = 25.056 W). With today’s IC’s packing millions of transistors this much power therefore heat is way too expensive.

V_Vgate

0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

-W(Vdrain)

0W

10mW

20mW

26mWP

o

w

e

r

C

o

n

s

u

m

e

d

Power Consumed as a function of Vin

Logic Threshold, Switching Point

Previously Determined

(2.8682,10.685m)

Min Power = 56uW

Max Power = 25mW

Power at Vin = 5V -> 25mW

Power at Vin = 0V -> 56uW

(2.8982,24.844m)

(2.8308,35.616u)

(5.0000,24.996m)

(0.000,56.129u)

Figure 9: PSpice simulation results showing power consumed by IRF-150 Power MOSFET.


10

Small Signal Characteristics of the IRF-150 Power MOSFET

In order to find the small signal characteristics of the IRF-150 Power MOSFET, the VDC power source “Vgate” voltage was changed (see figure 10) to the threshold voltage determined by figure 8. Next circuit simulation settings were adjusted for Bias Point analysis, and the check box for calculating small-signal DC gain was checked. “Vgate” was used as the simulation input source and “V(Vout)” was provided as an Output variable name as illustrated in figure 11.

Small data capture from the bottom of PSpice simulation output file… ---------------------------------------------------------------------------------------------------------------------

**** SMALL-SIGNAL CHARACTERISTICS V(VOUT)/V_Vgate = -1.137E+02

INPUT RESISTANCE AT V_Vgate = 1.000E+20 OUTPUT RESISTANCE AT V(VOUT) = 9.978E+02

--------------------------------------------------------------------------------------------------------------------- So the gain is approximately 113.7, input resistance is approximately 100 EΩ (exa-ohms) (or higher, due to PSpice limits), and output resistance is approximately 997.8 Ω. At this point it seems that this circuit has a good gain, extremely high input impedance and low output impedance.

M1

IRF150Vgate

2.868Vdc

Circuit used for finding the IRF-150

small signal characteristics. Vgate is

now at threshold voltage.

0

0

0

Vdrain

5Vdc

R1

1k

C1

1pF

Vout

Vin

0

Figure 10: PSpice circuit used to find the

small signal characteristics of the IRF-150. Figure 11: PSpice simulation settings for finding

small signal characteristics.


11

Frequency Response of the IRF-150 Power MOSFET

To find the frequency response of the circuit using the IRF-150 a VAC source (with 1 VAC, and the threshold voltage VDC) was swapped for the VDC source “Vgate” as shown in figure 12. Simulation settings were then adjusted to provide a good bode plot diagram showing frequencies from 10Hz to 1GHz (plotted logarithmically) at 10 points per decade as shown by figure 13. The results shown by figure 14 indicated the circuit was behaving like a low pass filter with a corner (f * 3 dB) frequency of 56 kHz. You may need to add a trace of “DB(V(Vout))” This indicates that frequencies less than the corner frequency will respond better (larger gains realized) than frequencies greater than the corner frequency (less gain realized, until eventually the IRF-150 is unable to keep up with the large frequencies and is non-functional.

Figure 14: PSpice simulation results (bode plot) of circuits frequency response. Corner freq = 56.410 kHz.

You should observe that frequencies below 10 kHz receive great gain and allow the IRF-150 switching speeds

to approximate that of an ideal inverter.

Frequency

10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz

DB(V(Vout))

-50

0

-65

45V

g

a

i

n

(

d

B

)

Note: The IRC-150 acts like a LP Filter (Approx 6dB / decade)

10*f(3dB) = 560kHz, Poor Gain

.1*f(3dB) = 5.6kHz, Max VGain

f(3dB) = 56kHz, .707 of Max VGain

frequency response

Bode plot for IRC-150's

We will round this frequency to 56kHz

and the voltage gain is reduced .707 of max

the power out is reduced to 1/2 of max

This is the frequency at which

Corner Frequency (Max -3dB)

(56.410K,38.112)

DB(V(Vout))

M1

IRF150


frequency responce. Vgate is

now a VAC source at threshold DC voltage.

0

0

0

Vdrain

5Vdc

R1

1k

C1

1pF

Vout

Vin

0Vgate1Vac

2.868Vdc

Figure 12: PSpice circuit used for finding IRF-150

frequency response. Figure 13: PSpice simulation settings for creating

a bode plot of the circuit’s frequency response.


12

Propagation Delays of the IRF-150 Power MOSFET

The circuit was again modified by replacing the VAC source “Vgate” with a Vpulse source as shown by figure 15. This figure was used in conjunction with the variable values used in table 2 for analyzing the circuits propagation delay (current) and digital frequency response (upcoming) sections of this report. For each simulation a Time Domain Analysis was performed to allow the user to see 3 to 5 periods (run to time = 3 to 5 * PER), and step size around 1/1000 of each period as shown by figure 16. Simulation results are shown on figure 17. Table 2: Variables used by PSpice circuit (figure 15).

Vpulse : variables used for IRF-150 PSpice schematic

Frequency (Hz) Period

(PER) (s) Pulse Width

(PW) (s)

Time-Rise &

Time-Fall (TR & TF)

(s)

f3db = 56 kHz 17.857 µs 8.9286 µs 1 ns

.1 * f3db = 5.6 kHz 178.57 µs 89.286 µs 10 ns

10 * f3db = 560 kHz 1.7857 µs .89286 µs .1 ns

Figure 15: PSpice circuit for finding the IRF-150

propagation delays and IRF-150 digital response at f(3

dB), .1 * f(3 dB), 100 * f(3 dB). V1 = 0, V2 = 5, TD = 0,

and TR/TF/PW/PER come from table 1.

Figure 16: PSpice simulation settings for finding the

IRF-150 propagation delays and digital responses.

Run to time should be 3-5 * PER, and step size should

= TR / TF.

M1

IRF150


propagation delays and digital frequency

responce. Vgate is now a Vpulse source

and TR/TF, PW, and PER will vary by freq.

0

0

0

Vdrain

5Vdc

R1

1k

C1

1pF

Vout

Vin

0Vgate

TD = 0

TF = 1nsPW = 8.9286usPER = 17.857us

V1 = 0

TR = 1ns

V2 = 5

V


13

Figure 17: PSpice simulation results showing rise time, fall time and propagation delays of circuit at input

freq. = 56 kHz.

From the results above we can calculate the following.. Note small error in tPHL and tP may be the result of the two points that reach 5 V. I used the right most point. The large off-shots above 5 V and below 0 V are due to the parasitic capacitance and resistance of the

IRF-150 model.

tHL = the time it takes output voltage to drop from 4.5 V to .5 V tLH = the time it takes output voltage to rise from .5 V to 4.5 V tPLH = the time it takes output voltage to rise from 0 to 2.5 V

tPHL = the time it takes output voltage to fall from 5 V to 2.5 V

tHL = 35.789 µs – 35.768 µs = 21 µs tLH = 31.931 µs – 27.478 µs = 4.453 µs tPLH = 28.899 µs – 27.125 µs = 1.774 µs

tPHL = 35.778 µs – 35.765 µs = 13 µs

Max Switching Frequency =

= 223.5 kHz

tP = Propagation delay time = .5 * ( tPLH + tPHL) = 831 ns

Time

26us 28us 30us 32us 34us 36us 37us

V(Vout)

0V

2.0V

4.0V

6.0VV

o

l

t

a

g

e

tP (Prop Delay Time) = 831ns

Max Switching Freq = 223.5 kHz

prop. delay (HL) = 13ns

prop. delay (LH) = 1.649us

t(HL) fall = 21ns

t(LH) rise = 4.453us

Frequency = f(3db) = 56kHz

Rise / Fall Times and Propagation Delays

tp(HL) = time to fall from 5 to 2.5V

tp(LH) = time to rise from 0 to 2.5V

.1 Vdd

.9Vdd to

.1Vdd to .9Vdd

t(LH)

t(HL)

Parasitic

Capacitance

Capacitance

Parasitic

Approx 0V

(35.804u,7.9055m)

(35.789u,500.000m)

(35.778u,2.5000)

(35.768u,4.5000)

(35.765u,5.0000)

(35.717u,5.0000)(31.931u,4.5000)

(28.899u,2.5000)

(27.478u,500.000m)

(27.125u,0.000)


14

Digital Frequency Response of the IRF-150 Power MOSFET

Now the IRF-150 Power MOSFET inverters digital response is analyzed using the circuit from the previous section (figure 15) and substituting for the frequencies provided by table 2. The digital response is checked first at the corner frequency of 56 kHz (as done previously), then at 5.6 kHz, and finally at 560 kHz. The results follow (Note, you will need to read the captions next to each figure for an understanding of the results)…

Figure 18: PSpice simulation results showing digital response of output at frequency of 56 kHz. Note the red

is the input square pulse (Vin), and the green is the output inverted response (Vout). This is acting as an OK

inverter since the output reaches over 90% of the operating range within a pulse width, however this

response should improve with a lower input frequency.

Time

0s 10us 20us 30us 40us 50us 60us 70us 80us

V(VOUT) V(Vin)

0V

2.0V

4.0V

6.0VV

o

l

t

a

g

e

Frequency = f(3dB) = 56kHz(38.451u,5.0000)

(31.057u,0.000)(9.2807u,16.438m)

(17.858u,4.9493)


15

Figure 19: PSpice simulation results showing digital response of output at frequency of 5.6 kHz (.1 * corner).

Notice the digital response is much cleaner now and is nearly that of an ideal inverter.

Figure 20: PSpice simulation results showing digital response of output at frequency of 560 kHz (10 * corner).

Notice the digital response is horrible now. The IRF-150 Power MOSFET simply cannot switch fast enough

to follow the input signal. This is now a non-functional inverter.

As observed from figures 18 thru 20 above, the lower the frequency is with respect to the corner frequency the better the IRF-150 Power MOSFET performs as an inverter. As the frequencies increase much higher than the corner frequency the IRF-150 cannot switch fast enough to follow the input signal (the rising edge time constant is too long per the switching speed.). This is due to the internal capacitance of the MOSFET.

Time

450us 500us 550us 600us 650us 700us 750us 800us 850us 900us 950us 990us

V(VOUT) V(Vin)

0V

2.0V

4.0V

6.0VV

o

l

t

a

g

e

Frequency = .1 * f(3dB) = 5.6kHz

(605.973u,5.0000)(535.044u,4.9888)

Time

3.0us 3.5us 4.0us 4.5us 5.0us 5.5us 6.0us 6.5us 7.0us 7.5us 8.0us2.6us

V(VOUT) V(Vin)

0V

2.5V

5.0VV

o

l

t

a

g

e

Frequency = 10 * f(3dB) = 560kHz

(4.1594u,5.0000)

(3.5722u,818.259m)


16

Maximum Frequency of the IRF-150 Power MOSFET circuit

The maximum frequency is the frequency at which the output just reaches 90% or 10% of the operating range within a pulse width. Finding the maximum frequency is done through a little trial and error. Using the corner frequency as a starting position the frequency was incrementally increased until the output reached 90% of VDD = 4.5 V. This was found to be approximately 100 kHz, as shown in figure 21 below.

Figure 21: PSpice simulation results of testing freq. = 100 kHz as maximum frequency. Notice output reaches

approx 4.5 V.

Time

5us 6us 7us 8us 9us 10us 11us 12us 13us 14us 15us

V(VOUT)

0V

2.0V

4.0V

6.0VV

o

l

t

a

g

e

Frequency = 100kHzApprox 4.5V -> 90% of 5V

(10.000u,4.4542)

By slowly increasing frequencies this freq. was found

Output Reaches Approx 90% of Operating Range

Approximation of Max Frequency Response


17

LAB 3: Summary of Results

Evaluation Procedure

Parameter Ideal

Inverter

IRF-150 Inverter Circuit

Transfer Char. VThreshold 2.5 V 2.8682 V

Noise Margins

NMH 2.5 V 2.092 V

NML 2.5 V 2.798 V

Power

P @ 0 V 0 W 56 µW

P @ 5 V 0 W 25 mW

PMax 0 W 25 mW

Rise Time tLH 0 s 4.453 µs

Fall Time tHL 0 s 21 ns

Propagation Delays

tPHL 0 s 13 ns

tPLH 0 s 1.774 µs

tP 0 s 831 ns

Small Signal Gain Av ∞ -113.7

Impedances Rin inf. inf.

Rout 0 997.8

3dB Corner Frequency

f3dB N/A 56.23 kHz

Maximum Frequency

fMax N/A 100 kHz

Table 3: Summary of Results for LAB 3.

Conclusion and Recommendations

As mentioned in previous sections for an ideal inverter (VIL=VIH=Vdd/2=2.5 V, VOH = Vdd=5 V,

VOL=0 V, Noise margins = 2.5 V) and as displayed by table 3 above, the IRF-150 NML is 12%

of the Ideal NML, while the IRF-150 NMH is -16% of the Ideal NMH. Also noted was the IRF-

150 works best as an inverter at frequencies below 10 kHz because its frequency response

closely resembles a low pass filter with a corner frequency of approximately 56 kHz. Because of

these reasons, I would say that the IRF-150 could be used as an inverter for simple low

frequency circuitry. Also, as mentioned in the power consumption section, each IRF-150 takes

either 56 µW or 25 mW depending upon the state of the inverter. This can create huge problems

in IC’s that require several of these devices to function, but since this is a Power device its

application in the digital world is not as relevant. With its long propagation delay’s and rise/fall

times cause by internal resistance and capacitance this inverter is not well suited for high

frequency applications.

Ee325 cmos design lab 3 report - loren k schwappach

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