EE247 Lecture 12 - University of California, Berkeleyee247/fa06/lectures/L12_f06.pdf · EECS 247...

EECS 247 Lecture 12: Data Converters © 2006 H. K.

EE247Lecture 12

• Administrative issuesMidterm exam Tues. Oct. 24tho You can only bring one 8x11 paper with your

own written notes (please do not photocopy)o No books, class or any other kind of

handouts/notes, calculators, computers, PDA, cell phones....

o Midterm includes material covered to end of lecture 14

EECS 247 Lecture 12: Data Converters © 2006 H. K. Page 2

EE247Lecture 12

Today:– Example of Switched-Capacitor filters NOT

followed by an ADC!– Data converters

• ADC & DAC transfer curve• Sampling, aliasing, reconstruction• Amplitude quantization• Static converter error sources

– Offset & full-scale error– DNL & INL


Summary of Last Lecture

• Switched-Capacitor Filters (continued)– Effect of non-idealities– Bilinear switched-capacitor filters– Filter design summary

• Comparison of various filter topologies

• Data Converters (continued today)


Last Lecture Questions

• Based on the CODEC example, class may have the impression that S.C. filters are always followed by an ADC!

• Assumption not accurate– Example- Switched-capacitor filters used in

the transmit path of ISDN ICs


Data Transmission Over Existing Twisted-Pair Phone Lines

Xmitter

Receiver

Central OfficeB

ackb

one

Dig

ital N

etw

ork

POTS

Xmitter

Receiver

• Data transmitted over existing voice grade phone lines covering distances close to 3.5miles

– Voice-band MODEMs– ISDN– HDSL, SDSL,……– ADSL

Customer

Twisted Pair

3 to 5km


Data Transmission Over Twisted-Pair Phone LinesISDN (U-Interface) Transceiver

• Full duplex transmission (RX & TX signals sent simultaneously)• 160kbit/sec baseband data (80kHz signal bandwidth)• Standardized line code 2B1Q (4 level code 3:1:-1:-3)• Max. desired loop coverage 18kft (~36dB signal attenuation)• Final required BER (bit-error-rate) 10-7 (min. SNDR=27dB)

Xmitter

Receiver

Central Office

Bac

kbon

eD

igita

l Net

wor

k

POTS

Xmitter

Receiver

Customer

Twisted Pair

3 to 5km


Analog Front-End2b S.C.

DAC2nd order

ButterworthS.C. Filter

Class A/BLine Driver

13bitDouble-Loop

To avoid stringent requirements for non-linear echo canceller:

high linearity analog circuitry needed (~ 75dB)

Peak signal frequency 80kHz

fs=2.56MHz

fs=20.48MHz


Data Converters


Data Converters

• Stand alone data converters– Used in variety of systems

– Example: Analog Devices AD9235 12bit/ 65Ms/s ADC- Applications:

• Ultrasound equipment

• IF sampling in wireless receivers

• Hand-held scopemeters

• Low cost digital oscilloscopes


Data Converters• Embedded data converters

– Cost, reliability, and performance integration of data conversion interfaces along with DSPs

– Main challenges• Feasibility of integrating sensitive analog functions in

technologies optimized for digital performance

• Down scaling of supply voltage

• Interference & spurious signal pick-up from on-chip digital circuitry

• Portable applications dictate low power consumption


D/A Converter Transfer Characteristics• An ideal digital-to-

analog converter:–Accepts digital inputs b1-bn

–Produces either an analog output voltage or current

–Assumption (will be revisited)

• Uniform, binary digital encoding

• Unipolar output ranging from 0 to VFS

D/A

……..…b1 b2 b3 bn

V0

MSB LSB

FS

FSN

FS2

N # of bi ts

V ful l scale output

min. s tep size 1LSB

V2

Vor N log resolut ion

=

=

Δ = →

Δ =

= →Δ

Nomenclature:


D/A Converter Transfer Characteristics

FS

FSN

N # of bi ts


min. step size 1LSB

V

2

=

=

Δ = →

Δ =

N

0 FSi 1

N

i 1

i

N i

biV V

2

bi 2 , bi 0 or 1

=

=

−

=

= Δ × × =

∑

∑

D/A

……..…b1 b2 b3 bn

V0

MSB LSB

binary-weighted


D/A Converter Exampe: D/A with 3-bit Resolution

D/A

b1 b2 b3

V0

MSB LSB

( )

( )

FS

0 1 2 3

3FS

0

0

NFS FS

2 1 0

2 1 0

Example : N 3

Assume V 0.8VInput code is 101

V b 2 b 2 b 2

Then : V / 2 0.1V

V 0.1V 1 2 0 2 1 2

V 0.5V

Note : MSB V / 2 & LSB V / 2

=

=

= Δ × + × + ×

Δ = =

→ = =× + × + ×

→ =

→ →

1 0 1


Ideal D/A Transfer Characteristic

• Ideal DAC introduces no error!

• One-to-one mapping from input to output

000 001 010 011 100 101 110 111

Step Height (1LSB =Δ)

Ideal Response

Digital InputCode

Analog OutputVFS

VFS /2

VFS /8


A/D Converter Transfer Characteristic

• For an ideal analog-to-digital converter with uniform, binary digital encoding & a unipolar input range for 0 to VFS

( ) FSi

FS N

Note : D Vb 1,al l i1

1V2

→ − Δ=⎛ ⎞−→ ⎜ ⎟⎝ ⎠

FS

FSN

where N # of bi ts


step s ize

V

2

=

=

Δ =

Δ =

……..…b1 b2 b3 bm

Vin

MSB LSB

A/D


Ideal A/D Transfer Characteristic

• Ideal ADC introduces error

(+-1/2 Δ) Δ = VFS /2 N

N= # of bits

• This error is called ``quantization error``

111

110

101

100

011

010

001

000

Digital Output

Analog input

0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ

1LSB


Example: Non-Linear A/D ConverterFor Voice-Band Telephony Applications

Non-linear ADC and DAC used in voice-band CODECs

• To maximize dynamic range with lower # of bits

• Coding scheme called A-law & μ-law

• Also called companding Ref: P. R. Gray, et al. "Companded pulse-code modulation voice codec using monolithic weighted capacitor arrays," IEEE Journal of Solid-State Circuits, vol. 10, pp. 497 - 499, December 1975.

-VFS/2-VFS -VFS/4

Coder Input(ANALOG)

Coder Output(DIGITAL)


Data Converter Performance Metrics• Data Converters are typically characterized by static, time-domain,

& frequency domain performance metrics :– Static

• Monotonicity• Offset• Full-scale error• Differential nonlinearity (DNL)• Integral nonlinearity (INL)

– Dynamic• Delay, settling time• Aperture uncertainty• Distortion- harmonic content• Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR)• Idle channel noise• Dynamic range & spurious-free dynamic range (SFDR)


Typical Sampling ProcessCT ⇒ SD ⇒ DT

ContinuousTime

Sampled Data(e.g. T/H signal)

Clock

Discrete Time

time

PhysicalSignals

"MemoryContent"


Discrete Time Signals• A sequence of numbers (or vector) with

discrete index time instants• Intermediate signal values not defined

(not the same as equal to zero!)• Mathematically convenient, non-physical• We will use the term "sampled data" for

related signals that occur in real, physical interface circuits


Uniform Sampling

• Samples spaced T seconds in time• Sampling Period T ⇔ Sampling Frequency fs=1/T• Problem: Multiple continuous time signals can yield

exactly the same discrete time signal (aliasing)

y(kT)=y(k)

t= 1T 2T 3T 4T 5T 6T ...k= 1 2 3 4 5 6 ...


Data Converters

• ADC/DACs need to sample/reconstruct to convert from continuous time to discrete time signals and back

• We distinguish between purely mathematical discrete time signals and "sampled data signals" that carry information in actual circuits

• Question: How do we ensure that sampling/reconstruction fully preserve information?


Aliasing

• The frequencies fx and Nfs ± fx, N integer, are indistinguishable in the discrete time domain

• Undesired frequency interaction and translation due to sampling is called aliasing

• If aliasing occurs, no signal processing operation downstream of the sampling process can recover the original continuous time signal!

• Let's look at this in the frequency domain...


Sampling Sine Waves

fs = 1/T

y(nT) time

Time domain

fs … f

Am

plitu

de

fin 2fs

fs - fin fs + fin

Vol

tage

Frequency domain


Frequency Domain Interpretation

fs …….. f

Am

plitu

de

fin 2fs

Am

plitu

de

f/fs

Signal scenariobefore sampling

Signal scenarioafter sampling DT

Signals @nfS ± fmax__signal fold back into band of interest

Aliasing

fs /2

0.5

ContinuousTime

DiscreteTime


How to Avoid Aliasing

• Must obey sampling theorem:fmax_Signal < fs/2

• Two possibilities:1. Sample fast enough to cover all spectral

components, including "parasitic" ones outside band of interest- usually not practical

2. Limit fmax_Signal through filtering


Brick Wall Anti-Aliasing Filter

ContinuousTime

DiscreteTime

0 fs 2fs ... f

Amplitude

0 0.5 f/fs

Filter

Sampling at Nyquist rate (fs=2fsignal) required brick-wall anti-aliasing filters


Practical Anti-Aliasing Filter

• Practical filter: Nonzero "transition band"• In order to make this work, we need to

sample faster than 2x the signal bandwidth• "Oversampling"

ContinuousTime

0 fs 2fs ... f

Amplitude Filter

fs/2


Practical Anti-Aliasing Filter

ContinuousTime

DiscreteTime

0 fs ... f

DesiredSignal

0 0.5 f/fs

fs/2B fs-B

ParasiticTone

B/fs

Attenuation


Data ConverterClassification

• fs > 2fmax Nyquist Sampling– "Nyquist Converters"– Actually always slightly oversampled (e.g. CODEC fsig

max 3.4kHz ADC sampling 8kHz)

• fs >> 2fmax Oversampling– "Oversampled Converters"– Anti alias filtering is often trivial– Oversampling is also used to reduce quantization noise, see later

in the course...

• fs < 2fmax Undersampling (sub-sampling)


Sub-Sampling

• Sub-sampling sampling at a rate less than Nyquist rate aliasing• For signals centered @ an intermediate frequency Not destructive!• Sub-sampling can be exploited to mix a narrowband RF or IF signal down

to lower frequencies

ContinuousTime

DiscreteTime

0 fs ... f

Amplitude

0 0.5 f/fs

BP Filter


Where Are We Now?

• We now know how to preserve signal information in CT DT transition

• How do we go back from DT CT?

Analog Postprocessing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

110

Anti-AliasingFilter

?

Sampling(+Quantization)


Ideal Reconstruction

• Unfortunately not all that practical...

∑∞

−∞=

−⋅=k

kTtgkxtx )()()(Bt

Bttgπ

π2

)2sin()( =

• The DSP books tell us:

⇒x(k) x(t)


Zero-Order Hold Reconstruction

• How about just creating a staircase, i.e. hold each discrete time value until new information becomes available?

• What does this do to the frequency content of the signal?

• Let's analyze this in two steps...

0 10 20 30-1

-0.6

-0.2

0.2

1

Time [μs]

Am

plitu

de

sampled dataafter ZOH

0.6


1) DT CT: Infinite Zero Padding

DT sequence

f/fs

Time Domain Frequency Domain

......

0.5

Zero paddedDT sequence

......

f/fs0.5/i 1.5/i 2.5/i

InfiniteInterpolation:CT Signal!

......

f0.5fs 1.5fs 2.5fs


2) Add a Hold Function

• Hold pulses for Tp period• Using the Fourier transform of a rectangular impulse:

......

Tp

Ts

p

p

s

p

fTfT

TT

fHπ

π )sin()( =


Hold Pulse Tp=Ts

0 0.5 1 1.5 2 2.5 30

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

f/fs

abs(

H(f)

)p

p

s

p

fTfT

TT

fHπ

π )sin(|)(| =


ZOH Spectral DistortionContinuous Time

Pulse Train Spectrum

ZOH Transfer Function

("Sinc Distortion")

ZOH output, Spectrum of

Staircase Approximation

f/fs

0 0.5 1 1.5 2 2.5 30

0.5

1

0 0.5 1 1.5 2 2.5 30

0.5

1

0 0.5 1 1.5 2 2.5 30

0.5

1

X(k)

ZOH


Smoothing FilterAgain:• A brick wall

filter would be nice

• Oversampling helps to reduce filter order

f/fs

0 0.5 1 1.5 2 2.5 30

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1


Summary• Sampling theorem fs > 2fmax, usually dictates

anti-aliasing filter

• If theorem is met, CT signal can be recovered from DT without loss of information

• ZOH and smoothing filter reconstruct CT from DT signal

• Oversampling helps reduce order & complexity of anti-aliasing & smoothing filters


Next Topic

• Done with "Quantization in time"

• Next: Quantization in amplitude

Analog Postprocessing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

110

Anti-AliasingFilter

Sampling(+Quantization)

SmoothingFilter

D/A+ZOH


AmplitudeQuantization

• Amplitude quantizationquantization “noise”

• Static ADC/DAC performance measures– Offset– Gain– INL– DNL


Ideal ADC ("Quantizer")• Quantization step:

Δ (= 1 LSB)

• Full-scale input range:-0.5Δ … (2N-0.5)Δ

• E.g. N = 3 Bits

VFS= -0.5Δ to 7.5Δ

-1 0 1 2 3 4 5 6 7 801234567

Dig

ital O

utpu

t Cod

e

ADC characteristicsIdeal converter with infinite # of bits

ADC Input Voltage [ Δ]VFS


Quantization Error• Difference between analog input and output of the ADC

converted to analog via an ideal DAC

• Called:

:Quantization error

Residue

Quantization noise

Vin ADCIdeal DAC Σ

Residue

+- εq (Vin )


Quantization Error

• For an ideal ADC:

• Quantization error is bounded by –Δ/2 … +Δ/2for inputs within full-scale range

+

εq (Vin )

Vin Dout

ADC Model

-1 0 1 2 3 4 5 6 7 801234567

Dig

ital O

utpu

t Cod

e ADC characteristicsideal converter with infinite bits

-1 0 1 2 3 4 5 6 7 8

-0.5

0

0.5

Qua

ntiz

atio

n er

ror

[LS

B]

ADC Input Voltage [Δ]


ADC Dynamic Range• Assuming quantization noise is much larger

compared to circuit generated noise:

• Crude assumption: Same peak/rms ratio for signal and quantization noise!

Question: What is the quantization noise power?

10

20

20 20 2 6 02

Maximum

Maximum

NFS

Full Scale Signal PowerD.R. logQuantization Noise Power

Peak Full ScaleD.R. logPeak Quantization NoiseVlog log . N [ dB ]

=

=

= = = ×Δ


Quantization Error

0

Δ/2

Quantizationerror [LSB]

Let us assume Vin is a ramp signal with amplitude equal to ADC full-scale

Vin_Ramp

Time

Time

VFS

Note: Quantization error waveform periodic and also ramp

−Δ/2


Quantization ErrorNeed to find the rms value for quantization error waveform:

Quantizationerror

0

Δ/2

Time

−Δ/2

εq=k.t

−Δ/2kΔ/2k

( ) ( )2 2

2eq

22

22

eq

eq

T / 2 / 2k

T / 2 / 2k

/ 2k

/ 2k

1k t dt k t dt

T k

kt dt

k

12

12

ε

ε

ε

+ +

+

Δ

− −Δ

Δ

−Δ

Δ= × = ×

Δ=

Δ→ =

Δ→ =

∫ ∫

∫

Independent of k

In general above equation applies if:• Input signal much larger than 1LSB• Input signal busy• No signal clipping


Quantization Error PDF• Uniformly distributed from

–Δ/2 … +Δ/2 provided that– Busy input– Amplitude is many LSBs– No overload

• Not Gaussian!

• Zero mean• Variance

Ref: W. R. Bennett, “Spectra of quantized signals,” Bell Syst. Tech. J., vol. 27, pp. 446-72, July 1988.

B. Widrow, “A study of rough amplitude quantization by means of Nyquist sampling theory,” IRE Trans. Circuit Theory, vol. CT-3, pp. 266-76, 1956.

-Δ/2

Pdf

error

1/Δ

+Δ/2

2 22

/ 2

/ 2

ee de

12

+Δ

−Δ

Δ= =

Δ∫


Signal-to-Quantization Noise Ratio• If certain conditions are met (!) the quantization error can be

viewed as being "random", and is often referred to as “noise”• In this case, we can define a peak “signal-to-quantization noise

ratio”, SQNR, for sinusoidal inputs:

• Actual converters do not quite achieve this performance due to other errors, including

– Electronic noise– Deviations from the ideal quantization levels

2N

2N2

1 22 2

SQNR 1.5 2

12

6.02N 1.76 dB Accurate for N>3

⎛ ⎞Δ⎜ ⎟⎜ ⎟⎝ ⎠= = ×

Δ

= +

e.g. N SQNR8 50 dB

12 74 dB16 98 dB20 122 dB


SQNR Measurement

20log(SQNR)

Vin [dB]0dB

6dB/octaveRealistic

peakSQNR 6.02N 1.76 dB= +

Dynamic Range

Ideal


Static, Ideal Macro ModelsADC

+DoutVin

εq

DACVoutDin


Cascade of Data ConvertersADC

+Vin

εq

DACVout

ADC

+εq

DACDout

Din


Static Converter Errors

Deviations of characteristic from ideal– Offset– Full scale error– Differential nonlinearity, DNL– Integral nonlinearity, INL


Offset ErrorADC DAC

Ref: “Understanding Data Converters,” Texas Instruments Application Report SLAA013, Mixed-Signal Products, 1995.


Full Scale ErrorADC DAC

Actual full scale point

Ideal full scale point Ideal full scale

point

Full scale error

Actual full scale

point

Full scale error


Offset and Full Scale Errors

• Alternative specification in % Full Scale = 100% * (# of LSB value)/ 2N

• Gain error can be extracted from offset & full scale error

• Non-trivial to build a converter with extremely good gain/offset specs

• Typically gain/offset is most easily compensated by the digital pre/post-processor

• More interesting: Linearity measures DNL, INL


Offset and Full-Scale Error

-1 0 1 2 3 4 5 6 7 8

0

1

2

3

4

5

6

7

Dig

ital O

utpu

t Cod

e

ADC Input Voltage [LSB]

ADC characteristicsideal converter

Offset error

Full-scale error

Note:For further measurements (DNL, INL) connecting the endpoints & deriving ideal codes based on the non-ideal endpoints elliminates offset and full-scale error


-1 0 1 2 3 4 5 6 7 8 9

0

1

2

3

4

5

6

7

8ADC characteristicsideal converter

ADC Differential Nonlinearity

DNL = deviation of code width from

Δ (1LSB)

+0.4 LSB DNL error

-0.4 LSB DNL error

Endpoints connectedIdeal characteriscticsderived DNL measured

0 LSB DNL error

Dig

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e



ADC Differential Nonlinearity

• Ideal ADC transitions point equally spaced by 1LSB

• For DNL measurement, offset and full-scale error is eliminated

• DNL [k] (a vector) measures the deviation of each code from its ideal width

• Typically, worst-case DNL along with the vector for the entire code is reported


ADC Differential NonlinearityExample

A 3bit ADC is designed to have an ideal LSB=0.1V

The measured transitions levels for the end product is shown in the table below, compute the DNL

0.680.657

0.50.556

0.420.455

0.370.354

0.20.253

0.130.152

0.020.051

Real transition point [V]

Ideal transition point [V]

Transition #



1- Find the average code width (LSB size)LSB=(Last transition-first transition)/(2N-2)

LSB=(0.68-0.02)/6=0.11V2- Find all code widthsWidth[k]=Transition[k+1]-Transition[k]3- Divide code width by LSB4- Find DNL:DNL[k]=(W[k]-LSB

--0

--7

0.640.186

-0.270.085

-0.550.054

0.550.173

-0.370.072

00.111

DNL[LSB]

Code Width [V]

Code #



--0

--7

0.640.186

-0.270.085

-0.550.054

0.550.173

-0.370.072

00.111

DNL[LSB]

Code Width [V]

Code #

Code #

DN

L [L

SB

}

0 1 2 3 4 5 6 7

1

0.5

0

-0.5

-1

Max.DNL


-1 0 1 2 3 4 5 6 7 8 9

0

1

2

3

4

5

6

7


ADC Differential NonlinearityExamples

-1 0 1 2 3 4 5 6 7 8 9

0

1

2

3

4

5

6

7


Non-monotonic(> 1 LSB DNL)

Missing code(+0.5/-1 LSB DNL)

Dig

ital O

utpu

t Cod

e


Dig

ital O

utpu

t Cod

e



ADC DNL

• DNL=-1 implies missing code• For an ADC DNL < -1 not possible• Can show:

• For a DAC DNL can be < -1

al l iDNL[i] 0=∑


DAC Differential Nonlinearity

• To find DNL for DAC– Draw end-point line from 1st point to last– Find ideal LSB size– Find segment sizes:

segment [m]=V[m]-V[m-1]

• Unlike ADC DNL, for a DAC DNL can be <-1LSB

segment[ m] V [ LSB]DNL[ m]

V [ LSB]

−=


DAC Differential Nonlinearity


Impact of DNL on Performance

• Same as a somewhat larger quantization error, consequently degrades SQNR

• How much – later in the course...• People sometimes speak of "DNL

noise", i.e. "additional quantization noise due to DNL"


ADC Integral Nonlinearity

• A straight line through the endpoints is usually used as reference,i.e. offset and full scale errors are ignored in INL calculation

• Ideal converter steps is found for the endpoint line, then INL is measured

• Note that INL errors can be much larger than DNL errors and vice-versa -1 0 1 2 3 4 5 6 7 8

0

1

6

7

Dig

ital O

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e


INL = deviation of code transition from its ideal location

-1 LSB INL

2

3

4

5


ADC Integral NonlinearityBest Fit versus End-Point

• End-Point– A straight line through the

endpoints is used as reference,i.e. offset and full scale errors are ignored in INL calculation

– Ideal converter steps is found for the endpoint line, then INL is measured

• Best-Fit– A best-fit line (in the least-

mean squared sense)

– Ideal converter steps is found then INL is measured

-1 0 1 2 3 4 5 6 7 8

0

1

6

7

Dig

ital O

utpu

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e


-1/2 LSB INL

2

3

4

5

+1/2 LSB INL

Note: Typically INL smaller for best-fit compared to end-point

Best Fit



--0

0-7

-0.640.646

-0.37-0.275

0.18-0.554

-0.370.553

0-0.372

001

INL[LSB]

DNL[LSB]

Code #Can show:

INL is found by computing the cumulative sum of DNL

For the previous example:Note: INL for the last code=0

m 1

i 1INL[ m] DNL[i]

−

== ∑



--0

0-7

-0.640.646

-0.37-0.275

0.18-0.554

-0.370.553

0-0.372

001

INL[LSB]

DNL[LSB]

Code #

Code #

DN

L [L

SB

]

0 1 2 3 4 5 6 7

1

0.5

0

-0.5

-1

INL

[LS

B]

0 1 2 3 4 5 6 7

1

0.5

0

-0.5

-1

Max.DNL

Max.INL


DAC Integral Nonlinearity


DAC DNL and INL

* Ref: “Understanding Data Converters,” Texas Instruments Application Report SLAA013, Mixed-Signal Products, 1995.


Example: INL & DNL

Large INL & Small DNL Large DNL & Small INL


Monotonicity• Monotonicity guaranteed if

| INL | ≤ 0.5 LSBThe best fit straight line is taken as the reference for determining the INL.

• This implies| DNL | ≤1 LSB


Non-Monotonic DAC

000 001 010 011 100 101 110 111

DigitalInput

Analog Output [LSB]

7

6

5

4

3

2

1

0

segment[ m] V [ LSB]DNL[ m]

V [ LSB]

segment[4] V [ LSB]

DNL[4]V [ LSB]

0.5 11.5[ LSB]

12.5 1

DNL[5] 1.5[ LSB]1

−=

−

=

− −= = −

−== =

• DNL< -1LSB for a DACNon-monotonicity

• When can non-monotonicity can cause major problems?


Non-Monotonic ADC

• Code 011 associated with two transition levels !

• For non-monotonic ADC

DNL not defined

111

110

101

100

011

010

001

000

Digital Output

Analog input

0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ

EE247 Lecture 12 - University of California, Berkeleyee247/fa06/lectures/L12_f06.pdf · EECS 247...

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