inst.eecs.berkeley.edu/~ee241b

Borivoje Nikoli

EE241B : Advanced Digital Circuits

Lecture 5 – Leakage, Delay Models

The passing of Barrie Gilbert (1937-2020). He was well known for his invention of numerous analog circuit concepts, holding over 100 patents worldwide, and for the discovery of the Translinear Principle. His name is attributed to a class of related topologies loosely referred to as the Gilbert cell, one of which is a mixer - a key frequency translation device - used in every modern wireless communication device.

1EECS241B L05 LEAKAGE/DELAY MODELS

Announcements

• Homework 1 posted today, due in 2 weeks

2EECS241B L05 LEAKAGE/DELAY MODELS

Outline

• Module 2• MOS transistor leakage• C-V models• Delay revisited

3EECS241B L05 LEAKAGE/DELAY MODELS

Recap last lecture

• Scaled transistors are different that the ones in textbooks• But the same principles still apply• Sizing:

• P/N ratio is set by mobilities• Mobility enhancements are more effective on PMOS devices• ~1:1 in sub 16nm

• Stack sizing set by velocity saturation• Stack of 2 reduces NMOS current by ~2/3

• PMOS depends on the degree of saturation, also ~2/3 in sub 16nm

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Recap last lecture: Logical Effort• Older CMOS (>1μm)

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OutIn

VDD

B

VDD

A

OutA

VDD

M2M1

B

M3

M4

• Planar CMOS (~28nm, bulk, FDSOI)

OutIn

VDD

B

VDD

A

OutA

VDD

M2M1

B

M3

M4

• FinFET (16nm-7nm)

OutIn

VDD

B

VDD

A

OutA

VDD

M2M1

B

M3

M4

ginv = 1

gNAND2 =

gNOR2 =

ginv = 1

gNAND2 =

gNOR2 =

ginv = 1

gNAND2 =

gNOR2 =

2.E Other Velocity Saturation Models

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Other Models: Alpha Power Law Model

• Simple model, sometimes useful for hand analysis

ThGSoxDS VVCLWI2

Parameter a is between 1 and 2.

Sakurai, Newton, JSSC 4/90

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Alpha Power Law Model

•This is not a physical model•Simply empirical:

• Can fit (in minimum mean squares sense) to variety of ’s, VTh• Need to find one with minimum square error – fitted VTh can be

different from physical

• Can also fit to = 1• What is VTh?

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K(VGS –VTHZ) Model ( = 1)

Drain current vs. gate-source voltage

0.0E+00

2.0E-04

4.0E-04

6.0E-04

8.0E-04

0 0.2 0.4 0.6 0.8 1 1.2V GS [V]

I DS

[A]

VTHZEECS241B L05 LEAKAGE/DELAY MODELS 9

Saturation Currents

Model Usage

Delay estimates with VDD >> VTH

Long channel devices (rare in digital)

Delay estimates in a wider range of VDD’s

Easy to remember, does not handle stacks correctly

Handles stacks correctly, sizing

DS GS THZWI K V VL

2ox

DS GS THCWI V V

L

2

2Dsat

DS ox GS TH DsatVWI C V V V

L2

2C GS THox

DSGS TH C

E L V VCWIL V V E L

2

2ox

DS GS THCWI V V

L

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2.F Transistor Leakage

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Transistor Leakage

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Transistor Leakage

Subthreshold slope

Leakage current is exponential with VGS

VDS = 1V

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

0 10 20 30 40 50 60 70 80 90 100

VGS [V]

IDS

[uA]

1m

100u

1u

10u

100n

0 10.5

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Transistor Leakage (130nm)

Two effects:• diffusion current (like a bipolar transistor)• exponential increase with VDS (DIBL)

0

2

4

6

8

0 0.2 0.4 0.6 0.8 1 1.2 1.4VDS [V]

I DS

[nA

]

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Transistor Leakage (32nm LP PTM)

Another view of DIBL>10x increase in leakage

0.00E+00

5.00E-12

1.00E-11

1.50E-11

2.00E-11

2.50E-11

3.00E-11

3.50E-11

1.00.80.60.40.20

VDS [V]

ILeak [A]

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Subthreshold Current

• Subthreshold behavior can be modeled physically

qkTVds

qkTmVV

oxeffsubthds eeqkTm

LWCI

ThGS

112

,

SVVV

subthds

dsThgs

WWII 10

00,

Or (approx):Taur, Ning, Modern VLSI Devices

ox

dm

CCm 1 (m ~ 1.1-1.4)

qkTmS 3.2

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Leakage Components

Courtesy of IEEE Press, New York. 2000EECS241B L05 LEAKAGE/DELAY MODELS 17

Leakage Components (250nm)

1. pn junction reverse bias current

2. Weak inversion

3. Drain-induced barrier lowering (DIBL)

4. Gate-induced drain leakage (GIDL)

5. Punchthrough

6. Narrow width effect

7. Gate oxide tunneling

8. Hot carrier injection

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Leakage Components

• Drain-induced barrier lowering (DIBL)• Voltage at the drain lowers the source potential barrier• Lowers VTh, no change on S

• Gate-induced drain leakage (GIDL)• High field between gate and drain increases injection of carriers into substrate ->

leakage (band-to-band leakage)

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2.H Transistor C-V

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MOS Transistor as a Switch

Discharging a capacitor• Can solve:

DS DS DSi i vDS

DS DSdvi C v

dt

• Prefer using equivalent resistances• Find tpHL• Find equivalent C, R

+

-vDS

iDSvGS

,

( )dDS DSpHL

DS GS DS

C v vti v v

C

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MOS Capacitances

• Gate capacitance• Non-linear channel capacitance• Linear overlap, fringing capacitances• Miller effect on overlap, fringing capacitance

• Non-linear drain diffusion capacitance• PN junction

• Wiring capacitances• Linear

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Gate and Drain CapacitancesGate capacitance

Drain capacitance

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Gate Capacitances

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Gate Capacitances

• Gate capacitance is non-linear• First order approximation with CoxWL (CoxL = 2fF/ m)

• Need to find the actual equivalent capacitance by simulating it

• Since this is a linear approximation of non-linear function, it is valid only over the certain range

• Different capacitances for HL, LH transitions and power computation

• Drain capacitance non-linearity compensates• But this changes with fanout

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2.I Delay Revisited

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MOS Transistor as a Switch (EECS251A)

Traversed path

C

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MOS Transistor as a Switch (EE241A)

Solving the integral:

Averaging resistances:

with appropriately calculated Idsat

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CMOS Performance

Propagation delay: LeqnpHL CRt 2ln LeqppLH CRt 2ln

ln2 = 0.7

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0.0E+00

1.0E-04

2.0E-04

3.0E-04

4.0E-04

5.0E-04

6.0E-04

0.2 0.4 0.6 0.8 1.0

VDS[V]

IDS[A]

Switching Trajectory

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Effective Current

• Ion(VDD) is never reached• Define Ieff = (IH + IL)/2• IL = IDS(VGS=VDD/2, VDS=VDD); IH=IDS(VGS=VDD, VDS=VDD/2),

Na, IEDM’2002Von Arnim, IEDM’2007

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DIBL Matters• A. Loke, VLSI’16

FinFET, FDSOI – less DIBL

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0.0E+00

1.0E-04

2.0E-04

3.0E-04

4.0E-04

5.0E-04

6.0E-04

0.2 0.4 0.6 0.8 1.0

VDS[V]

IDS[A]

Transistor Stacks

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Effective Current in Stacks

Von Arnim, IEDM’2007

Add linear current, I3

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Next Lecture

• Standard Cells

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