EE241 - Spring 2013bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s13/... · Circuits, vol. 25, no....
Transcript of EE241 - Spring 2013bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s13/... · Circuits, vol. 25, no....
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EE241 - Spring 2013Advanced Digital Integrated Circuits
Lecture 2: Scaling Trends and Features of Modern Technologies
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Announcements
Sign up for Piazza if you haven’t already
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Assigned Reading
R.H. Dennard et al, “Design of ion-implanted MOSFET's with very small physical dimensions” IEEE Journal of Solid-State Circuits, April 1974.
Just the scaling principles
C.G. Sodini, P.-K. Ko, J.L. Moll, "The effect of high fields on MOS device and circuit performance," IEEE Trans. on Electron Devices, vol. 31, no. 10, pp. 1386 - 1393, Oct. 1984.
K.-Y. Toh, P.-K. Ko, R.G. Meyer, "An engineering model for short-channel MOS devices" IEEE Journal of Solid-State Circuits, vol. 23, no. 4, pp. 950-958, Aug. 1988.
T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584 - 594, April 1990.
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Outline
Scaling issues
Technology scaling trends
Features of modern technologiesLithography
Process technologies
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Part 1:Technology
A. Scaling Trends
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Transistor Counts
Doubles every 2 years
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0.1
1
10
100
1000
10000
1970 1975 1980 1985 1990 1995 2000 2005 2010
Fre
qu
ency
[MH
z]
Frequency Trends in Intel's Microprocessors
4004
8008
8080
8086
8088
80286
386DX
486DX486DX4
Pentium
Pentium Pro Pentium II
Pentium MMX
Pentium III
Pentium 4
ItaniumItanium II
Core2
i7
Frequency
Has been doublingevery 2 years
Nearly flat
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0.1
1
10
100
1000
1970 1975 1980 1985 1990 1995 2000 2005 2010
Po
wer
[W
]
Power Trends in Intel's Microprocessors
4004
80088080
8086
8088
80286
386DX
486DX
Pentium
Pentium Pro
Pentium II
Pentium III Pentium 4
ItaniumItanium II Core 2
i7
Power Dissipation
Has been > doublingevery 2 years
Has to stay ~constant
B. Scaling Issues
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p substrate, doping *NA
L/xd/
GATE
n+ source
n+ drain
WIRINGVoltage, V /
W/tox/
CMOS Scaling Rules
SCALING:Voltage: V/Oxide: tox /Wire width: W/Gate width: L/Diffusion: xd /Substrate: * NA
RESULTS:Higher Density:
~2
Higher Speed: ~Power/ckt: ~1/2
Power Density:~Constant
R. H. Dennard et al., IEEE J. Solid State Circuits, (1974).
11Å
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CMOS Scaling
Two 30nm transistors (then and now)
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Transistor ScalingShrink by 30%
“Contacted gate pitch”Shrink by 30%
28nmC. Auth, VLSI’12
Gate pitch scales 0.7x every nodeIntel 22nm: contacted gate pitch 90nm
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0.1
1
10
100
1000
10000
10 100 1000Lg [nm]
V DD
I DSAT
T inv
V Th
Ideal I DSAT
Ideal V DD
Ideal T inv
Ideal V Th
Ideal vs. Real Scaling
Leakage slows down VTh, VDD scaling
[µA/µm]
[x10V]
[ps]
[V]
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Technology Flavors
LP keeps drain leakage constant
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32nm Technology Flavors (Intel)
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Lg, R, C scaling
With scaling L, need to scale up doping - scale junction depth (control leakage) – S/D resistance goes up
External resistance limits current
m
10000
1000
100
10
10
1
0.1
0.01
nm130nm
90nm
70nm
50nm
Gate Length65nm
35nm
1970 1980 1990 2000 2010 2020
45nm
32nm
22nm
~30nm
0.7X every 2 years
Nominal feature size
180nm
250nm
/D DS channel extI V R R
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Parasitic Capacitance Scaling
S. Thompson, Materials Today, 2006.
Reality: Overlap + fringe can be 50% of Cchannel in 32nm
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C. 32/28nm Technology Features
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Technology Features
Lithography implications (this lecture)Restrictions on design
Implications on design variability
FEOL features (next lecture)
Models
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EE 141 Technology vs. 32/28nmFEOL
0.25m featuresLg ~ 240nm248nm lithographyNo OPC, liberal design rulesSiO2 oxide, 3.5nm106 dopant atomsLOCOSNobody knew what ‘strain’ isVelocity saturatedNo SD leakageNo gate leakageOne transistor flavor
BEOLAl interconnectSiO2 ILD4-5 M layersNo CMP, no density rules
FEOL32nm technologyLg = 30-35nm193nm immersion lithographyOPC, restricted design rulesHf-based dielectric~102 dopant atomsSTIStrained silicon in channelVelocity saturatedIDS,off ~ 100nA/µmLow gate leakageMany transistor flavors
BEOLCu interconnectLo-k ILD8-11 M layersCMP, density rules
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Step-and-Scan Lithography
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Lithography Scaling
m
10000
1000
100
10
10
1
0.1
0.01
nm
130nm90nm
65nm
1970 1980 1990 2000 2010 2020
45nm32nm
22nm
Nominal feature size scaling
180nm250nm
365nm248nm
193nm
EUV 13nm
EUV – Technology of the future (forever)?
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Sub-Wavelength Lithography
Light projected through a gap
Mask
193nm light
Lightintensity
Lightintensity
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Sub-Wavelength Lithography
Decrease Presently: 193 nm (ArF excimer laser)(Distant?) future: EUV
Increase NA = nsinαMaximum n is 1 in airPresently: ~0.92-1.35Immersion
Result: Shrinking k1Presently: 0.35 – 0.4Theoretical limit: 0.25
1CD k
NA
min 1
1930.25 50
0.92nm
CD k nmNA
45nm technology beyond resolution limit