EE143 S06 Final Exam Review EE143 LABee143/sp06/lectures/finalexam_review.pdf · Professor N...
Transcript of EE143 S06 Final Exam Review EE143 LABee143/sp06/lectures/finalexam_review.pdf · Professor N...
1Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
EE143 LAB
1
2Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
EE143 Equipment in Cory 218
3Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Si wafer
ProcessingSteps
Guidelines for Process Integration* A sequence of Additive and Subtractive steps with lateral patterning
• Watch out for materials compatibility issues (e.g. temperature limit)• Planarity is desirable for lithography, etching, and thin-film deposition• Whenever possible, use self-aligned structures
4Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
0200400600800
100012001400
Resist
Expos
ure
Resist
Spin-on
Resist
Bak
e
Evap
oratio
n Dep
ositio
n
Sputte
ring D
epos
ition CVD
Ion Im
planta
tion
Post Im
planta
tion A
nnea
l
Therm
al Oxid
ation
Dopan
t Diffu
sion Ep
i
Pro
cess
Tem
per
atu
re in
C
ResistReflow
Al-Si Eutectic (560C)
Si MeltingPoint (1412C)
Processing Temperature and Material Failure Temperature
5Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Self-Aligned Silicide Process (SALICIDE) using Ion
Implantation and Metal-Si reaction
n+n+
TiSi2 (metal)poly-gate
*Self-aligned structures are always preferred for process integration
6Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Layout Design Rules
•Understand the meaning of the boundaries
•Use EE143 design rule values
•Actual layout may look different from conceptual layout when rule values are applied
•Change of design rules values will need understanding of device structures/technology•(qualitative)“conceptual layout”
7Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Summary : Parameters Affecting VT
6
7
n+
Na
VB
5
1
2
4
3
Dopant implant near Si/SiO2 interface
fOX Q&ρ Mφ
xox
VCQn n+
VG-VB= ΦMS+ Vox +VSi
8Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Accumulation
Depletion
Inversion
Vox = Qa/Cox
VSi ~ 0
Vox =qNaxd/Cox
VSi = qNaxd2/(2εs)
Vox = [qNaxdmax+Qn]/Cox
VSi = qNaxdmax2/(2εs)
= 2|ΦF|
Voltage drop = area under E-field curve
* For simplicity, dielectric constants assumed to be same for oxide and Si in E-field sketches
9Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
+ Qf or Qox
B threshold implant
As or P threshold implant
Xox increases
Xox increases
ΦM increases
ΦM decreases
|VCB| increases
|VCB| increases
10Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
DSDS
TGOXn
D VV
VVCLW
I
−−=
2µ
For VD < VDsat
( )2
2 TGOXn
DsatD VVCLW
II −==µ
For VD > VDsat
Note: VDsat = VG - VT
MOSFET I-V Characteristics
11Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Small Signal Capacitance C ( ≡ ∆Q/∆VG)
*p-type substrateCox
12Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Typical Thin Film stress : 108 to 5x1010
dynes/cm2 (107 dyn/cm2 = 1 MPa)
Radius of Curvature of warpage
“Stoney Equation”
r = Es × ts2
( 1- ν)s × 6 ×σf ×tf
13Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
substratesubstrate
Effect of Thin-film Stress Gradient on Cantilever Deflection
substrate
z
(1) No stress gradient along z-direction
(2) Higher tensile stress near top surface of cantileverbefore release from substarte
(3) Higher compressive stress near top surface of cantileverbefore release from substrate
Cantilever
14Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
MEMS Process Flow Example:to form a hollow cantilever beam
15Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
MEMS- IC Integration
Example of MEMS-first approach
16Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Thermal Oxidation Model
CGCs
Co
Ci
X0x
stagnantlayer
SiO2 Si
F1 F2 F3
gastransportflux
diffusionflux
through SiO2
reactionflux
at interface
NoteCs ≠ Co
NoteCs ≠ Co
17Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
CVD Deposition Rate [Grove Model]
F
F
=
=
3
1
kTE
os
G
ekk
hD
∆−=
=δ
F1 F3
Si
film
δ = thickness of stagnant layer
31 FF =
δ
D [ CG - CS] / δ
kS CS
18Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Ion Implantation
C(x)Cp
0.61 Cp
∆Rp
Rpx=0 x
( )( )( )
straggleallongitudinR
rangeprojectedReCpxC
p
p
R
Rx
p
p
=∆
=⋅= ∆
−−2
2
2
CB
xj
Implantation Damage
random scattering path
deeper penetration
Si Crystal
random scattering path
deeper penetration
Si Crystal
Ion Channeling
19Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
T(t)
time
∑=i
ieffective DtDt
BudgetThermal
)()(
welldrive-in
stepS/D
Annealstep
For a complete process flow, only those steps with high Dtvalues are important
For a complete process flow, only those steps with high Dtvalues are important
Examples: Well drive-in and S/D annealing steps
20Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
21Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
point
best
off
Depth of Focus (DOF)
22Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Worst-Case Design Considerations for Etching
step
Substrate
step heightvariation
variationof filmthicknessacross wafer
etching maskcan be eroded
duringfilm etchingMask
film
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Final Exam ReviewEE143 S06
effect
Controlvariable
Effect of RIE process variables on etching characteristics
24Professor N Cheung, U.C. Berkeley
Final Exam ReviewEE143 S06
Multilevel Metallization and Planarization