EE141

1

EE1411

EECS141-S05

EE141EE141--Spring 2005Spring 2005Digital Integrated Digital Integrated CircuitsCircuits

Lecture 10Lecture 10

Introduction to wiresIntroduction to wires

EE1412

EECS141-S05

Administrative StuffAdministrative Stuff

No Lab this weekMidterm 1?Project first part to be announced next Tu

EE141

2

EE1413

EECS141-S05

Last LectureLast Lecture

Last lectureCMOS scaling

Today’s lectureIntroduction to wires

EE1414

EECS141-S05

WiresWires

EE141

3

EE1415

EECS141-S05

The WireThe Wire

transmitte rs rece ivers

schematics physical

EE1416

EECS141-S05

Interconnect Impact on ChipInterconnect Impact on Chip

EE141

4

EE1417

EECS141-S05

Wire ModelsWire Models

All-inclusive model Capacitance-only

EE1418

EECS141-S05

Impact of Interconnect Impact of Interconnect ParasiticsParasiticsInterconnect parasitics

reduce reliabilityaffect performance and power consumption

Classes of parasiticsCapacitiveResistiveInductive

EE141

5

EE1419

EECS141-S05

10 100 1,000 10,000 100,000Length (u)

No

of n

ets

(Log

Sca

le)

Pentium Pro (R)Pentium(R) IIPentium (MMX)Pentium (R)Pentium (R) II

Nature of InterconnectNature of Interconnect

Local Interconnect

Global Interconnect

SLocal = STechnologySGlobal = SDie

Sour

ce: I

ntel

EE14110

EECS141-S05

INTERCONNECTINTERCONNECT

EE141

6

EE14111

EECS141-S05

Capacitance of Wire InterconnectCapacitance of Wire Interconnect

VDD VDD

VinVout

M1

M2

M3

M4Cdb2

Cdb1

Cgd12

Cw

Cg4

Cg3

Vout2

Fanout

Interconnect

VoutVin

CLSimplified

Model

EE14112

EECS141-S05

Capacitance: The Parallel Plate ModelCapacitance: The Parallel Plate Model

Die le ctric

Su bs trate

L

W

H

td i

Ele ctrica l-fie ld lines

Cu rre nt flow

WLt

cdi

diint

ε=

LLCwire SSS

SS 1=

⋅=

EE141

7

EE14113

EECS141-S05

PermittivityPermittivity

EE14114

EECS141-S05

Fringing CapacitanceFringing Capacitance

W - H/2H

+

(a)

(b)

EE141

8

EE14115

EECS141-S05

Fringing versus Parallel PlateFringing versus Parallel Plate

(from [Bakoglu89])

EE14116

EECS141-S05

InterwireInterwire CapacitanceCapacitance

fringing pa rallel

EE141

9

EE14117

EECS141-S05

Impact of Impact of InterwireInterwire CapacitanceCapacitance

(from [Bakoglu89])

EE14118

EECS141-S05

Wiring Capacitances (0.25 Wiring Capacitances (0.25 µµm CMOS)m CMOS)

EE141

10

EE14119

EECS141-S05

INTERCONNECTINTERCONNECT

EE14120

EECS141-S05

Wire Resistance Wire Resistance

W

LH

R = ρH W

L

Sheet ResistanceRo

R1 R2

EE141

11

EE14121

EECS141-S05

Interconnect Resistance Interconnect Resistance

EE14122

EECS141-S05

Dealing with ResistanceDealing with Resistance

Selective Technology ScalingUse Better Interconnect Materials

reduce average wire-lengthe.g. copper, silicides

More Interconnect Layersreduce average wire-length

EE141

12

EE14123

EECS141-S05

PolycidePolycide Gate MOSFETGate MOSFET

n+n+

SiO2

PolySilicon

Silicide

p

Silicides: WSi 2, TiSi2, PtSi2 and TaSi

Conductivity: 8-10 times better than Poly

EE14124

EECS141-S05

Sheet ResistanceSheet Resistance

EE141

13

EE14125

EECS141-S05

Modern InterconnectModern Interconnect

EE14126

EECS141-S05

Example: Intel 0.25 micron ProcessExample: Intel 0.25 micron Process

5 metal layersTi/Al - Cu/Ti/TiNPolysilicon dielectric

EE141

14

EE14127

EECS141-S05

InterconnectInterconnect

EE14128

EECS141-S05

The Lumped ModelThe Lumped ModelVo ut

Drivercwire

VinClumped

Rdriver Vout

EE141

15

EE14129

EECS141-S05

The Distributed RC LineThe Distributed RC Line

EE14130

EECS141-S05

The Elmore DelayThe Elmore DelayRC ChainRC Chain

EE141

16

EE14131

EECS141-S05

Wire ModelWire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

EE14132

EECS141-S05

StepStep--response of RC wire as a response of RC wire as a function of time and spacefunction of time and space

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

0.5

1

1.5

2

2.5

time (nsec)

volta

ge (

V)

x= L/10

x = L/4

x = L/2

x= L

EE141

17

EE14133

EECS141-S05

RC ModelsRC Models

EE14134

EECS141-S05

The Lumped RCThe Lumped RC--ModelModelThe Elmore DelayThe Elmore Delay

EE141

18

EE14135

EECS141-S05

Driving an RCDriving an RC--lineline

Vin

Rs Vout(rw,cw,L)

EE14136

EECS141-S05

Design Rules of ThumbDesign Rules of Thumbrc delays should only be considered when tpRC >> tpgate of the driving gate

Lcrit >> √ tpgate/0.38rcrc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line

trise < RCwhen not met, the change in the signal is slower than the propagation delay of the wire

© MJIrwin, PSU, 2000

EE141

19

EE14137

EECS141-S05

INTERCONNECTINTERCONNECT

EE14138

EECS141-S05

Common Wire CrossCommon Wire Cross--SectionsSections

CoaxialCable

TriplateStrip Line

MicroStrip Wire aboveGround Plane

cl = εµ1

2

1

2

log2

log2

rr

rr

l

c

πµ

πε

=

=

c - capacitance/lengthl - inductance/length

=

=

Whl

Wh

c

µ

ε

EE141

20

EE14139

EECS141-S05

Inductance of package pinsInductance of package pins

Chip

MountingCavity

Lead Frame

Bonding Wire

Pin

L

L’

Make Rise- and Fall Times as slow as possible

EE14140

EECS141-S05

The Transmission LineThe Transmission Line

Vin

r l

c

r l

c

r l

c

r l

c

Voutx

g g g g

The Wave Equation

EE141

21

EE14141

EECS141-S05

Lossless Transmission Line Lossless Transmission Line -- ParametersParameters

vacuumspeed of light in

EE14142

EECS141-S05

Wave Propagation SpeedWave Propagation Speed

EE141

22

EE14143

EECS141-S05

Wave Reflection for Different TerminationsWave Reflection for Different Terminations

EE14144

EECS141-S05

Transmission Line Response (RTransmission Line Response (RLL== ∞∞))

0.0

1.0

2.0

3.0

4.0

5.0

V

0.0

1.0

2.0

3.0

4.0

V

0.0 5.0 10.0 15.0t (in tlightf)0.0

2.0

4.0

6.0

8.0

V

RS = 5Z0

RS = Z0

RS = Z0/5

(a)

(b)

(c)

VDestVSource

EE141

23

EE14145

EECS141-S05

Lattice DiagramLattice Diagram

VSource VDest

0.8333 V

1.6666 V+ 0.8333

+ 0.8333

+ 0.5556

+ 0.5556

+ 0.3704

+ 0.2469

+ 0.3704

+ 0.2469

2.2222 V

3.1482 V

3.7655 V

...

2.7778 V

3.5186 V

4.0124 V

L/ν

t

EE14146

EECS141-S05

Critical Line Lengths versus Rise TimesCritical Line Lengths versus Rise Times

(1990, Bakoglu)

100-200ps today

Lcrit ~ 1cm

EE141

24

EE14147

EECS141-S05

Design Rules of ThumbDesign Rules of ThumbTransmission line effects should be considered when the rise or fall time of the input signal (tr, tf) is smaller than the time-of-flight of the transmission line (tflight).

tr (tf) << 2.5 tflightTransmission line effects should only be considered when the total resistance of the wire is limited:

R < 5 Z0

The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance,

R < Z0/2

EE14148

EECS141-S05

Should we be worried?Should we be worried?

Transmission line effects cause overshooting and non-monotonic behavior

Clock signals in 400 MHz IBM Microprocessor(measured using e-beam prober) [Restle98]

EE141

25

EE14149

EECS141-S05

Next LectureNext Lecture

CMOS Logic