EE108A Lecture 2: Combinational Logic...

21
9/30/2005 1 EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 1 1/14/2008 EE108A Lecture 2: Combinational Logic Design EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 2 1/14/2008 Announcements Prof. Levis will have no office hours on Friday, Jan 18. Labs and sections have been assigned - see the web page Register for eeclass Labs start this week - no prelab for Lab 0 Handouts Lecture notes Homework 2 Lab 1

Transcript of EE108A Lecture 2: Combinational Logic...

Page 1: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

1

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 11/14/2008

EE108A

Lecture 2: Combinational Logic Design

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 21/14/2008

Announcements

• Prof. Levis will have no office hours on Friday, Jan 18.• Labs and sections have been assigned - see the web page• Register for eeclass• Labs start this week - no prelab for Lab 0• Handouts

– Lecture notes– Homework 2– Lab 1

Page 2: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

2

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 31/14/2008

Review

• Lecture 1– The world is digital

• Analog at the edges, hardware for demanding problems, 100x perdecade

– Digital signals• Encode discrete states in a continuous signal• Reject noise

– Representations• Binary, set, continuous, compound

– Boolean Algebra (0,1,∧,∨)• Axioms, properties, duality• Logic equations express binary functions

– Combinational logic• Output is a function only of current input

– Verilog• Defines hardware modules, assign, case

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 41/14/2008

Today

• How to implement combinational logic by hand– Given a description of a logic function– Generate a gate-level circuit that realizes that function

• Everyone needs to do this once– To understand how its done– Demystifies what the synthesis tools do– Better understanding of what synthesis tools can and can’t do– Makes you better at helping synthesis tool do a good job

• In practice you will rarely have to do this by hand• General practice is:

– Design using Verilog– Simulate with test cases– Generate gates with synthesis program

Page 3: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

3

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 51/14/2008

F(d,c,b,a) is true if input d,c,b,a is prime

English language description of a combinational logicfunction

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 61/14/2008

Truth Table

F(d,c,b,a) is true if input d,c,b,a is prime

No dcba q

0 0000 0

1 0001 1

2 0010 1

3 0011 1

4 0100 0

5 0101 1

6 0110 0

7 0111 1

8 1000 0

9 1001 0

10 1010 0

11 1011 1

12 1100 0

13 1101 1

14 1110 0

15 1111 0

Page 4: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

4

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 71/14/2008

F(d,c,b,a) is true if input d,c,b,a is prime

No dcba q

0 0000 0

1 0001 1

2 0010 1

3 0011 1

4 0100 0

5 0101 1

6 0110 0

7 0111 1

8 1000 0

9 1001 0

10 1010 0

11 1011 1

12 1100 0

13 1101 1

14 1110 0

15 1111 0

!=dcba

mf )13,11,7,5,3,2,1(

Equation

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 81/14/2008

Schematic Logic Diagram

!=dcba

mf )13,11,7,5,3,2,1(

d c b a

f

1

2

3

5

7

11

13

!

Equation:

Schematic Logic Diagram:

Page 5: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

5

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 91/14/2008

000 001

010

100

110 111

011

101

1X0

1X1

11X

10X

0X0

0X1

01X

00XX00

X01

X10 X11

XX1

XX0

1XX

0XXX0X

X1X

∑=

cba

mf )7,5,3,2,1(

Cube representation (3-bit prime)

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 101/14/2008

0001

0011

1011

0101

0111

0010

1101

!=dcba

mf )13,11,7,5,3,2,1(

4-D Hypercube (4-bit prime)

Page 6: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

6

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 111/14/2008

4-bit Prime Number Function (cont)

dcba

0xx1

001x

x101

x011

0001

0011

1011

0101

0111

0010

1101

f = (a d) V (b c d) V (a b c) V (a b c)V V V V V V V¯ ¯ ¯ ¯ ¯

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 121/14/2008

0001

0011

1011

0101

0111

0010

1101 0 1 1 1

0 1 1 00 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

00 01 11 10

a

b

c

d0 1 0 0

0 0 1 0

Karnaugh Map of 4-bit Prime

0001

1110

dcba

Page 7: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

7

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 131/14/2008

Position of minterms on a 4-bit Karnaugh map

0 1 3 2

4 5 7 6

baa

12 13 15 14

8 9 11 1000

0111

10

00 01 11 10

d

b

c

dc

Karnaugh Map of 4-bit Prime: Minterms

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 141/14/2008

00000001

1110

0001 0011 0010

0100 0101 0111 0110

1100 1101 1111 1110

1000 1001 1011 1010

Adjacent minterms differ in exactly one bitEvery positive minterm is an implicant

baa

00 01 11 10

d

b

c

dc

Karnaugh Map of 4-bit Prime: Implicants

Page 8: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

8

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 151/14/2008

00000001

1110

0001 001X

0100X101

0111 0110

1100 1111 1110

1000 1001 1011 1010

Can combine adjacent minterms into implicants

baa

00 01 11 10

d

b

c

dc

Karnaugh Map of 4-bit Prime: Larger Implicants

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 161/14/2008

00000001

1110

0001 0010

0100X101

0111 0110

1100 1111 1110

1000 1001 X011 1010

X011

Can combine adjacent minterms into implicantsNote edges wrap around

baa

00 01 11 10

d

b

c

dc

Karnaugh Map of 4-bit Prime: Adjacency

Page 9: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

9

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 171/14/2008

00000001

1110

0XX10010

0100 0110

1100 1101 1111 1110

1000 1001 1011 1010

A larger implicant

baa

00 01 11 10

d

b

c

dc

Karnaugh Map of 4-bit Prime: 0XX1

0001

0011

1011

0101

0111

0010

1101

0001

1110

a

b

c

d

0

00

0

0 0

1

1 1

1 1

1 0 0

1 0

badc00 01 11 10

0001

1110

a

b

c

d

0

412

6

8 9

1

5 7

3 2

13 15 14

11 10

badc 001X

X101

0XX1

00 01 11 10

X011

Why make implicants overlap?

Two reasons:

1. Larger implicants have fewer gates.

2. Hazards. More on them later.

Page 10: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

10

dcba

0xx1

001x

x101

x011

a

d

f

b

c

0XX1

001X

X011

X101

0001

1110

a

b

d

0

00

0

0 0

1

1 1

1 1

1 0 0

1 0

badc 001X

X101

0XX1

00 01 11 10

X011

a

d

f

b

c

In practice, CMOS gates are alwaysinverting, so the real circuit might looklike this

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 201/14/2008

! +=

dcba

Dmf )15,14,13,12,11,10()7,5,3,2,1(

Decimal prime number function – includes don’t cares

00 01 11 10

0001

1110

a

b

c

d

0

0x

0

0 0

1

1 1

1 1

x x x

x x

badc

Page 11: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

11

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 211/14/2008

Decimal prime number function K-Map

1110

0111

a

b

d

0

0x

0

0 0

1

1 1

1 1

x x x

x x

badc

X1X1

00 01 11 10

X01X

0XX1XX11

c

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 221/14/2008

a

bf

c

d 0XX1

X01X

Cover: 0XX1 X01X

f = (a d) V (b c)V V¯ ¯

Decimal prime number function – circuit

0001

1110

a

b

d

0

0x

0

0 0

1

1 1

1 1

x x x

x x

badc 00 01 11 10

X01X

0XX1

c

Page 12: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

12

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 231/14/2008

Revisiting some definitions (and some new ones)

• Minterm: a product term that includeseach input of a circuit or itscomplement.

• Implicant: a product term that if trueimplies the function is true.

• Prime Implicant: is an implicant thatcannot be made any larger and still bean implicant.

• Essential Prime Implicant: the onlyprime implicant that contains aparticular minterm of the function.

• Distinguished One: is a minterm thatis contained in only one implicant.

0001

1110

a

b

d

0

00

0

0 0

1

1 1

1 1

1 0 0

1 0

badc 00 01 11 10

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 241/14/2008

Product-of-Sums Implementation

• Sum-of-Products circuit: focus on inputs states where truth table is a 1.

• Product-of-Sums: focus on input states where truth table is a 0.

• Basic approach: design for the complement, apply DeMorgan’s– We end up with a product of sums, not a sum of products

1 1 1 1

1 1 1 10 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

00 01 11 10ba

dc

101 1

0 10 0

a

b

c

d1 0 0 1

1 1 1 1

!=dcba

Mf )2,0( a∨c∨d

Page 13: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

13

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 251/14/2008

Product-of-Sums Implementation

1 1 1 1

1 1 1 10 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

00 01 11 10ba

dc

1011

010 0

a

b

c

d1 0 0 1

1 1 1 1

!=dcba

Mf )2,0(

0 0 0 0

0 0 0 00 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

00 01 11 10ba

dc

1011

0100

a

b

c

d0 1 1 0

0 0 0 0

¬(a∧c∧d)

a∨c∨d

DeMorgan

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 261/14/2008

Product-of-Sums Example: Decimal Prime

0 1 1 1

0 1 1 00 1 3 2

4 5 7 6

8 9 11 10

12 13 15 14

00 01 11 10ba

dc

1011

0100

a

b

c

dx x x x

0 0 x x

d

ca ∨ba ∨

)15,14,13,12,11,10()15,11,9,7,6( DMfdcba

+=!

Page 14: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

14

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 271/14/2008

0 0 1 1

0 1 1 00 1 3 2

4 5 7 6

00 01 11 10ba

c1

0

a

b

ca

b

cN

f

c

1

1

1

d

e

3

c

cN

d

e

f

Static-1 hazard

Hazards

cb

ca v

v

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 281/14/2008

a

b

cN

f

c

1

1 1

31

0 0 1 1

0 1 1 00 1 3 2

4 5 7 6

00 01 11 10ba

c

10

a

b

c

cb

ca ba

Cover transitions to eliminate hazards

v v

v

Page 15: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

15

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 291/14/2008

Reminder: 4-bit Prime Number Function

a

d

f

b

c

0XX1

001X

X011

X101

dcba

0xx1

001x

x101

x011

a

d

f

b

c

0001

1110

a

b

d

0

00

0

0 0

1

1 1

1 1

1 0 0

1 0

badc 001X

X101

0XX1

00 01 11 10

X011

c

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 301/14/2008

4-bit Prime Number Function in Verilog Code –Using case

module prime(in, isprime) ; input [3:0] in ; // 4-bit input output isprime ; // true if input is prime reg isprime ;

always @(in) begin case(in)

1,2,3,5,7,11,13: isprime = 1'b1 ; default: isprime = 1'b0 ; endcase endendmodule

Page 16: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

16

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 311/14/2008

4-bit Prime Number Function in Verilog Code –Using casex

module prime(in, isprime) ; input [3:0] in ; // 4-bit input output isprime ; // true if input is prime reg isprime ;

always @(in) begin casex(in) 4'b0xx1: isprime = 1 ; 4'b001x: isprime = 1 ; 4'bx011: isprime = 1 ; 4'bx101: isprime = 1 ; default: isprime = 0 ; endcase endendmodule

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 321/14/2008

4-bit Prime Number Function in Verilog Code –Using assign

module prime(in, isprime) ; input [3:0] in ; // 4-bit input output isprime ; // true if input is prime

wire isprime = (in[0] & ~in[3]) | (in[1] & ~in[2] & ~in[3]) | (in[0] & ~in[1] & in[2]) | (in[0] & in[1] & ~in[2]) ;endmodule

Page 17: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

17

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 331/14/2008

Which is a better description? Why?

• Using case• Using casex• Using assign

module prime(in, isprime) ; input [3:0] in ; output isprime ; reg isprime ;

always @(in) begin case(in) 1,2,3,5,7,11,13: isprime = 1'b1 ; default: isprime = 1'b0 ; endcase endendmodule

module prime1(in, isprime) ; input [3:0] in ;

output isprime ; reg isprime ;

always @(in) begin casex(in) 4'b0xx1: isprime = 1 ; 4'b001x: isprime = 1 ; 4'bx011: isprime = 1 ; 4'bx101: isprime = 1 ; default: isprime = 0 ; endcase endendmodule

module prime(in, isprime) ; input [3:0] in ; output isprime ;

wire isprime = (in[0] & ~in[3]) | (in[1] & ~in[2] & ~in[3]) | (in[0] & ~in[1] & in[2]) | (in[0] & in[1] & ~in[2]) ;endmodule

Make your code easy to read, understand, and reason about.

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 341/14/2008

4-bit Prime Number Function in Verilog Code –Result of synthesizing description using case

module prime ( in, isprime );input [3:0] in;output isprime; wire n1, n2, n3, n4; OAI13 U1 ( .A1(n2), .B1(n1), .B2(in[2]), .B3(in[3]), .Y(isprime) ); INV U2 ( .A(in[1]), .Y(n1) ); INV U3 ( .A(in[3]), .Y(n3) ); XOR2 U4 ( .A(in[2]), .B(in[1]), .Y(n4) ); OAI12 U5 ( .A1(in[0]), .B1(n3), .B2(n4), .Y(n2) );endmodule

n2

n1

U1

U5

U2in[1]

in[0]

U3n3in[3]

n4U4

in[2]

isprime

001X

0XX1

X101

X011X01X

X10X

Page 18: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

18

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 351/14/2008

Synthesis Reports****************************************Report : areaDesign : primeVersion: 2003.06Date : Sat Oct 4 11:38:08 2003****************************************

Library(s) Used:

GS30KA_W_125_1.35_CORE.db (File:/home/imagine/from_ti/gs30ka_1.3/sun5/synop

sys/lib/GS30KA_W_125_1.35_CORE.db)

Number of ports: 5Number of nets: 9Number of cells: 5Number of references: 4

Combinational area: 7.000000Noncombinational area: 0.000000Net Interconnect area: undefined (Wire load has zero

net area)

Total cell area: 7.000000Total area: undefined

****************************************Report : timing -path full -delay max -max_paths 1Design : primeVersion: 2003.06Date : Sat Oct 4 11:38:08 2003****************************************

Operating Conditions:Wire Load Model Mode: enclosed

Startpoint: in[2] (input port) Endpoint: isprime (output port) Path Group: (none) Path Type: max

Des/Clust/Port Wire Load Model Library ------------------------------------------------ prime 2K_5LM

GS30KA_W_125_1.35_CORE.db

Point Incr Path ----------------------------------------------------------

- input external delay 0.000 0.000 r in[2] (in) 0.000 0.000 r U4/Y (EX210) 0.191 0.191 f U5/Y (BF051) 0.116 0.307 r U1/Y (BF052) 0.168 0.475 f isprime (out) 0.000 0.475 f data arrival time 0.475 ----------------------------------------------------------

- (Path is unconstrained)

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 361/14/2008

Constraint File

create_clock "clk" -name clk -period 2 -waveform {0 1.7}set_clock_uncertainty 0.2 clkset_fix_hold all_clocks()set_load -pin_load 5 {isprime}

set_input_delay 0.5 -clock clk {in}

set_output_delay -max 0.8 -clock clk {isprime}

Page 19: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

19

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 371/14/2008

Test bench

module test_prime ; reg [3:0] in ; wire isprime ;

// instantiate module to test prime p0(in, isprime) ;

initial begin in = 0 ; repeat (16) begin #100 $display("in = %2d isprime = %1b",in,isprime) ; in = in+1 ; end endendmodule

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 381/14/2008

Test benches use a very different style of verilog

• Initial statements• $display• Repeat and other looping constructs• #delay

• Don’t use these constructs in synthesizable modules

Page 20: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

20

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 391/14/2008

Testing Result

# in = 0 isprime = 0# in = 1 isprime = 1# in = 2 isprime = 1# in = 3 isprime = 1# in = 4 isprime = 0# in = 5 isprime = 1# in = 6 isprime = 0# in = 7 isprime = 1# in = 8 isprime = 0# in = 9 isprime = 0# in = 10 isprime = 0# in = 11 isprime = 1# in = 12 isprime = 0# in = 13 isprime = 1# in = 14 isprime = 0# in = 15 isprime = 0

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 401/14/2008

1514131211109876543210

Wave output

Page 21: EE108A Lecture 2: Combinational Logic Designweb.stanford.edu/.../ee108a.1082/lectures/02-combinational-w08.pdf · EE108A Lecture 2: Combinational Logic Design ... –Lecture notes

9/30/2005

21

module prime_dec(in, isprime) ; input [3:0] in ; // 4-bit input output isprime ; // true if input is prime reg isprime ;

always @(in) begin casex(in) 0,4,6,8,9: isprime = 1’b0 ; 1,2,3,5,7: isprime = 1’b1 ; default: isprime = 1’bx ; endcase endendmodule

EE 108A Lecture 2 (c) 2005-2008 W. J. Dally and P. Levis 421/14/2008

Summary

• To minimize logic– Write K-map– Find all prime implicants– Pick a minimal set of prime implicants that covers the function

• Hazards (output glitches) can be eliminated by covering transitions• Verilog

– Can represent with case, casex, assign, or structurally– Use representation that is readable and maintainable

• case for truth tables• assign for equations• Don’t try to do the logic design yourself

– Synthesis tool will do the optimization– Test benches check that implementation meets its specification

• Test benches use a different style of Verilog