EE105 Fall 2007 Lecture 7, Slide 1 Prof. Liu, UC Berkeley

Lecture 7

OUTLINE• BJT Amplifiers (cont’d)– Biasing– Amplifier topologies– Common-emitter topology

Reading: Chapter 5.1.2-5.3.1

ANNOUNCEMENTS• MIDTERM #1 will be held in class on Thursday, October 11

– Review session will be held on Friday, October 5• MIDTERM #2 will be held in class on Tuesday, November 13

EE105 Fall 2007 Lecture 7, Slide 2 Prof. Liu, UC Berkeley

Biasing of BJT• Transistors must be biased because

1. They must operate in the active region, and2. Their small-signal model parameters are set by the bias

conditions.

EE105 Fall 2007 Lecture 7, Slide 3 Prof. Liu, UC Berkeley

DC Analysis vs. Small-Signal Analysis• Firstly, DC analysis is performed to determine the DC

operating point and to obtain the small-signal model parameters.

• Secondly, independent sources are set to zero and the small-signal model is used.

EE105 Fall 2007 Lecture 7, Slide 4 Prof. Liu, UC Berkeley

Simplified Notation• Hereafter, the voltage source that supplies power to

the circuit is replaced by a horizontal bar labeled VCC, and input signal is simplified as one node labeled vin.

EE105 Fall 2007 Lecture 7, Slide 5 Prof. Liu, UC Berkeley

Example of Bad Biasing• The microphone is connected to the amplifier in an attempt

to amplify the small output signal of the microphone. • Unfortunately, there is no DC bias current running through

the transistor to set the transconductance.

EE105 Fall 2007 Lecture 7, Slide 6 Prof. Liu, UC Berkeley

Another Example of Bad Biasing• The base of the amplifier is connected to VCC, trying

to establish a DC bias. • Unfortunately, the output signal produced by the

microphone is shorted to the power supply.

EE105 Fall 2007 Lecture 7, Slide 7 Prof. Liu, UC Berkeley

Biasing with Base Resistor• Assuming a constant value for VBE, one can solve for

both IB and IC and determine the terminal voltages of the transistor.

• However, the bias point is sensitive to variations.

EE105 Fall 2007 Lecture 7, Slide 8 Prof. Liu, UC Berkeley

Improved Biasing: Resistive Divider• Using a resistive divider to set VBE, it is possible to

produce an IC that is relatively insensitive to variations in , if the base current is small.

EE105 Fall 2007 Lecture 7, Slide 9 Prof. Liu, UC Berkeley

Accounting for Base Current• With a proper ratio of R1 to R2, IC can be relatively

insensitive to . However, its exponential dependence on R1 // R2 makes it less useful.

EE105 Fall 2007 Lecture 7, Slide 10 Prof. Liu, UC Berkeley

Emitter Degeneration Biasing• RE helps to absorb the change in VX so that VBE stays

relatively constant.• This bias technique is less sensitive to (if I1 >> IB)

and VBE variations.

EE105 Fall 2007 Lecture 7, Slide 11 Prof. Liu, UC Berkeley

Bias Circuit Design Procedure1. Choose a value of IC to provide the desired small-

signal model parameters: gm, r, etc.

2. Considering the variations in R1, R2, and VBE, choose a value for VRE.

3. With VRE chosen, and VBE calculated, Vx can be determined.

4. Select R1 and R2 to provide Vx.

EE105 Fall 2007 Lecture 7, Slide 12 Prof. Liu, UC Berkeley

Self-Biasing Technique• This bias technique utilizes the collector voltage to

provide the necessary Vx and IB.• One important characteristic of this approach is that

the collector has a higher potential than the base, thus guaranteeing active-mode operation of the BJT.

EE105 Fall 2007 Lecture 7, Slide 13 Prof. Liu, UC Berkeley

Self-Biasing Design Guidelines

(1) provides insensitivity to .

(2) provides insensitivity to variation in VBE .

BECCBE

BC

VVV

RR

2)(

(1)

EE105 Fall 2007 Lecture 7, Slide 14 Prof. Liu, UC Berkeley

Summary of Biasing Techniques

EE105 Fall 2007 Lecture 7, Slide 15 Prof. Liu, UC Berkeley

PNP BJT Biasing Techniques• The same principles that apply to NPN BJT biasing

also apply to PNP BJT biasing, with only voltage and current polarity modifications.

EE105 Fall 2007 Lecture 7, Slide 16 Prof. Liu, UC Berkeley

Possible BJT Amplifier Topologies• There are 3 possible ways to apply an input to an

amplifier and 3 possible ways to sense its output.• In practice, only 3 out of the possible 6 input/output

combinations are useful.

EE105 Fall 2007 Lecture 7, Slide 17 Prof. Liu, UC Berkeley

Common-Emitter (CE) Topology

EE105 Fall 2007 Lecture 7, Slide 18 Prof. Liu, UC Berkeley

Small Signal of CE Amplifier

in

outv v

vA

EE105 Fall 2007 Lecture 7, Slide 19 Prof. Liu, UC Berkeley

Limitation on CE Voltage Gain • Since gm = IC/VT, the CE voltage gain can be written as

a function of VRC , where VRC = VCC - VCE.

• VCE should be larger than VBE for the BJT to be operating in active mode.

T

RC

T

CCv V

V

V

RIA

EE105 Fall 2007 Lecture 7, Slide 20 Prof. Liu, UC Berkeley

Voltage-Gain / Headroom Tradeoff

EE105 Fall 2007 Lecture 7, Slide 21 Prof. Liu, UC Berkeley

I/O Impedances of CE Stage• When measuring output impedance, the input port

has to be grounded so that vin = 0.

riv

RX

Xin C

X

Xout R

i

vR

EE105 Fall 2007 Lecture 7, Slide 22 Prof. Liu, UC Berkeley

CE Stage Design Trade-offs

EE105 Fall 2007 Lecture 7, Slide 23 Prof. Liu, UC Berkeley

Inclusion of the Early Effect• The Early effect results in reduced voltage gain of the

CE amplifier.

OCout

OCmv

rRR

rRgA

||

)||(

EE105 Fall 2007 Lecture 7, Slide 24 Prof. Liu, UC Berkeley

Intrinsic Gain• As RC goes to infinity, the voltage gain approaches its

maximum possible value, gm × rO, which is referred to as the intrinsic gain.

• The intrinsic gain is independent of the bias current:

T

Av

Omv

VV

A

rgA

EE105 Fall 2007 Lecture 7, Slide 25 Prof. Liu, UC Berkeley

Current Gain, AI

• The current gain is defined as the ratio of current delivered to the load to current flowing into the input.

• For a CE stage, it is equal to .

CEI

in

outI

A

i

iA