Editorial Hardware Implementation of Digital Signal...
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Hindawi Publishing Corporation Journal of Electrical and Computer Engineering Volume 2013, Article ID 782575, 2 pages http://dx.doi.org/10.1155/2013/782575 Editorial Hardware Implementation of Digital Signal Processing Algorithms Ashkan Ashrafi, 1 Antonio G. M. Strollo, 2 and Oscar Gustafsson 3 1 Department of Electrical and Computer Engineering, San Diego State University, San Diego, CA 92182, USA 2 Department of Biomedical, Electronic and Telecommunications Engineering, University of Napoli Federico II, 80125 Napoli, Italy 3 Department of Electrical Engineering, Link¨ oping University, SE-581 83 Link¨ oping, Sweden Correspondence should be addressed to Ashkan Ashrafi; ashrafi@mail.sdsu.edu Received 4 June 2013; Accepted 4 June 2013 Copyright © 2013 Ashkan Ashrafi et al. is is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Advances in integrated circuits have provided high-per- formance and high-speed digital circuitries in the form of Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) that enable us to imple- ment complicated digital signal processing algorithms in hardware. With this new technology, real-time realization of complex algorithms is a reality. e application of hardware implementation of digital signal processing algorithms is extended from communication systems, digital filter design, and image and video processing applications to implementa- tion of complex mathematical procedures for data analysis. e need to use hardware implementations of digital signal processing algorithms is exponentially increasing due to the explosion of stored data and the necessity of analyzing these data in less amount of time. is goal cannot simply be accomplished by computer soſtware because they are running in operating systems hence lower processing speed. is special issue was aimed to address some of the challenges engineers and scientists face in hardware imple- mentation of DSP algorithms and provide solutions for some of these challenges. Several papers were submitted to this special issue and aſter an extensive review process, five were selected for publication. In the paper “Efficient parallel carrier recovery for ultra- high speed coherent QAM receivers with applications to optical channels,” P. Gianni et al. proposed a novel scheme that is a combination of low-latency parallel digital phase locked loop (DPLL) with a feed-forward carrier phase recovery algorithm (CPR). eir novel low-latency parallel DPLL compensates both carrier frequency offset and frequency fluctuations. To enable parallel processing implementation of the algorithm in multigigabit per second receivers, they introduced a new approximation to the DPLL computation. eir technique reduces the latency in the feedback loop of the DPLL caused by parallel processing and it provides a bandwidth and capture range close to those achieved by serial DPLL. A. L. Pola et al. proposed the implementation of an improved decision feed-forward equalizer (DFFE) for high- speed receivers in the presence of highly dispersive channels in their paper entitled “A low-complexity decision feedforward equalizer architecture for high-speed receivers on highly dis- persive channels.” is new DFFE prevents the exponential increase in complexity by using tentative decision to can- cel iteratively the intersymbol interference (ISI). ey also showed that the proposed DFFE reduces the complexity in channels with large memory. In the paper “Holistic biquadratic IIR filter design for communication systems using differential evolution,” A. Melzer et al. introduced a holistic design flow with the system’s bit error rate as the objective function to be optimized. ey used Differential Evolution to find the quantized filter coefficients that optimize the objective function. ey showed that very small number of formats is acceptable for complex filters. ey also showed that the choice between fixed-point and floating-point numbers is nontrivial if a precision is a free parameter. In the paper “Asynchronous realization of algebraic integer-based 2D DCT using achronix speedster SPD60 FPGA,”
Transcript of Editorial Hardware Implementation of Digital Signal...
Hindawi Publishing CorporationJournal of Electrical and Computer EngineeringVolume 2013, Article ID 782575, 2 pageshttp://dx.doi.org/10.1155/2013/782575
EditorialHardware Implementation of Digital SignalProcessing Algorithms
Ashkan Ashrafi,1 Antonio G. M. Strollo,2 and Oscar Gustafsson3
1 Department of Electrical and Computer Engineering, San Diego State University, San Diego, CA 92182, USA2Department of Biomedical, Electronic and Telecommunications Engineering, University of Napoli Federico II,80125 Napoli, Italy
3 Department of Electrical Engineering, Linkoping University, SE-581 83 Linkoping, Sweden
Correspondence should be addressed to Ashkan Ashrafi; [email protected]
Received 4 June 2013; Accepted 4 June 2013
Copyright © 2013 Ashkan Ashrafi et al.This is an open access article distributed under the Creative Commons Attribution License,which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Advances in integrated circuits have provided high-per-formance and high-speed digital circuitries in the form ofApplication Specific Integrated Circuits (ASICs) and FieldProgrammable Gate Arrays (FPGAs) that enable us to imple-ment complicated digital signal processing algorithms inhardware. With this new technology, real-time realization ofcomplex algorithms is a reality. The application of hardwareimplementation of digital signal processing algorithms isextended from communication systems, digital filter design,and image and video processing applications to implementa-tion of complex mathematical procedures for data analysis.The need to use hardware implementations of digital signalprocessing algorithms is exponentially increasing due to theexplosion of stored data and the necessity of analyzing thesedata in less amount of time. This goal cannot simply beaccomplished by computer software because they are runningin operating systems hence lower processing speed.
This special issue was aimed to address some of thechallenges engineers and scientists face in hardware imple-mentation of DSP algorithms and provide solutions for someof these challenges. Several papers were submitted to thisspecial issue and after an extensive review process, five wereselected for publication.
In the paper “Efficient parallel carrier recovery for ultra-high speed coherent QAM receivers with applications to opticalchannels,” P. Gianni et al. proposed a novel scheme that is acombination of low-latency parallel digital phase locked loop(DPLL) with a feed-forward carrier phase recovery algorithm(CPR). Their novel low-latency parallel DPLL compensates
both carrier frequency offset and frequency fluctuations. Toenable parallel processing implementation of the algorithmin multigigabit per second receivers, they introduced a newapproximation to the DPLL computation. Their techniquereduces the latency in the feedback loop of the DPLL causedby parallel processing and it provides a bandwidth andcapture range close to those achieved by serial DPLL.
A. L. Pola et al. proposed the implementation of animproved decision feed-forward equalizer (DFFE) for high-speed receivers in the presence of highly dispersive channelsin their paper entitled “A low-complexity decision feedforwardequalizer architecture for high-speed receivers on highly dis-persive channels.” This new DFFE prevents the exponentialincrease in complexity by using tentative decision to can-cel iteratively the intersymbol interference (ISI). They alsoshowed that the proposed DFFE reduces the complexity inchannels with large memory.
In the paper “Holistic biquadratic IIR filter design forcommunication systems using differential evolution,” A.Melzeret al. introduced a holistic design flow with the system’s biterror rate as the objective function to be optimized.They usedDifferential Evolution to find the quantized filter coefficientsthat optimize the objective function. They showed that verysmall number of formats is acceptable for complex filters.They also showed that the choice between fixed-point andfloating-point numbers is nontrivial if a precision is a freeparameter.
In the paper “Asynchronous realization of algebraicinteger-based 2DDCTusing achronix speedster SPD60 FPGA,”
2 Journal of Electrical and Computer Engineering
N. Rajapaksha et al. introduced an FPGA implementationof algebraic-integer (AI) based discrete cosine transform(DCT) algorithms. These algorithms are implemented andtested on asynchronous quasi delay-insensitive logic usingAchronix SPD60 FPGA. They showed that their designhas an improvement of 31% over the integer DCT in thenumber of transform coefficients having 1% error. They alsoinvestigated the performance of the 65 nm asynchronoushardware in terms of speed and operation and compared itwith those of 65 nm synchronous Xilinx FPGA. With thewordlengths of 5 and 6 bits, they observed increases of230% and 199%, respectively. This indicates that AI DCT canbe used in High Efficiency Video Coding for applicationsdemanding high accuracy and high throughput provided thatnovel quantization schemes are devised to allow accuracyimprovements.
In the paper “FPGA implementation of gaussian mixturemodel algorithm for 47fps segmentation of 1080p video,” M.Genovese et al. proposed the hardware implementation ofthe improved formulation of the Gaussian mixture model(GMM) algorithm in theOpenCV library.This design utilizesa hardware oriented formulation of theGMMequation, trun-cated binary multipliers, and ROM compression techniquesto reduce the hardware complexity and to increase processingcapability. They implemented their design on Virtex6 andStratixIV FPGAs. The implemented hardware can process 45frames per second in 1080p format and uses a few percent ofFPGA logic resources.
The guest editors would like to thank all authors who con-tributed to this special issue.We also thank the reviewers whogenerously gave their time to review the papers. We hope thisspecial issue would be useful for the readers and researcherswho are working in the area of hardware implementations ofthe DSP algorithms.
Ashkan AshrafiAntonio G. M. Strollo
Oscar Gustafsson
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