ECE 126

Introduction to Analog Integrated Circuits Design

Lab 1: MOSFET DC Ids – Vds Characteristic Curve &

Spice Extraction of Small-Signal Model Parameters

Submitted by:

Guisadio, Johanna Whil R.

Submitted to:

Prof. Allenn Lowaton

September 26, 2015

Step 1:

Connect the NMOS and PMOS. Simulate the Ids-Vgs characteristic

curve.

a.) NMOS

HSPICE CODE: .OP RESULT

Figure 1: Ids-Vgs characteristic curve of an NMOS.

The graph in Figure 1 shows the characteristics of the drain current as gate-to-

source voltage is increased. There is no current flow when Vgs is less than Vth (|Vtn|).

Beyond Vgs, the current will start to increase almost linearly before if saturates.

b.) PMOS

HSPICE CODE: .OP RESULT

Figure 2: Ids-Vgs characteristic curve of a PMOS.

This graph in Figure 2 shows the characteristic of the drain current in a PMOS.

As with that of an NMOS, no current flows when the gate-to-source voltage is less than

the threshold voltage. If Vgs is further increased such that its magnitude is more than the

threshold voltage, there will now be current flowing and will linearly increase as Vgs is

increased. Thus, the direction of the current flow in a PMOS is opposite in an NMOS

with respect to the drain and source.

Step 2:

Disconnect the gate and the drain of the MOS of the figure 1.2(a). Then, assign

the different values of Vgs to its gate terminal. Simulate the Ids-Vgs characteristic curve.

a.) NMOS

HSPICE CODE: .OP RESULT

Figure 3. Ids-Vds characteristic curve of an NMOS with W/L=0.5u/0.18u.

This graph shows how increasing the gate-to-source voltage increases the drain

current. As the gate voltage is increased, there will be greater channel inversion in the

substrate of a NMOS allowing more current to flow through.

Vgs

=0.595V

Vgs

=0.58V

Vgs

=0.56V

Vgs

=0.54V

b.) PMOS

HSPICE CODE: .OP RESULT

Figure 4. Ids-Vds characteristic curve of an NMOS with W/L=0.5u/0.185u.

Same in NMOS, more current will flow as the magnitude of the gate-to-source

voltage is increased Noted that the Vgs applied must be negative, that is, the way it is

“wired” must be opposite with respect to that of an NMOS so that the p-substrate will be

repelled away from the gate to allow channel inversion.

Vgs

= -0.65V

Vgs

= -0.70V

Vgs

= -0.75V

Vgs

= -0.82V

Step 3:

Follow Step 2, change the channel length. Simulate the Ids-Vgs characteristic curve.

HSPICE CODE: .OP RESULT

a.) NMOS

Figure 5. An NMOS Ids-Vds characteristic curve with W=0.5u.

The drain current is inversely proportional with the length of the channel since

longer channel creates more resistance. As shown in the graph, the longer the channel

length, the less the current flows and so there is less saturation current also.

l=0.18u

l=0.20u

l =0.25u

l=0.30u

b.) PMOS

HSPICE CODE: .OP RESULT

Figure 6. A PMOS Ids-Vds characteristic curve with W=0.5u.

Changing the channel length in NMOS also applies to PMOS. Longer channel

lessens the saturation current in the device while shorter channels allows more current

to flow. At higher drain current flow, more gate-to-source voltage is needed to achieve

saturation.

l= 0.258u

l= 0.22u

l= 0.20u

l= 0.18u

Step 4:

Set |Vgs| to a value smaller than |Vt| to operate the MOS in subthreshold region.

Simulate the Ids-Vgs characteristic curve.

Figure 7: Ids-Vgs characteristic curve of an NMOS operated in subthreshold region.

(Noted: y-axis is in log scale).

HSPICE CODE:

a.) NMOS

In the subthreshold region, the gate-to-source voltage is less than the effective

voltage. The current of the graph is in logarithmic scale to show the exponential

relationship between drain current and Vgs in this region of operation.

Figure 8: Ids-Vgs characteristic curve of a PMOS operated in subthreshold region.

(Noted: y-axis is in log scale).

b.) PMOS

HSPICE CODE:

We can see from this graph that at subthreshold region, the drain currents at

different gate-to-source voltages differ exponentially. We can observe that as currents

increased, the drain-to-source voltage also increased.

Questions:

1. If we increase W/L of the device in Step 1, what changes will occur to the curve?

- As the W/L of the device increased, the curve will have a bigger slope

either in NMOS or PMOS. Since resistance is inversely proportional to W/L, so

as the channel width increased and decreased the channel length, resistance will

also decrease. Thus, there will be more current flowing through the channel of

the MOSFET.

2. When the dimensions Wn/Ln equal Wp/Lp, does |Idsp|/Idsn equal µp/µn?

- Yes. Using the equation of ID at the saturation region (or in any other

region).

;;

since,

so,

3. What relationship between the channel length and the slope of Ids – Vds

Characteristic Curve of NMOS and PMOS?

- When the channel length is increased, the slope of the characteristic curve

will decrease. So, when the channel length is shortened, more current can flow

due to less resistance and the graph will become steeper.

4. When the MOSFET operates in subthreshold region, what is the relationship

between Vgs and the slope of the Ids – Vgs Characteristic Curve? What device,

either PMOS or NMOS, has the larger slope? Why?

- The drain current depends exponentially on the gate-source voltage in

sub-threshold region. NMOS has a larger slope because it has larger current

than PMOS.

CONCLUSION:

As we observe in the characteristic curve of NMOS and PMOS, there is no

current flow when the gate-to-source voltage is less than the threshold voltage. But

when we increased the Vgs such that its magnitude is more than the threshold voltage,

the current will linearly increase as Vgs is increased. If we compare the current that flows

in NMOS AND PMOS, the direction of the current flow in a PMOS is opposite in an

NMOS with respect to the drain and source.

There are some factors that can affect the drain current, such that, as we

increased the gate-to-source voltage, the drain current also increases. Aside from the

gate-to-source voltage, one factor that can increase the amount of current at increased

Vgs is the channel length where the drain current is inversely proportional with the length

of the channel. And in the subthreshold region, when the gate-to-source voltage is

smaller than the Vth, there is still current flowing from drain to source.