ECE-522 CMOS Integrated Circuits-I

Project report :Design of A Two Stage Miller Compensated Op-Amp

Submitted By: Romesh Kumar Nandwana

Abstract:

In this project A two stage miller compensated Op-Amp has been designed for the given

specifications. Open loop gain of the amplifer is achieved as 68.53dB with the phase margin of

62.27 degree and Unity gain bandwidth of 16.677MHz on 6pF load capacitor .Power Supply

rejection ratio and Input reffered noise voltages have been measured on the Op-Amp .Circuit

simulation was performed using BSIM3 model with Cadence Custom IC Design Suite on 0.18um

process.

Introduction:

Operational Amplifiers are one of the most basic building blocks of the analog circuit. In this

project a miller compensated opamp has been designed for the given specifications.

For designing the compensation network Miller compensation or Pole Splitting technique is used

in which we choose the compensation capacitor value in such a way that the second pole is at

unity gain frequency and the zero of the circuit is pushed to the Left Half plane to provide the

better phase margin.

The designed circuit consist of 8 transistor with a bias current source and comensation Capacitor

and Zero nulling resistor.

Design Approch:

For designing the circuit at first the process parameters are extracted from the model using some

basic techniques. To neglect the short channel effect minimum channel length is choosen as

540nm and W/L ratio of transistors is calculated in the multiplication of this channel length only.

For the determiniation of K’ and Vt the following relation is used. For small Vds voltage

From here the k’ and Vt are calculated for NMOS and PMOS.

Similarly from the other relation Id = Io (1+λ VDS) We can calculate the value of λ for both

NMOS and PMOS transistors. The calculated values of the parametes are shown in the table1.

TABLE-1

Parameter Value

K’N 290µA/V2

K’P 70µA/V2

VTN 450mV

VTP 450mV

λN 0.085

λP 0.085

Now form here we set the overdrive voltage for the design as 200mV and bias current as 20mu

A.Current in the second branch is selected as 5 times of the bias current so that there will be no

major effect of the load capacitance on the slew rate and it will be only dependedent upon the

Compensation capacitance value. Because no information is given about the slew rate in the

design specification so these value is choosen as for the ease of designing the circuit.

Now from the gain constraint we divide our over all gain into two stages such as gm of the

second stage is 5 times then the gm of differencial stage. From here we calculate the gain of the

differential stage with the consideration of Unity gain freq as UGB= Gm1/Cc where gm1 is the

gain of the first stage and Cc is the compensation capacitance which is not known yet. And from

the dc bias current values we can calculate the gain of both stages for the selected W/L ratio.

W/L of M6 is selected in such a manner so that we can avoid the systematic offset error.

And from here the w/l ratio of all the transistors is decided as given in the following table.

To include the effect of junction capacitances in the design source and drain diffusion area is

defined as AD=AS= 0.6 $\mu$ m *W and source and drain periphery is defined as PD=PS= 1.2

$\mu$ m + 2 W where W is the width of the MOS transistor.

Now for miller compensation the second pole is put at the unity gain freq and from this relation

the value of compensation capacitor is calculated.

Cc = gm1/gm2 *CL where gm1 and gm2 are the respective gm of first and second stage and CL

is the load capacitance.

With this value of Cc the unity gain freq value is verified and it is more the the desired

specification.

And AC response is measured in this condition. From here we can see that the gain and unity

gain bandwidth are meeting the desing specifications but the phase margin is low as we have a

right half plane zero.

So to move this zero into the left half plane we put a zero nulling resistor in series with

compensation capacitor and its value is calculated from the formula tha R > 1/gm2 and the value

of R is calculated form here.

Results :

Figure 1 shows the schematic of the designed 2stage opamp and table 2 shows the W/L ratio of

all the transistors.

TABLE-2

Parameter Value Parameter Value

W1 30*L W2 30*L

W3 2*L W4 2*L

W5 12*L W6 21*L

W7 60*L W8 6*L

Rz 2.5K Cc 1.2pF

Figure-1: Opamp Schematic

Table 3 shows the comparison of desired specifications and the simulated results. And The gain

and phase response is shown in figure 2 and the common mode range of the opamp can be seen

in figure 3.

TABLE-3

Parameter Specifications Simulated result

Open Loop Gain >68dB 68.35dB

Phase Margin >60o 63.5

o

Unity gain freq >12Mhz 16.677MHz

ICMR -7.48Vto 1.019V

Figure :2 Open Loop Response

Figure :3 ICMR

from figure 5 we can see the PSRR of the opamp.

Figure5-a PSRR due to VDD

Figure5-b PSRR due to VSS

Figure 6 gives us the Input reffered noise voltage at 1KHz and 4MHz.

Figure:6 Input reffered Noise

Conclusion:

The opamp has beed designed successfully and meet the desired specifications.

Refernces :

[1]. Kartikeya Mayaram,Lacture Notes –ECE-522,Oregon State University, 2010.

Appendix

NMOS Characterization curves

Id Vs Vgs Curve for VDS=20mV

Id Vs Vds Curve for Vgs=700mV

PMOS Characterisation curves

Id Vs Vgs Curve for VDS=20mV

Id Vs Vds Curve for Vgs=700mV

Pole Zero Summery:

****************

PZ Analysis `pz'

****************

Warning from spectre during PZ analysis `pz'.

BSIM3v3 MOS Transistor - frequency dependent components are present in

the circuit, approximated as AC equivalents at 1.000000e+03Hz for pz

analysis.

Poles (Hz)

Real Imaginary Qfactor

1 -7.36454e+03 0.00000e+00 5.00000e-01

2 -2.37168e+07 0.00000e+00 5.00000e-01

3 -7.00802e+07 0.00000e+00 5.00000e-01

4 -4.58731e+08 +/- 1.87173e+08 5.40019e-01

5 -6.45264e+08 0.00000e+00 5.00000e-01

Zeros (Hz)

at V(Out,0)/V7

Real Imaginary Qfactor

1 -6.24905e+07 0.00000e+00 5.00000e-01

2 -9.90301e+07 0.00000e+00 5.00000e-01

3 -4.51702e+08 +/- 2.68905e+08 5.81893e-01

4 6.21998e+08 0.00000e+00 -5.00000e-01

5 3.39008e+09 0.00000e+00 -5.00000e-01

Constant factor = 1.40654e-03

DC gain = 2.61611e+03