ECE371-Lab1Report-Group2
Transcript of ECE371-Lab1Report-Group2
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EE371 Lab 1 Report Group2-10ES 2013 June Page 0
Danang University of Technology
ECE371 Lab1Report
WORKING ON GPIO PORTOF ARM CORTEX 3M LM3S8962
Instructor: NguyenTheNghia
Group 2-10ES:TranVanLoc
LeTrungHieu
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Experiment 1: Turn on User Led at Pin 47 PF0/PWM0.
+Create new Project in IAR.
Open IAR Embedded Workbench IDE. Select Workspace in direction C:\StellarisWare\boards\ek-
lm3s8962. Generate new project in IAR. Create new folder for the Project named Lab1a and givethe project a name call Lab1a. Write below C code into file main.c.
#include "inc/lm3s8962.h"
intmain(void){
volatile unsigned long ulLoop;
SYSCTL_RCGC2_R = SYSCTL_RCGC2_GPIOF;
GPIO_PORTF_DIR_R = 0x01;GPIO_PORTF_DEN_R = 0x01;
while(1){// Enable the GPIO port that is used for the on-board LED.SYSCTL_RCGC2_R = SYSCTL_RCGC2_GPIOF;
// Do a dummy read to insert a few cycles after enabling the peripheral.ulLoop = SYSCTL_RCGC2_R;
// Enable the GPIO pin for the LED (PF0). Set the direction as output, and// enable the GPIO pin for digital function.GPIO_PORTF_DIR_R = 0x01;GPIO_PORTF_DEN_R = 0x01;
// Loop forever.while(1){
// Turn on the LED.GPIO_PORTF_DATA_R |= 0x01;
// Delay for a bit.for(ulLoop = 0; ulLoop < 200000; ulLoop++){}
// Turn off the LED.GPIO_PORTF_DATA_R &= ~(0x01);
// Delay for a bit.for(ulLoop = 0; ulLoop < 200000; ulLoop++){}
}
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+ Answer to the questions: (According to lm3s8962.h and refer to datasheet of
lm3s8962)
1. What is the SYSCTL_RCGC2_R ?RCGC2 stands for Run mode Clock Gating Control register 2. This register controls the clock gating
logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clockand functions. Otherwise, the unit is unclocked and disabled (for saving power). If the unit is unclocked,
reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless
otherwise noted, so that all functional units are disabled.
2. What are SYSCTL_RCGC2_R, GPIO_PORTF_DIR_R, GPIO_PORTF_DEN_R andGPIO_PORTF_DATA_R?
RCGC2 stands for Run mode Clock Gating Control register 2. This register controls the clock gating
logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock
and functions. Otherwise, the unit is unclocked and disabled (for saving power). If the unit is unclocked,
reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless
otherwise noted, so that all functional units are disabled.
GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the
corresponding pin to be an output, while bits set to 0 configure the corresponding pins to be inputs. All bits
are cleared by a reset, meaning all GPIO pins are inputs by default.GPIO Port F has the base address of
0x4002.5000 and offset of 0x400 (for direction). Thus, the address of GPIO_PORTF_DIR_R is
0x40025400.
GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used
for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their
digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage
into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the
corresponding GPIODEN bit must be set. GPIO Port F has the base address of 0x4002.5000 and offset of
0x51C (for digital enable). Thus, the address of GPIO_PORTF_DEN_R is 0x4002551C.
GPIODATA register is the data register. In software control mode, values written in the GPIODATA
register are transferred onto the GPIO port pins if the respective pins have been configured as outputs
through the GPIODIR register. In order to write to GPIODATA, the corresponding bits in the mask,
resulting from the address bus buts [9:2], must be High. Otherwise, the bit values remain unchanged by the
write. Similarly, the values read from this register are determined for each bit by the mask bit dereved from
the address used to access the data register, bits [9:2]. Bits that are 1in the address mask cause the
corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the
corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns
the last bit value written if the respective pins are configured as outputs, or it returns the value on the
corresponding input pin when these are configured as inputs. All bits are cleared by a reset.
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3. Write out the mapped memory address of SYSCTL_RCGC2_R, GPIO_PORTF_DIR_R,
GPIO_PORTF_DEN_R and GPIO_PORTF_DATA_R.
SYSCTL_RCGC2_R 0x400FE108
GPIO_PORTF_DIR_R 0x40025400
GPIO_PORTF_DEN_R 0x4002551C
GPIO_PORTF_DATA_R 0x400253FC
4. In Disassembly window, write out the assembly code of the C intrustionGPIO_PORTF_DATA_R |= 0x01. Explain in detail the mean of each assembly code. Why this intrustion
can write logic 1 to the output port
We set the first bit of Port F (PF0) OR with itself at the high logic value (1) .// Load the value of PC +48 hexadecimal into register R00x11c: 0x4812 LDR.N R0,[PC, #0x48]// Load the value at memory address defined by R0 (that is PC+48) back into R00x11e: 0x6800 LDR R0, [R0]// Or value in R0 with intermediate number 1 and write back to R00x120: 0xf050 0x0001 ORRS.W R0, R0, #1// Load the value of PC +40 hexadecimal into register R10x124: 0x4910 LDR.N R1, [PC, 0#0x40]// Store value in R0 into memory at address defined by R1 (that is PC +40)
0x126: 0x6008 STR R0, [R1]
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Experiment 2: Using button select (Pin 61 PF1/IDX1) to blink the LED (Pin 47
PF0/PWM0)
1. Create new project in IAR with name Lab1b and configure it as in Experiment 1.
2. Copy and modify the code in Experiment 1 as following steps:
a. Configure pin PF1 to Input mode
b. Configure pin PF0 to Output mode
c. The controlling rule is: if the select button is pressed, the LED will blink in frequency
1Hz. As illustrated in above figure, the pressed select button will generate the logic 0 and
the Led will blink.
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a. Define the design flow to write to a GPIO Port.Enable port by set the system control to the port by setting value for register SYSCTL_mode
After that, set the direction, digital enable by setting value for register GPIO DIR and DEN
Finally, write the data to the port by setting the value for register GPIO DATA
b. Define the design flow to read data from a GPIO PortEnable port by set the system control to the port by setting value for register SYSCTL_mode
Then, set the direction, digital enable by setting value for register GPIO DIR and DEN
Finally, read the data to the port by reading the value of register GPIO DATA
c. Why do we have to set the pull up register for PF1?We have to set the pull up register for PF1 (Port F1) because, as we can see from the above
figure, the select button we need, which is connected to PF1, is active low by default. It means
that if we press the select button, it is low. However, if we do not press, the state of select is x
(high impedance). Therefore, we have to set the pull up register for PF1, which is the code
GPIO_PORTF_PUR_R = 0x02; //set pull up register for PF1
d. If we dont know what is the current value of PORTF, write the C code to set pin 3 and pin 7of PORTF without influence to other pins in PORTF.GPIO_PORTF_DATA_R |= 0x88
or GPIO_PORTF_DATA_R = GPIO_PORTF_DATA_R | 0x88
e. If we dont know what is the current value of PORTF, write the C code to clear pin 2 and pin6 of PORTF without influence to other pin of PORTF.
GPIO_PORTF_DATA_R &=0xBB
or GPIO_PORTF_DATA_R = GPIO_PORTF_DATA_R & 0xBB
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Experiment 3: Traffic Lights. Connecting with real electric device
A freeway on-ramp has the traffic light control system to regular the flow of cars onto the freeway. There
are three lanes, each with its own red/green (stop/go) light. The middle Pool lane has higher priority then
2 other lanes if the car presents in this lane. Right lane has higher priority than Left lane if cars presents in
both two lanes. Yellow sensor has default value 0 if there is not car go to that lane and has value 1 when
there are car got to the lane.
Alls variable using in the project are:
Inputs:
- CarPool: 1 if there is a car present in the car pool lane.
- CarLeft: 1 if there is a car present in the car left lane.
- CarRight: 1 if there is a car present in the car right lane.
Outputs:
- LightPoolR: Turn on the light Red of Pool Line
- LightPoolG: Turn on the light Green of Pool Line
- LightLeftR: Turn on the light Red of Left Line
- LightLeftG: Turn on the light Green of Left Line
- LightRightR: Turn on the light Red of Right Line
- LightRightG: Turn on the light Green of Right Line
Setting up the project.
Car
Pool laneLeft lane Right lane
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Variable Device Pin
using
Direction Description
CarPool Upswitch
72-PE0
Input Active in Lowlevel.
CarLeft Left
switch
74-
PE2
Input Active in Low
level.
CarRight Right
switch
75-
PE3
Input Active in Low
level
LightPoolR External
Led
28-
PA2
Output Active in Low
level
LightPoolG External
Led
29-
PA3
Output Active in Low
level
LightLeftR External
Led
30-
PA4
Output Active in Low
level
LightLeftG External
Led
31-
PA5
Output Active in Low
level
LightRightR ExternalLed
26-PA0
Output Active in Lowlevel
LightRightG External
Led
27-
PA1
Output Active in Low
level
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C code for experiment 3:
The end.