ECE260B – CSE241A Winter 2005 Interconnects and Delay Calculation
description
Transcript of ECE260B – CSE241A Winter 2005 Interconnects and Delay Calculation
ECE 260B – CSE 241A Interconnects and Delay 1 http://vlsicad.ucsd.edu
ECE260B – CSE241A
Winter 2005
Interconnects andDelay Calculation
Website: http://vlsicad.ucsd.edu/courses/ece260b-w05
ECE 260B – CSE 241A Interconnects and Delay 2 http://vlsicad.ucsd.edu
Interconnect-Centric Methodology
Conventional component-centric design methodology Interconnect impacts are negligent components characterized by cell libraries
Modern interconnect-centric design methodology Interconnects dominate VLSI system performance Needs accurate interconnect prediction and analysis
Approaches Hierarchical “time-budgeting” Top-level “chip-integration”
•Slide courtesy of Sylvester/Shepard
ECE 260B – CSE 241A Interconnects and Delay 3 http://vlsicad.ucsd.edu
Wire
ViaGlobal (up to 5)
Intermediate (up to 4)
Local (2)
PassivationDielectricEtch Stop Layer
Dielectric Capping Layer
Copper Conductor with Barrier/Nucleation Layer
Pre Metal DielectricTungsten Contact Plug
SEMATECH Prototype BEOL stack, 2000
What are some implications of reverse-scaled global interconnects?
•Slide courtesy of Chris Case, BOC Edwards
ECE 260B – CSE 241A Interconnects and Delay 4 http://vlsicad.ucsd.edu
Damascene and Dual-Damascene Process Damascene process named after the ancient Middle Eastern
technique for inlaying metal in ceramic or wood for decoration
• Single Damascene • Dual Damascene
ILD Deposition
Oxide Trench Etch
Metal Fill
Metal CMP
Oxide Trench / Via Etch
Metal Fill
Metal CMP
ECE 260B – CSE 241A Interconnects and Delay 5 http://vlsicad.ucsd.edu
Cu Dual-Damascene Process
Bulk copper removal
Barrier removal
Oxide over-polish
Oxide erosion
Copper dishing
Cu Damascene Process
Polishing pad touches both up and down area after step height
Different polish rates on different materials
Dishing and erosion arise from different polish rates for copper and oxide
ECE 260B – CSE 241A Interconnects and Delay 6 http://vlsicad.ucsd.edu
Area Fill & Metal Slot for Copper CMP
Dishing can thin the wire or pad, causing higher-resistance wires or lower-reliability bond pads
Erosion can also result in a sub-planar dip on the wafer surface, causing short-circuits between adjacent wires on next layer
Oxide erosion and copper dishing can be controlled by area filling and metal slotting
Oxide
Copper
Metal SlotArea Fill
ECE 260B – CSE 241A Interconnects and Delay 7 http://vlsicad.ucsd.edu
Resistance & Sheet Resistance
W
LT
R = T W
L
Sheet ResistanceR
R1 R2
Resistance seen by current going from left to right is same in each block
ECE 260B – CSE 241A Interconnects and Delay 8 http://vlsicad.ucsd.edu
Bulk Resistivity
• Aluminum dominant until ~2000
• Copper has taken over in past 4-5 years
• Copper as good as it gets
ECE 260B – CSE 241A Interconnects and Delay 9 http://vlsicad.ucsd.edu
Capacitance: Parallel Plate Model
SiO2
Substrate
L
W
T
HILD
ILD = interlevel dielectric
Bottom plate of cap can be another metal layer
Cint = eox * (W*L / tox)
ECE 260B – CSE 241A Interconnects and Delay 10 http://vlsicad.ucsd.edu
Line Dimensions and Fringing Capacitance
w S
Line dimensions: W, S, T, H
Sometimes H is called T in the literature, which can be confusing
Lateral cap
ECE 260B – CSE 241A Interconnects and Delay 11 http://vlsicad.ucsd.edu
Inductance
V = L d I/d t V2 = M12 d I1/d t
Faraday’s law
V = N d (B A) / d t
B = (N / l) IL = N2 A / l
V = voltageN = number of turns of the coilB = magnetic fluxA = area of magnetic field circled by the coill = height of the coilt = time
At high frequencies, can be significant portion of total impedance Z = R + jL ( = 2f = angular freq)
Slide courtesy of Ken Yang, UCLA
ECE 260B – CSE 241A Interconnects and Delay 12 http://vlsicad.ucsd.edu
Inductance is Important… e.g.
Faster clock speeds
Frequency of interest is determined by signal rise time, not clock frequency
Copper interconnects R is reduced
Thick, low-resistance (reverse-scaled) global lines
Chips are getting larger long lines large current loops
RL
Massoud/Sylvester/Kawa, Synopsys
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
1S2S
I
ECE 260B – CSE 241A Interconnects and Delay 13 http://vlsicad.ucsd.edu
On-Chip Inductance
Inductance is a loop quantity
Knowledge of return path is required, but hard to determine
For example, the return path depends on the frequency
Signal Line
Return Path
Massoud/Sylvester/Kawa, Synopsys
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
ECE 260B – CSE 241A Interconnects and Delay 14 http://vlsicad.ucsd.edu
Frequency-Dependent Return Path
At low frequency, and current tries to minimize impedance minimize resistance use as many returns as possible (parallel resistances)
At high frequency, and current tries to minimize impedance minimize inductance use smallest possible loop (closest return path) L dominates, current returns
“collapse” Power and ground lines always available as low-impedance current returns
Signal Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
)( LjR
)( LR
)( LR )( LjR
Signal Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys
ECE 260B – CSE 241A Interconnects and Delay 15 http://vlsicad.ucsd.edu
Inductance vs. Capacitance
Capacitance Locality problem is easy: electric field lines “suck up” to nearest
neighbor conductors Local calculation is hard: all the effort is in “accuracy”
Inductance Locality problem is hard: magnetic field lines are not local; current
returns can be complex Local calculation is easy: no strong geometry dependence; analytic
formulae work very well
Intuitions for design Seesaw effect between inductance and capacitance Minimize variations in L and C rather than absolutes
- E.g., would techniques used to minimize variation in capacitive coupling also benefit inductive coupling?
•Slide courtesy of Sylvester/Shepard
ECE 260B – CSE 241A Interconnects and Delay 16 http://vlsicad.ucsd.edu
Interconnect Modeling Lumped load capacitance
Distributed R(L)C(K) network Model for each uniform wire segment
Transmission line
Microwave domain
Distributed using multiple lumps of model of a single wire
Vin Vout
ECE 260B – CSE 241A Interconnects and Delay 17 http://vlsicad.ucsd.edu
Characterization Signal
Propagation delay
Transition time (slew rate)
Interconnect transfer function H(s) in Laplace domain
V s H s V s
V t h t V d
ou t in
ou t in
t
( ) ( ) ( )
( ) ( ) ( )
0
Distributed using multiple lumps of model of a single wire
Vin Vout
80%50%20%
Delay
Transition
ECE 260B – CSE 241A Interconnects and Delay 18 http://vlsicad.ucsd.edu
Transition Degradation
Step response of a distributed RC wire as function of location along wire and time
Transition degradation leads to increased downstream (gate and interconnect) delays
Courtesy Prof. A. B. Kahng
ECE 260B – CSE 241A Interconnects and Delay 19 http://vlsicad.ucsd.edu
Elmore Delay = First Moment of Transfer Function H(t) = step input response
h(t) = impulse response = dH(t)/dt = transfer function in time domain
T50% = median of h(t)
TED = mean of h(t)
TED = first moment of h(t)
H T h t d tT
( ) ( ) . 00 5
T t h t d tE D
( )0
H s e h t d t m m s m s
mi
t h t d t
st
i
ii
( ) ( ) . . .
( )!
( )
0 0 1 22
0
1
ECE 260B – CSE 241A Interconnects and Delay 20 http://vlsicad.ucsd.edu
Elmore Delay = Simple Delay Metric
h(t)
ttelm
Upper bound 50% delay for RC trees
TED = T50% if symmetric h(t)
TED > T50% for monotonic waveforms
TED T50% with increased transition time
TED = T50% / ln2 for an RC load driven by a step input
+/- 15% error for RC interconnects with a ratio
Simple (linear time) computation
Incremental
facilitate ECO (Engineering Chang Order)
R
C
ECE 260B – CSE 241A Interconnects and Delay 21 http://vlsicad.ucsd.edu
Elmore Delay Computation in an RC Tree
Courtesy Prof. A. B. Kahng
ECE 260B – CSE 241A Interconnects and Delay 23 http://vlsicad.ucsd.edu
Asymptotic Waveform Evaluation (AWE), etc. Moment matching poles and residues time domain
Distributed using multiple lumps of model of a single wire
Vin Vout
H s m sk
s p
h t k e
V t k e V t d
ii
i
j
jj
jp t
j
ou t jp
jin
t
j
j
( )
( )
( ) ( )
0
ECE 260B – CSE 241A Interconnects and Delay 24 http://vlsicad.ucsd.edu
0 00
0 00 0
0 00 0
00 0
0 10
01 0
00 0
0001
0 0 1
1
2
1
2
3
1 1
1 1 2 2
2 2
1
2
3
3
cc
vvvi
g gg g g g
g g
vvvi
u
vi
ou t ou t
N
ou t
00 0 0 1
1
2
3
vvvi out
Interconnect Model Order Reduction
C x G x B u
i L xn n N
NT
n
Direct matrix solver (AWE): numerical instability
Pade via Lancoz (PVL)
Block Arnoldi (PRIMA)
or
v1 v2 v3
c1 c2
g1 g2IoutuN
ECE 260B – CSE 241A Interconnects and Delay 25 http://vlsicad.ucsd.edu
Capacitive Coupling (Crosstalk)
Two coupled lines
Cross-section view
Interwire capacitance allows neighboring wires to interact
Charge injected across Cc results in temporary (in static logic) glitch in voltage from the supply rail at the victim
ECE 260B – CSE 241A Interconnects and Delay 26 http://vlsicad.ucsd.edu
Crosstalk Noise
Glitches caused by capacitive coupling between wires An “aggressor” wire switches A “victim” wire is charged or discharged by the coupling capacitance (cf.
charge-sharing analysis)
An otherwise quiet victim may look like it has temporarily switched
This is bad if: The victim is a clock or asynchronous reset The victim is a signal whose value is being latched at that moment What are some fixes?
Aggressor
Victim
•Slide courtesy of Paul Rodman, ReShape
ECE 260B – CSE 241A Interconnects and Delay 27 http://vlsicad.ucsd.edu
Crosstalk Delay Variation: Timing Pull-In
A switching victim is aided (sped up) by coupled charge
This is bad if your path now violates hold time
Fixes include adding delay elements to your path
Aggressor
Victim
•Slide courtesy of Paul Rodman, ReShape
ECE 260B – CSE 241A Interconnects and Delay 28 http://vlsicad.ucsd.edu
Crosstalk Delay Variation: Timing Push-Out
A switching victim is hindered (slowed down) by coupled charge
This is bad if your path now violates setup time
Fixes include spacing the wires, using strong drivers, …
Aggressor
Victim
•Slide courtesy of Paul Rodman, ReShape
ECE 260B – CSE 241A Interconnects and Delay 29 http://vlsicad.ucsd.edu
Delay Uncertainty
Relatively greater coupling noise due to line dimension scaling
Tighter timing budgets to achieve fast circuit speed (“all paths critical”)
Delay
Noise
Aggressor Victim
Delay Uncertainty
0.35 0.30 0.25 0.20 0.15 0.1025303540455055606570758085
Td /
Td (
%)
Technology Generation (μm)
Nominal DelayDelay Uncertainty
•Slide courtesy of Kevin Cao, Berkeley
ECE 260B – CSE 241A Interconnects and Delay 30 http://vlsicad.ucsd.edu
Crosstalk Delay Calculation: Levels of Accuracy Discard coupling capacitances
De-coupling by replacing coupling caps by double ground caps
De-coupling by Miller factors
Simulating multi-input multi-output (MIMO) networks
Input 1
Input 2
Output 1
Output 2
ECE 260B – CSE 241A Interconnects and Delay 31 http://vlsicad.ucsd.edu
Miller Factor
Q = Ccv Vv = Cc (Vv – VA)
Ccv = (Vv – VA) / Vv * Cc
Miller factor roughly between 0 and 2
Or between –1 and 3 (for 50% delay calculation)?
Courtesy Prof. A. B. Kahng
ECE 260B – CSE 241A Interconnects and Delay 32 http://vlsicad.ucsd.edu
Multi-Input Multi-Output Model RLC interconnect is linear
Superposition Each of the drivers is simulated in turn Other Thevenin voltage sources are shorted
AWE/PRIMA model order reduction techniques
Input 1
Input 2
Output 1
Output 2
ECE 260B – CSE 241A Interconnects and Delay 33 http://vlsicad.ucsd.edu
Worst Case Aggressor Scenario Stimuli vector
For RC interconnects- Aggressors take opposite transition
max delay- Aggressors take identical transition
min delay For RLC interconnects
- ?
Aggressor alignment For (linear) interconnects
- Aggressors are aligned with each other to make max crosstalk noise peak
- Align the noise peak to make max delay variation
For worst case gate delay- ?
Aggressor 1
Aggressor 2
Noise
delay
alignment
ECE 260B – CSE 241A Interconnects and Delay 34 http://vlsicad.ucsd.edu
Calculation Flow
Timing window overlaps enable crosstalk delay variation
Chicken-egg dilemma: delay vs. crosstalk
Aggressor
Victim
delay
overlap
Iteration Starting with the assumption that all
timing windows are overlapped (pessimistic about the unknowns)
Refine calculation by reducing pessimism
refinement
Timing window assumptions Crosstalk delay
calculation
ECE 260B – CSE 241A Interconnects and Delay 35 http://vlsicad.ucsd.edu
Gate Timing Characterization
“Extract” exact transistor characteristics from layout Transistor width, length, junction area and perimeter Local wire length and inter-wire distance
Device modeling and simulation by BSIM or SPICE (differential-equations solver)
CL DA
B
F
CL
Courtesy Prof. A. B. Kahng
ECE 260B – CSE 241A Interconnects and Delay 36 http://vlsicad.ucsd.edu
Static Timing Analysis Conservatism (Worst case scenario)
True gate delay depends on input arrival time patterns STA will assume that only 1 input is switching Will use worst slope among several inputs
For a number of different input slews and load capacitances simulate the circuit of the cell
Propagation time (e.g., 50% Vdd at input to 50% at output) Output slew (e.g., 20% Vdd at output to 80% Vdd at output)
Time
tslew
tpd
Vdd
Courtesy Prof. A. B. Kahng
ECE 260B – CSE 241A Interconnects and Delay 37 http://vlsicad.ucsd.edu
DG = f (CL, Sin) and Sout = f (CL, Sin) Non-linear Interpolate between table entries Polynomial representation vs. lookup tables
Look-Up Table
Input Slew
Input Slew
Delay of the gate
LoadCapacitance
LoadCapacitance
Output Slew
GateDelay
Resulting waveform
ECE 260B – CSE 241A Interconnects and Delay 38 http://vlsicad.ucsd.edu
Delay Calculation
Cap\Tr 0.05 0.2 0.5
0.01 0.02 0.16 0.30
0.5 0.04 0.32 0.60
2.0 0.08 0.64 1.20
Cap\Tr 0.05 0.2 0.5
0.01 0.03 0.18 0.33
0.5 0.06 0.36 0.66
2.0 0.09 0.72 1.32
Cell Fall
Cell Rise
1.0pf
0.1ns
0.12ns
Fall delay = 0.178nsRise delay = 0.261nsFall transition = 0.147nsRise transition = …
0.178
0.261
Cap\Tr 0.05 0.2 0.5
0.01 0.01 0.09 0.15
0.5 0.03 0.27 0.45
2.0 0.06 0.54 0.90
Fall Transition
0.147
0.147ns
Courtesy Prof. A. B. Kahng
ECE 260B – CSE 241A Interconnects and Delay 39 http://vlsicad.ucsd.edu
Effective Capacitance
Resistive shielding effect
effective capacitance < total load capacitance
Distributed using multiple lumps of model of a single wire
Vin Vout
C I dteff ou t
T r 0
Iout
tTr
C I dtto ta l ou t
0
Ceff gate delay
ECE 260B – CSE 241A Interconnects and Delay 40 http://vlsicad.ucsd.edu
Timing Library Example (.lib)library(my_lib) {
delay_model : table_lookup;
library_features (report_delay_calculation);
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1mA";
leakage_power_unit : 1uW;
capacitive_load_unit(1,pf);
pulling_resistance_unit : "1kohm";
nom_voltage : 1.08;
nom_temperature : 125.0;
nom_process : 1.0;
slew_derate_from_library : 0.500000;
default_operating_conditions : slow_125_1.08 ;
lu_table_template("load") {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1( "1, 2, 3, 4" );
index_2( "1, 2, 3, 4" );
}
cell("INV") {
pin(Z) {
direction : output;
function : "!A";
max_transition : 1.500000;
max_capacitance : 5.1139;
timing() {
related_pin : "A";
cell_rise(load) {
index_1( "0.0375, 0.2329, 0.6904, 1.5008" );
index_2( "0.0010, 0.9788, 2.2820, 5.1139" );
values ( \
"0.013211, 0.071051, 0.297500, 0.642340", \
"0.028657, 0.110849, 0.362620, 0.707070", \
"0.053289, 0.165930, 0.496550, 0.860400", \
"0.091041, 0.234440, 0.661840, 1.091700" );
}
ECE 260B – CSE 241A Interconnects and Delay 41 http://vlsicad.ucsd.edu
PVT (Process, Voltage, Temperature) Derating
Actual cell delay = Original delay x KPVT
Courtesy Prof. A. B. Kahng
ECE 260B – CSE 241A Interconnects and Delay 42 http://vlsicad.ucsd.edu
PVT Derating: Example + Min/Typ/Max Triples
Proc_var (0.5:1.0:1.3)Voltage (5.5:5.0:4.5)Temperature (0:20:50)KP = 0.80 : 1.00 : 1.30KV = 0.93 : 1.00 : 1.08KT = 0.80 : 1.07 : 1.35
KPVT = 0.60 : 1.07 : 1.90Cell delay = 0.261nsDerated delay = 0.157 : 0.279 : 0.496 {min : typical : max}
Courtesy Prof. A. B. Kahng