ECE 561 - Lecture 4 - State Machine Design
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Transcript of ECE 561 - Lecture 4 - State Machine Design
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7/21/2019 ECE 561 - Lecture 4 - State Machine Design
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Lecture 4 State Machine
Design
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State Machine Design
State Machine types an s!"e #asics
State Machine Design $r!cess
State Machine Design E%a"p&es State Machine Design in the 'DL
(!r&
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)ypes !* state "achines
Mea&y Machine
Characteri+e #y ,utputs are a*uncti!n !* #!th inputs an current state
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State Machine )ypes
M!!re "achine
Characteri+e #y ,utputs are a*uncti!n current state !n&y
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Mea&y an M!!re."p&e"entai!ns
!th Mea&y an M!!re "achinei"p&e"entati!n can #e i"p&e"ente(ith any seuentia& e&e"ent
hy ch!!se !ne e&e"ents !3er an!ther Eciency )he ne%t state &!gic "ay ier
signi7cant&y (hen using ierent / types
Eciency !* i"p&e"entati!n is a&s!rastica&&y aecte #y ch!ice !* stateassign"ent
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Characteristic Euati!ns
)he Characteristic Equation *!r"a&&yspeci7es the ip-!p:s ne%t state asa *uncti!n !* its current state an
inputs
;< "eans the ne%t state 3a&ue *!rthe ; !utput !* the /
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Characteristic Euati!ns
S-= Latch
D Latch
D /
D / (ith Ena#&e
>-? /
) /
;< @ S A =: ;
;< @ D
;< @ D
;< @ EB D A EB: ;
;< @ > ;: A ?: ;
;< @ ;:
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Designing a Synchr!n!usSyste"
Steps *!r esigning a c&!cesynchr!n!us state "achine starting*r!" a (!r escripti!n !r speci7cati!n
irst unerstan the escripti!n !rspeci7cati!n an res!&3e any uesti!ns
Step 1 C!nstruct a state/!utput ta#&ec!rresp!ning t! the escripti!n/specF,r create a state iagra"G
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E%a"p&e
Descripti!n
Design a c&!ce synchr!n!us state"achine (ith t(! inputs H an I an a
sing&e !utput J that is 1 i* H ha the sa"e 3a&ue at each !* the t(!
pre3i!us c&!cs
Or
has #een 1 since the &ast ti"e that the 7rstc!niti!n (as true
,ther(ise the !utput is 0
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E3!&uti!n !* a state ta#&e
igures -46 an -4 !* te%t
Set up ta#&e ha3ing c!&u"ns *!r there&e3ant in*! Hs (e ha3e 2 inputs nee
the 4 ch!ices *!r inputs
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irst input
hat happens (hen 7rst inputarri3es
H0 ha3e !ne 0 !n H
H1 ha3e !ne 1 !n H
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Sec!n .nput
B!( (hat happens (hen in state H0May ha3e a 3a&ue !* 0 !r 1 !n the
ne%t H input Be( state ,?
,? says ha3e 2 !* the sa"e !n H
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Sec!n input Fc!ntG
B!( i* y!u are in state H1 (hathappens at ne%t input
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)he ne%t input
B!( res!&3e state ,?
May ha3e t! sp&it state ,?
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Be%t input F1G
=e7ne state ,? t! inicate i* H is 0s!r 1s
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=e7ne state ,?
)(! 0s !n the H input
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=e7ne state ,? F2G
i&& in state ,?1
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Be%t step
Step 2 - Mini"i+e the nu"#er !*states ca&&e state minimization
)his step (as a "aK!r part !* state
"achine esign
ith current 'DL synthesis t!!&s n! s!"uch s! t!ay
Step Ch!!se a set !* state3aria#&es an assign state-3aria#&ec!"#inati!ns t! na"e states
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)he 7na& steps
Step 5 ch!!se a / type t!aya&"!st a&(ays a D type /
Step 6 C!nstruct an e%citati!n ta#&e
Step Deri3e e%citati!n euati!ns*r!" the ta#&e
Step 8 Deri3e !utput euati!ns*r!" the ta#&e
Step 9 Dra( a &!gic iagra"
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E%a"p&e !* 7nishing esign
State an !utput ta#&e t! #ei"p&e"ente
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."p&e"ent (ith D /
Hssign c!ing t! state
hy are / use
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De3e&!p e%citati!neuati!ns
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H n!te !n "aps
)hese are 5 3aria#&e "aps
Each is a *uncti!n !* 5 3aria#&es inputHI input I an the / !utputs
;1I;2I;
En up (ith
D1 @ ;1 A ;2: ;
D2 @ ;1 ;: H A ;1 ; H A ;1 ;2 D @ ;1 H A ;2: ;: H
J @ ;1 ;2 ;: A ;1 ;2 ; @ ;1 ;2
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Hssign"ent
$r!# 46 *r!" te%t Dueenesay ,ct 8
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