Model-1Model-2 East : West : E1 E2 E3 W3 W2 W1 - Click on the villa type for Floor Plan details W4.
ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review...
-
date post
21-Dec-2015 -
Category
Documents
-
view
224 -
download
0
Transcript of ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review...
![Page 1: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/1.jpg)
ECE 511: Digital System & Microprocessor
![Page 2: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/2.jpg)
Course Outline
Week Subject
W1-W2 Digital Logic Review
W2-W3 Microprocessor Architecture & Overview
W3-W6 Microprocessor Instruction Set & Programming
W6-W9 Memory Interfacing
W10-W14 Parallel I/O Interfacing
![Page 3: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/3.jpg)
References
J. L. Antonakos, “The 68000 Microprocessor: Hardware and Software Principles & Applications,” 5th Ed., Pearson Prentice-Hall, 2004.
C. M. Gilmore, “Microprocessors: Principles & Applications,” 2nd Ed., McGraw-Hill, 1995.
A. Clements, “Microprocessor System Design,” PWS-Kent, 1992.
J. Palmer & D. Perlman, “Introduction to Digital Systems,” Schaum’s Outlines Series, McGraw-Hill, 1993.
![Page 4: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/4.jpg)
Course Evaluation
Tests x 2 30% Quizzes x 3 20% Mini Projects 50%
![Page 5: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/5.jpg)
If you have problems, please contact me:
Ahmad Ihsan bin Mohd Yassin
Rm. T2-A13-1A, Dept. of Comp. Eng.
Faculty of Elect. Eng.
UiTM, Shah Alam.
03-55436118, 017-2576295
*Please call before you see me.
![Page 6: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/6.jpg)
Digital Logic Review: Part I
ECE 511: Digital System & Microprocessor.
![Page 7: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/7.jpg)
What we will learn in this session:
Review of logic gates. Flip-flops. Universal representation of logic gates. Decoders.
![Page 8: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/8.jpg)
Gates
![Page 9: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/9.jpg)
What are gates? Gates are:
Simple electronic devices. Constructed using transistors. Used to design digital systems.
Three basic gates: AND OR NOT
Usually packed into ICs.
![Page 10: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/10.jpg)
Gates as Building Blocks
![Page 11: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/11.jpg)
Basic Gate - AND
The AND gate is similar to multiply operation.
AAND
BC
A B C
0
1
0
1
0
0
1
1
0
0
0
1
TRUTH TABLE
CBA CBA
![Page 12: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/12.jpg)
Basic Gate - OR
The OR gate is similar to add operation.
ORA
BC
CBA CBA
A B C
0
1
0
1
0
0
1
1
0
1
1
1
TRUTH TABLE
![Page 13: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/13.jpg)
Basic Gate - NOT
The NOT gate performs the inverse operation.
NOTA B
BA BA
TRUTH TABLE
A B
0
1
1
0
![Page 14: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/14.jpg)
Extended Gates
Combination of basic gates to perform complex functions:NANDNORXOR XNORFlip-Flops
![Page 15: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/15.jpg)
NAND Gate
Adds NOT after AND gate. AND outputs are inverted NAND (NOT-AND).
AAND
BCNOT
ANAND
BC
CBA
A B C
0
1
0
1
0
0
1
1
1
1
1
0
TRUTH TABLE
![Page 16: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/16.jpg)
NOR Gate
Adds NOT after OR gate. OR outputs are inverted NOR (NOT-OR).
ORA
BCNOT CNOR
A
B
CBA A B C
0
1
0
1
0
0
1
1
1
0
0
0
TRUTH TABLE
![Page 17: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/17.jpg)
XOR Gate XOR performs the Exclusive Or operation. When A=B, C=0; when A≠B, C=1.
)
A B C
0
1
0
1
0
0
1
1
0
1
1
0
TRUTH TABLE
CBA CBABA
XOR
A
B ) C
![Page 18: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/18.jpg)
XNOR Gate Adds NOT after XOR gate. XOR outputs inverted XNOR (NOT XOR).
)
A B C
0
1
0
1
0
0
1
1
1
0
0
1
TRUTH TABLE
CBABA
XOR
A
B ) CNOT XOR
A
B ) C
![Page 19: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/19.jpg)
Flip-Flops
![Page 20: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/20.jpg)
Flip-Flops
Extended gate. 2 gates, feedback connections. 2 inputs, 4 states. Used as memory:
Each FF stores 1 bit. Unchanged at “keep” state.
More complex ones may: Use timing from CLK. Perform bit toggle.
![Page 21: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/21.jpg)
RS Flip-Flop
4 states: Three stable. One not stable.
2 inputs, 2 outputs. May contain clock (CLK) signal.
![Page 22: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/22.jpg)
RSFF - NOR Implementation
*Assuming initial condition:S = 0, R = 0, Q = 0
Qprev S R Q
N/A 0 0 0
0 1 0 1
1 0 1 0
Doesn’tmatter 1 1 N/AUnstable
Output unchanged
Output set (Q = 1)
Output reset (Q = 0)
Q’
1
0
1
N/A
*As long as S=0 and R=0, Q will always remain at previous state.
S
R
Q’
Q
![Page 23: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/23.jpg)
RS Flip-Flop (NAND Implementation)
*Assuming initial condition:S = 0, R = 0, Q = 0
Qprev S R Q
N/A 0 0 0
0 1 0 1
1 0 1 0
Doesn’tmatter 1 1 N/AUnstable
Output unchanged
Output set (Q = 1)
Output reset (Q = 0)
Q’
1
0
1
N/A
*As long as S=0 and R=0, Q will always remain at Qprev.
S
R
Q
Q’
![Page 24: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/24.jpg)
Clocked RS S
R
Q’
Q
CLK
Qprev S R Q
N/A 0 0 0
0 1 0 1
1 0 1 0
Doesn’tmatter 1 1 N/AUnstable
Output unchanged
Output set (Q = 1)
Output reset (Q = 0)
Q’
1
0
1
N/A
CLK
↑
↑
↑
Doesn’tmatter
Only active when CLKis ↑
Reduced sensitivity to noise.
![Page 25: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/25.jpg)
JK Flip-Flop
Same as RS, but forbidden state used to toggle bit.
Can also be clocked using CLK.
Qprev S R Q
N/A 0 0 0
0 1 0 1
1 0 1 0
Q 1 1 QToggle
Output unchanged
Output set (Q = 1)
Output reset (Q = 0)
Q’
1
0
1
Q
![Page 26: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/26.jpg)
JK Flip-Flop (Palmer & Perlman, pg. 200)
Qprev S R Q
N/A 0 0 0
0 1 0 1
1 0 1 0
Q 1 1 QToggle
Output unchanged
Output set (Q = 1)
Output reset (Q = 0)
Q’
1
0
1
Q
J
K
Q
Q
![Page 27: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/27.jpg)
Clocked JK (Palmer & Perlman, pg. 200)
Qprev S R Q
N/A 0 0 0
0 1 0 1
1 0 1 0
Q 1 1 QToggle
Output unchanged
Output set (Q = 1)
Output reset (Q = 0)
CLK
↑
↑
↑
↑
CLK
J
K
Q
Q
![Page 28: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/28.jpg)
D-Flip-Flop
Data latch. Modification of RSFF. Stores 1-bit of information.
Can be combined to store more. How data stored in memory.
![Page 29: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/29.jpg)
D-Flip-Flop D
Q’
Q
EN
Qprev D Q
Doesn’t Matter 1 1
Doesn’t Matter 0 0
Output set (Q = 1)
Output reset (Q = 0)
Q’
0
1
EN
1
1
Only active when ENis 1
![Page 30: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/30.jpg)
D-Flip-Flop: Timing Diagram
D
EN
Q
![Page 31: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/31.jpg)
Storing 8-bits using DFF
DFF DFFDFF DFFDFF DFF DFF DFF
Q3 Q5 Q6 Q7Q1 Q2 Q4Q0
EN
D3 D5 D6 D7D1 D2 D4D0
![Page 32: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/32.jpg)
Asynchronous Latch
Allows both synchronous & asynchronous operations:Synchronous: CLK driven (Clocked JK).Asynchronous: similar to RSFF.
5 inputs, 2 outputs:J, K and CLK for synch. operation.PR, CLR for asynch. operation.
![Page 33: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/33.jpg)
Asynchronous Latch (Perlman, pg. 201)
CLK
J
K
Q
Q
CLR
PREPRE CLR Q
1 1 Follows J, K, CLK (Synch. JK)1 0 Q = 0, resets output.0 1 Q = 1, sets output.0 0 Not valid.
PRE CLR Q0 0 Follows J, K, CLK (Synch. JK)0 1 Q = 0, resets output.1 0 Q = 1, sets output.1 1 Not valid.
CLK
J
K
Q
Q
CLR
PRE
![Page 34: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/34.jpg)
Universal Gates – NAND and NOR
![Page 35: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/35.jpg)
NAND and NOR as Universal Gates In industry, NAND and NOR gates are
most common. Reason?
Can be used to represent any gate (functionally complete).
Easiest & cheapest to produce.
![Page 36: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/36.jpg)
NAND Logic
NOT
NAND
AND NAND NAND
![Page 37: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/37.jpg)
NOR Logic
NOT
NOR
AND
NOR
NOR
NOR
![Page 38: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/38.jpg)
NAND Logic
OR
NAND
NAND
NAND
XOR
NAND
NAND
NANDNAND
![Page 39: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/39.jpg)
NOR Logic
NOR NOROR
NOR
NOR
NOR
NOR
NOR
XOR
![Page 40: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/40.jpg)
IC 4011 IC 7402
![Page 41: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/41.jpg)
Decoders
![Page 42: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/42.jpg)
Decoders
Electronic device that:Reverse of an encoder.“Translates” binary codes back into signal.Converts n inputs into 2n combinations.
Uses:Activate devices for use by µP.Memory, I/O interfacing.
![Page 43: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/43.jpg)
Encoder vs. Decoder8 3 Encoder
I0
I7
I6
I5
I4
I3
I2
I1
I4 I5 I6 I7 Y0 Y1 Y2I0 I1 I2 I3
00
1 10
00000
01
11
11
11
1
00000
0000
000
00 0
00000
0
0
00000
000000
000000
0000
000
0 0 0010 000 110 1
1 0 0110
11 1
0
Y2
Y0
Y1
![Page 44: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/44.jpg)
Encoder vs. Decoder3 8 Decoder
I0
I7
I6
I5
I4
I3
I2
I1
Y2
Y0
Y1
Y2 Y1 Y0
1 1
0 0010 000 110 1
1 0 0110
11 1
0
I4I5I6I7 I0I1I2I3
00
0
00000
01
11
11
11
1
00000
0000
000
000
00000
0
0
00000
000000
0 00000
0000
000
0
![Page 45: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/45.jpg)
What Goes on Inside a Decoder?Y0
Y1
Y2
I0 = Y0Y1Y2
I2 = Y0Y1Y2
I3 = Y0Y1Y2
I4 = Y0Y1Y2
I5 = Y0Y1Y2
I6 = Y0Y1Y2
I7 = Y0Y1Y2
I1 = Y0Y1Y2
![Page 46: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/46.jpg)
Decoders in Action
Decoder
Device Code
Code Device000 LED001 DC Motor010 Memory #1
110 LCD Display
011 Memory #2100 Memory #3101 Memory #4
Act
ivat
e S
igna
l
![Page 47: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/47.jpg)
74LS139 Dual 2-4 Line Decoder
Motorola 2-4 decoder. 2 x decoders in one IC. 16 pins total:
2 inputs, 4 outputs (active low).Vcc (±5V) and GND.2 x Enable pins.
![Page 48: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/48.jpg)
74LS139 Dual 2-4 Line Decoder
Ea
A0a
A1a
O0a
O1a
O2a
O3a
Eb
A0b
A1b
O0b
O1b
O2b
O3b
![Page 49: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/49.jpg)
74LS139 Truth Table
E I0I1 O3 O0O1O2
1 XX 1 111
0 00 1 011
0 10 1 101
0 01 1 110
0 11 0 111
![Page 50: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/50.jpg)
74LS138 3-8 Line Decoder
Motorola 3-8 decoder. 1 x decoder in one IC. 16 pins total:
3 inputs, 8 outputs (active low).Vcc (±5V) and GND.3 x Enable pins.
![Page 51: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/51.jpg)
74LS138 3-8 Line Decoder
E1
A0
A1
O0
O1
O2
O3
O4
O5
O6
O7
E2
E3
A2
![Page 52: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/52.jpg)
E1 I0I1 O3 O0O1O2
1 XX 1 111
X XX 1 111
X XX 1 111
0 00 1 011
0 10 1 101
E2
X
1
X
0
0
E3
X
X
0
1
1
I2
X
X
X
0
0
O7 O4O5O6
1 111
1 111
1 111
1 111
1 111
0 01 1 1100 1 0 1 111
0 11 0 1110 1 0 1 111
0 00 1 111
0 10 1 111
0
0
1
1
1
1
1 011
1 101
0 01 1 1110 1 1 1 110
0 11 1 1110 1 1 0 11174LS
138
Tru
th T
able
![Page 53: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/53.jpg)
Conclusion
Gates: most basic elements in circuits.Can be extended to perform advanced
functions.Some types are universal.Flip-flops can store data – feedback.
Decoders transform code into original signals.Can be used to control access to hardware.
![Page 54: ECE 511: Digital System & Microprocessor. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor.](https://reader036.fdocuments.us/reader036/viewer/2022081508/56649d575503460f94a359ed/html5/thumbnails/54.jpg)
The End
Please read:Palmer & Perlman, pg.194-203.http://computerscience.jbpub.com/ecoa/2e/Null03.pdf