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ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.
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Transcript of ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.
![Page 1: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/1.jpg)
ECE 477 Design Review ECE 477 Design Review Team 4 Team 4 Spring 2008 Spring 2008
Zach Dicklin
AmyRitter
Ian Bacon
Eric Yee
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OutlineOutline• Project overview Project overview • Project-specific success criteriaProject-specific success criteria• Block diagramBlock diagram• Component selection rationaleComponent selection rationale• Packaging designPackaging design• Schematic and theory of operationSchematic and theory of operation• PCB layoutPCB layout• Software design/development statusSoftware design/development status• Project completion timelineProject completion timeline• Questions / discussionQuestions / discussion
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Project OverviewProject OverviewDigiJock
shoppers also like to shop at…
AD
Targeting ads… Reaching demographics…The future of advertising!
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Project-Specific Success CriteriaProject-Specific Success Criteria
RFID
DigiJocks
• Decode a valid shopper RFID tag.Decode a valid shopper RFID tag.
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Project-Specific Success CriteriaProject-Specific Success Criteria• Retrieve shopper’s characteristics from a Retrieve shopper’s characteristics from a
database indexed by decoded ID.database indexed by decoded ID.
RFID
DigiJocks
What does this DigiJock like?
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Project-Specific Success CriteriaProject-Specific Success Criteria• Load “general” and targeted advertisements Load “general” and targeted advertisements
from a database.from a database.
RFID
DigiJocks
Where is this ad?
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Project-Specific Success CriteriaProject-Specific Success Criteria• Display targeted advertisement images on a Display targeted advertisement images on a
local LCD in response to current shopper’s ID.local LCD in response to current shopper’s ID.
RFID
DigiJocks
AD
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Project-Specific Success CriteriaProject-Specific Success Criteria• Display “general” advertisement images on a Display “general” advertisement images on a
local LCD when valid RFID tag is not detected.local LCD when valid RFID tag is not detected.
RFID
DigiJocks
HI
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Block DiagramBlock Diagram
Microcontroller(MC9S12NE64)
LevelShifter
(Max3322)
LCDController
(SLCD)
RFID Reader
(TRRO1OEM)
RFID tags
2
CLOCK1
PushButton
SD CardReader
(BOB-00204)
RJ-45
4
24
7 2
1
Voltage Regulator
3.3V
Microcontroller(MC9S12NE64)
LevelShifter
(Max3322)
LCDController
(SLCD)
RFID Reader
(TRRO1OEM)
RFID tags
2
CLOCK1
PushButton
SD CardReader
(BOB-00204)
RJ-45
4
24
7 2
1
Voltage Regulator
3.3V
SCI
SCI
SPI
Ethernet
SCI
SCI
SPI
Ethernet
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Component Selection RationaleComponent Selection Rationale
• Agatha’s Major ComponentsAgatha’s Major Components– MicrocontrollerMicrocontroller
MC9S12NE64
Freescale
FREE + DevKit
On board
2 Channels
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Component Selection RationaleComponent Selection Rationale
• Agatha’s Major ComponentsAgatha’s Major Components– RFID ReaderRFID Reader
TRR01OEM
Up to 28.25 inches*
6 x 6 x 1.5 cm
YES
YES
YES (round / 18” diameter)
$78.00
*tag dependent**includes license fee
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• Agatha’s Major ComponentsAgatha’s Major Components– Display driverDisplay driver
$429
Component Selection RationaleComponent Selection Rationale
*includes external RAM
SLCD
SCI
$240 (discounted)
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Packaging DesignPackaging Design
• Outer KioskOuter Kiosk– 5.7” LCD Display5.7” LCD Display– 5’ for eye-level viewing5’ for eye-level viewing– Wood constructionWood construction– WeightedWeighted
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Packaging DesignPackaging Design
• Inner KioskInner Kiosk– Circuitry on floorCircuitry on floor– Power/EthernetPower/Ethernet– LCD ScreenLCD Screen– RS-232 runs 15’RS-232 runs 15’
to RFID readerto RFID reader
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Packaging DesignPackaging Design12
0
12
Microprocessor(HC9S12NE64)
31
3.8
2424
Serial Port
15.9
Ethernet
31
Level shifter
3.8
I/O Header
4014
10
2.5
Serial Port
31
10
SPI Header
103
(Dimensions in mm)
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Schematic/Theory of OperationSchematic/Theory of Operation
• Main functionsMain functions– Read RFID TagsRead RFID Tags– Choose a display imageChoose a display image– Retrieve image data from updatable SD cardRetrieve image data from updatable SD card– Communicate / update data with Ethernet Communicate / update data with Ethernet – Send image data to LCD screenSend image data to LCD screen– User interaction with displayUser interaction with display
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Schematic/Theory of OperationSchematic/Theory of Operation
• Basic Power RequirementsBasic Power Requirements– All components run at 3.3VAll components run at 3.3V– On board voltage regulatorOn board voltage regulator– Microcontroller voltage regulatorMicrocontroller voltage regulator
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWERPOWER
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POWERHEADER
• Power/Ground header for 5V Wall-wart
DIODE/FUSE
REGULATOR
• 278R33 - 3.3V regulator
• Diode/Fuse for protection
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
MICRO
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MICRO• MC9S12NE64
I/O
SCI SPI
ET
HE
RN
ET
• Decoupling Caps• Interfacing
3.3 Voltage Rail
Ground Rail3.
3 V
olta
ge R
ail
Gro
und
Rai
l
DECOUPLING CAPS
D CAP
CLOCKINGBDM
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
ETHERNET
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ETHERNET
• RJ-45 Connector
RJ-45
DECOUPLING CAPS
PULL UP• Pull Up Resistors
• Freescale’s suggested layout
• Decoupling caps
3.3 Voltage Rail
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
CLOCKINGBDM
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CLOCKINGBDM
• Freescale’s suggested layout
3.3 Voltage Rail
Ground Rail
HEADER
• BDM with external reset switch
• Clocking - 25MHz
RESET SWITCH
25 MHz Oscillator
CAP / RES network
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
SCI SERIAL
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SCI SERIAL
• Both SCI ports
• Pinned out
HEADER
• Level Shifter
MAX3222 Level Shifter
CAP / RES NETWORK
• Suggested Layout
SERIAL PORTS
• SLCD and RFID connections
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
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SPI Pinout
HEADER3.3 Voltage Rail
Ground Rail
• SPI interfaces with SD Card Reader
• Status LED’s using PG port GPIO
STATUSLED’S
3.3
Vol
tage
Rai
l
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
I/O & USER INPUT
![Page 31: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/31.jpg)
3.3 Voltage Rail
I/O & USER INPUT • I/O Header
• Optical Isolator
GPIO Header
3.3
V
Gro
und
• Header for Push Button
OPTICAL ISOLATORPUSH
BUTTON
![Page 32: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/32.jpg)
Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
![Page 33: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/33.jpg)
PCB LayoutPCB Layout
• Main considerationsMain considerations– Parallel power and ground railsParallel power and ground rails– Decoupling Capacitors near componentsDecoupling Capacitors near components– Transmit and Receive lines uninterruptedTransmit and Receive lines uninterrupted– Ethernet / Clocking circuits isolatedEthernet / Clocking circuits isolated
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POWER
PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 35: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/35.jpg)
PCB LayoutPCB Layout
• Main power and ground rails parallel
• Minimal current looping
• Trace width of 60mil
POWER
![Page 36: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/36.jpg)
PCB LayoutPCB Layout
• Main power and ground rails parallel
• Minimal current looping
• Trace width of 60mil
POWER
• Header easily accessed on edge
HEADER
DIODE&FUSE
• Diode / Fuse protection
REGULATOR
• On board regulator
• Status LED’s
STATUS LEDs
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PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 38: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/38.jpg)
MICRO
• Clocking/BDM
• Ethernet
• Decoupling Caps
CLOCKINGBDM
ETHERNETETHERNET CAPS
CAP
CAPS
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PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 40: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/40.jpg)
ETHER-NET
• RJ-45 on edge
RJ-45
RESIST / CAPS
• Clear , short path for traces
• Resist and Caps
![Page 41: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/41.jpg)
PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 42: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/42.jpg)
CLOCKINGBDM
SPI
SPI
• SPI for SD pinned out
CLOCKINGCAPS
• Clocking isolated
OSC
• BDM pinned out
BDM HEADER
SWITCH
![Page 43: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/43.jpg)
PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 44: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/44.jpg)
SCI SERIAL
• SCI Traces
• Layer shifter on bottom
LEVEL SHIFTER
HEADER
• SCI Pinout
• Ports on edge
PORT
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PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 46: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/46.jpg)
I/O & USER INPUT
• Extra I/O Pinouts
PORT
• Optical Isolator
OPTICAL ISOLATORPUSH
BUTTON HEADER
• External User Input
![Page 47: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/47.jpg)
PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 48: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/48.jpg)
Software Design/Development StatusSoftware Design/Development Status
• Basic interfacing of peripherals Basic interfacing of peripherals – SCI, SPI, GPIOSCI, SPI, GPIO
• RFID system RFID system – Antenna and reader communicatingAntenna and reader communicating
• SD Card SD Card – Attempting card communicationAttempting card communication
• LCD displayLCD display– Transferring of bitmapsTransferring of bitmaps
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Project Completion TimelineProject Completion TimelineTASK DESCRIPTION Week 9 Week 10 Week 11 Week 12 Week 13 Week 14 Week 15 Hardware Revise Schematic Design Revise PCB Layout Component Soldering Board Testing Software Initial Peripheral Communication SLCD Communication SLCD Image display RFID Communication RFID tag reading SPI/SD card read and write Image Display Algorithm Ethernet Initialization FAT File System Design
Update Files through Ethernet Packaging Kiosk Prototyping Kiosk Construction Hardware Integration Documentation User Manual Final Presentation/Documentation
![Page 50: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/50.jpg)
Questions / DiscussionQuestions / Discussion
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Schematic/Theory of OperationSchematic/Theory of Operation
MICROI/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI Pinout
ETHERNET
POWER
![Page 52: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/52.jpg)
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PCB LayoutPCB Layout
MICRO
I/O & USER INPUT
CLOCKINGBDM
SCI SERIAL
SPI
ETHER-NET
POWER
![Page 54: ECE 477 Design Review Team 4 Spring 2008 Zach Dicklin Amy Ritter Ian Bacon Eric Yee.](https://reader035.fdocuments.us/reader035/viewer/2022062717/56649e495503460f94b3d47d/html5/thumbnails/54.jpg)