ECE 477 DESIGN REVIEWFEST – FALL 2011

OUTLINE

Project overview

Project-specific success criteria

Block diagram

Component selection rationale

Packaging design

Schematic and theory of operation

PCB layout

Software design/development status

Project completion timeline

Questions/discussion

PROJECT OVERVIEW

Automated system for testing speakerphones

Delivers • test signals • pre-recorded audio

Used to determine • time delay• frequency response

Records audio output from DUT

PSSC

An ability to measure time delay response between project’s

components; the playback device, the telephone line simulator,

the DUT which is the speakerphone, and the receiving device.

An ability to determine the frequency response of the DUT.

An ability to “play back” sound files.

An ability to record audio and write it to non-volatile (removable)

memory.

An ability to perform duplex testing of recording data and playing

back data.

BLOCK DIAGRAM

COMPONENT SELECTION RATIONALE

TMS320F-28035 MCU• 80 pin count, 128KB on-chip Flash• ANSI C language• 60 MHz• 2 - SPI, 1- SCI, 1 – I2C• 14 PWM and 16 ATD

COMPONENT SELECTION RATIONALE

TLV320AIC23 Audio Codec• 8 – 96 KHz sampling up to 24-bit depth• Stereo Channel

COMPONENT SELECTION RATIONALE

LCD – 09568• SCI/SPI interface• Programmable baud rate• 20 x 4

COMPONENTS PROVIDED

PACKAGING DESIGN

Back• Power switch• Reset button• Power jack• Power LED

Side• SD Card• RJ11

PROJECT PACKAGING

Front• Microphone

• XLR• ¼”

• Speaker

TOP• LCD• 4 Push Buttons

Front

Left

Top

THEORY OF OPERATION

Power Management• Power rails of 3.3 V and 5.0 V needed.• Two voltage regulators will be used for getting the

desired power rails.

POWER SCHEMATIC

THEORY OF OPERATION

SD Card• Operating Voltage - 3.3V• Interfaced using SPI module.• Run at 15 Mhz (Maximum supported by SPI moudle)• Will be used to read and write audio files.

SD CARD SCHEMATIC

THEORY OF OPERATION

LCD• Operating Voltage – 5.0V• Interfaced using SCI module.• Run at 9600 Baud rate• Will be used to implement a simple user interface.• 20 x 4

LCD SCHEMATIC

SCHEMATICTHEORY OF OPERATION

MCU• SPI

SCHEMATICTHEORY OF OPERATION

MCU• I2C – Used to program the codec

SCHEMATICTHEORY OF OPERATION

MAIN (MCU AND POWER)

MAIN PCB Includes:• 5V and 3.3V Regulators (LT1086)• TI Microcontroller (TMS320F28035)• Transceiver (MAX3221)• Digital Isolator (ISO7221A)• 14-pin Header• SD Card Header (M11)• JTAG• Power Jack “Wall wart”

MCU AND POWER

CODEC (AND OTHER)

 CODEC PCB Includes:• Codec (TLV320AIC23B)• 3.5mm Audio Jacks (Microphone & Speaker)• Data Access Arrangement device (CH1840)• Microphone Preamplifier (MAX4063) • Simple 6-pin RJ11 Jack• Potentiometer• 14-pin Header• 5V and 3.3V Regulators (LT1086)

CODEC AND OTHER

PIN ASSIGNMENTGPIO PINS Mux 1 Mux 2 Mux 3 Mux 4 GPIO Name

GPIO00 EPWM1A      

GPIO01 EPWM1B   COMP1OUT  

GPIO02 EPWM2A      

GPIO03 EPWM2B SPISOMIA COMP2OUT  

GPIO04 EPWM3A       OP3*

GPIO05 EPWM3B SPISIMOA ECAP1   SPIA_WP*

GPIO06 EPWM4A EPWMSYNCI EPWMSYNCO  

GPIO07 EPWM4B SCIRXDA    

GPIO08 EPWM5A   ADCSOCAO'  

GPIO09 EPWM5B LINTXA HRCAP1  

GPIO10 EPWM6A   ADCSOCBO'  

GPIO11 EPWM6B LINRXA HRCAP2   SPIA_CD*

GPIO12 TZ1' SCITXDA SPISIMOB

GPIO13 TZ2' SPISOMIB     DATA/VOICE*

GPIO14 TZ3' LINTXA SPICLKB   RUN/STOP*

GPIO15 TZ1' LINRXA SPISTEB'  

GPIO16 SPISIMOA TZ2'

GPIO17 SPISOMIA TZ3'

PIN ASSIGNMENTGPIO PINS Mux 1 Mux 2 Mux 3 Mux 4 GPIO Name

GPIO18 SPICLKA LINTXA XCLKOUT

GPIO19 XCLKIN SPISTEA' LINRXA ECAP1

GPIO20 EQEP1A   COMP1OUT  

GPIO21 EQEP1B   COMP2OUT   OFF_HOOK*

GPIO22 EQEP1S   LINTXA  

GPIO23 EQEP1I LINRXA

GPIO24 ECAP1   SPISIMOB  

GPIO25 SPISOMIB

GPIO26 HRCAP1 SPICLKB

GPIO27 HRCAP2 SPISTEB'

GPIO28 SCIRXDA SDAA TZ2'

GPIO29 SCITXDA SCLA TZ3'

GPIO30 CANRXA      

GPIO31 CANTXA      

GPIO32 SDAA EPWMSYNCI ADCSOCAO'

GPIO33 SCLA EPWMSYNCO ADCSOCBO'

GPIO34 COMP2OUT COMPT3OUT    

GPIO35 TDI

PIN ASSIGNMENTGPIO PINS Mux 1 Mux 2 Mux 3 Mux 4 GPIO Name

GPIO36 TMS

GPIO37 TDO

GPIO38 TCK XCLKIN

GPIO39         OP2*

GPIO40 EPWM7A       OP0*

GPIO41 EPWM7B       OP1*

GPIO42 COMP1OUT      

GPIO43 COMP2OUT      

GPIO44        

PIN ASSIGNMENTADC Comparator Digital Input

ADCINA7    

ADCINA6 COMP3A AIO6

ADCINA5    

ADCINA4 COMP2A AIO4

ADCINA3    

ADCINA2 COMP1A AIO2

ADCINA1    

ADCINA0    

   

ADCINB7    

ADCINB6 COMP3B AIO14

ADCINB5    

ADCINB4 COMP2B AIO12

ADCINB3    

ADCINB2 COMP1B AIO10

ADCINB1    

ADCINB0    

SOFTWARE DESIGNDEVELOPMENT STATUS

Interrupt-driven software

Interrupt generated by Timer module for accurate

task transition• Each interrupt causes MCU to switch task and

spoon-feed necessary modules with data (SPI, SCI, I2C, etc.)

• Buttons also generate interrupt

Same repetitive tasks until test is stopped or SD

card is full

Remaining CPU time for signal processing math

SOFTWARE DESIGN DEVELOPMENT STATUS

SOFTWARE DESIGN DEVELOPMENT STATUS

1. Out-of-reset• Display menu• Check SD card status• Display test options

2. Begin test• Measure time delay• Measure frequency response• Any other pre-programmed tests

3. Free-run test until SD card is full

TIMELINE

*DR = Design Review Week

Expected Completion (Week)

FatFS (FAT32) DR DR + 4

FFT + Auto Correlation DR + 2 DR + 6

Wrap Up ( Processor Time Allocation )

DR + 4 DR + 6

Interrupt, SCI, Codec(I2C, SPI, and Timer)

DR

Wave File Header DR

QUESTIONS

Please Don’t ask any…