ECE 4510/5530Microcontroller Applications

Chapter 7

Dr. Bradley J. BazuinAssociate Professor

Department of Electrical and Computer EngineeringCollege of Engineering and Applied Sciences

ECE 4510 2

Chapter 7: Parallel Ports

• I/O Addressing Modes• Input data from switches• Output data to LEDs• Data transfer

ECE 4510 3

Overview of HCS12 Parallel Ports

• HCS12 device may have from 48 to 144 pins arranged in 3 to 12 I/O ports and packaged in a quad flat pack (QFP) or low profile quad flat pack (LQFP).

• A QFP or Quad Flat Package is an integrated circuit package with leads extending from each of the four sides. It is used for surface mounting (SMD) only, socketing or hole mounting is not possible. There are versions having from 32 to over 200 pins with a pitch ranging from 0.4 to 1.0 mm. Special cases include LQFP (Low profile QFP) and TQFP (Thin QFP).

ECE 4510

Basic Concepts of I/O

• I/O devices are also called peripheral devices.– For microcontrollers, they are usually part of the IC– For microprocessors, they are usually separate ICs

• I/O devices are consist of circuitry (logic or a device) that exchange data with a computer processing unit (CPU).– Examples data includes: switches, light-emitting diodes, cathode-

ray tube screens, printers, modems, keyboards, and disk drives.

ECE 4510

Interface (Peripheral) Logic/IC (1 of 2)

• Logic/IC whose function is to synchronize data transfer between the CPU and I/O devices– Consists of control registers, status registers, data direction latches, and

control circuitry– Has pins that are connected to the CPU and I/O port pins that are

connected to the I/O devices

• Each interface chip has a chip enable signal input or inputs, when asserted, allow the interface chip to react to the data transfer request.– Data transfer between an I/O device and the CPU can be proceeded bit-

by-bit or in multiple bits (parallel).– For embedded devices, this is the peripheral register address!

ECE 4510

AddressDecoder

Microprocessor

Data Bus

Interfacechip 1

Interfacechip 1

frominputdevice

tooutputdeviceI/O pins

Figure 7.1 Interface chip, I/O devices, and microprocessor

CE CE

Interface (Peripheral) Chip (2 of 2)

• Address decoder makes sure that each time one and only one peripheral device responds to the CPU’s I/O request.

ECE 4510 7

Adapt9S12DP512 I/O Pins

ECE 4510 8

DP512CPU Pins and Peripherals(No internal Busses Shown)

ECE 4510 9

HCS12 Parallel Ports

• The number of pins available in each I/O port for HCS12 are (see mc9s12dp512.s and mc9s12dp512.h for names):– PORTA 8 pins PA7 – PA0– PORTB 8 pins PB7 – PB0– PORTE 8 pins PE7 – PE0– PTH 8 pins PH7 – PH0– PTJ 4 pins PJ7, PJ6, PJ1, PJ0– PORTK 7 pins PK7, PK5 – PK0– PTM 8 pins PM7 – PM0– PTP 8 pins PP7 – PP0– PTS 8 pins PS7 – PS0– PTT 8 pins PT7 – PT0– PORTAD1, PORTAD0 16 pins PAD15 – PAD0

ECE 4510

HCS12 Parallel Ports (1 of 3)

• All I/O pins serve multiple functions.– When a peripheral function is enabled, its associated pins cannot

be used as general purpose I/O pins.

• Each I/O port has several registers to support its operation.

• Registers related to I/O ports have been assigned a mnemonic name and the user can use these names to refer to them (see mc9s12dp512.s and mc9s12dp512.h):– movb #$FF, PortA ; output $FF to Port A

ECE 4510

HCS12 Parallel Ports (2 of 3)

• All I/O ports (except PORTAD0 and PORTAD1) have an associated data direction register and a data register.

• The name of the data direction register is formed by adding the letters “DDR” as the prefix to the port name. For example, DDRA, DDRB, and DDRT.– To configure a pin for output, write a ‘1’ to the associated bit in the

data direction register.

• To configure a pin for input, write a ‘0’ to the associated bit in the data direction register.movb #$FF,DDRA ; configure port A for outputmovb #0,DDRA ; configure port A for inputbset DDRA,$81 ; configure Port A pin 7 and 0 for output

ECE 4510 12

HCS12 Parallel Ports (3 of 3)

• We use “PORT” as the prefix to the port name for ports A, B, E, and K.

• For the other ports, the register name is formed by adding letters “PT” as the prefix to the port name. For example, PTH, PTJ, PTM, PTP, PTS, and PTT.

• Output a value to a port is done by storing that value to the port data register.

• movb #$FF,DDRH ; configure Port H for output• movb #$37,PTH ; output the hex value 37 to port H

• Input a value from an input port is done by loading from the port data register.

• movb #0,DDRH ; configure Port H for input• ldaa PTH ; read data from port H into A

ECE 4510 13

References to Parallel Ports

• Better way is to use the = directive (in assembly language) to equate a symbolic name to the address of a given register

• This allows to use the symbolic name to access it• Ex:

PORTA = $0000 PTH = $0260PORTB = $0001 DDRH = $0262DDRA = $0002 PTT = $0240DDRB = $0003 DDRT = $0242

LDAA #$FF ; Configure Port A for outputSTAA DDRALDAA #$FF ; Write to Port ASTAA PORTA

ECE 4510 14

Port B Code Example

• Example writing to port B:.area prog(abs)PORTB = $0001DDRB = $0003.text_main::

Ldaa #$FF Staa DDRB ; configures PB7 – PB0 as output pinsLdaa #$A5Staa PORTB ; write data $A5 on the PORTB

ECE 4510 15

ICC12 Parallel Ports Names

• The naming of the port data registers is not uniform• The names of some of the port data registers are formed by

adding “PORT” as the prefix of the port name or by adding the prefix “PT” only

• Port Name Data register Name• A PORTA• B PORTB• E PORTE• K PORTK• H PTH • J PTJ• M PTM• P PTP• S PTS• T PTT

ECE 4510 16

Basic Concepts of I/O (1)

• The speed and electrical characteristics of I/O devices may be very different from those of CPU– These different characteristics makes it difficult to connect them

directly to the CPU– Interface chips may be used to resolve the differences between the

microprocessor and I/O devices

• A major function of the interface circuitry is to synchronize data transfer between the CPU and I/O devices– Interface circuits (on or off CPU) consists of control registers, data

registers, status registers, data direction registers and control circuitry

ECE 4510 17

Basic Concepts of I/O (2)

• Interface devices have data pins that are connected to the microprocessor data bus and I/O port pins that are connected to the I/O devices– Only one device is allowed to drive data to the data bus at a time– Otherwise, data bus contention can result and the system may be

damaged

• Address Decoder Insures that one and only one device is allowed to drive data to the data bus or accept data from the data bus at a time– A Chip Enable or CE is driven by the address decoder to enable a

peripheral device (typically active low)– Additional address bits may be used for internal I/O register

selection

ECE 4510 18

Basic Concepts of I/O (3)

Control Registers Allows to set up parameters for the desired I/O operations

Data direction registers Allows to select the data transfer direction for each I/O pin

Status Registers Reports the progress and status of the I/O operation

Data Registers Holds the data to be sent to the output device or the new data placed by the input device

ECE 4510 19

Basic Concepts of I/O (4)

• Interface devices is allowed to respond to the data transfer request from the microprocessor only when its chip enable (CE) is enabled– In most devices the chip enable (CE) signal is active low by nature– Otherwise the interface chip is electrically isolated from the data

bus

• Data transfer between the I/O device and the interface devices can proceed bit-by-bit (serial) or in multiple bits (parallel)– Data are transferred serially in low-speed devices such as modems

and low-speed printers– Parallel data transfer is mainly used by high-speed I/O devices

ECE 4510 20

Parallel I/O and the HC12

• Memory-mapped I/O scheme (HC12)– The microprocessor uses the same instruction set to perform memory

accesses and I/O operations.– The I/O devices and memory components are resident in the same

memory space.• A mechanism should be available to make sure:

– Data is valid when the microprocessor reads data– To make sure output device is ready to accept data when the

microprocessor outputs data– For the HC12 parallel ports, this does not exist!

• Brute-Force Synchronization (is OK if timing of data not important) :– The HC12 parallel ports have no inherent synchronization– For input-- The microprocessor reads the interface chip and the interface

chip returns the voltage levels on the input port pins to the microprocessor.

– For output --The interface chip places the data that it received from the microprocessor directly on the output port pins.

ECE 4510 21

HC12 Parallel I/O Synchronization

• Handshake Method:– Interlocked handshake– Use two I/O pins from another port, one input, one output:

• Write I/O– First output level to assert data– First input level to show when data has been read– Output return to remove data– Input return to complete cycle

• Read I/O– First output level to request data– First input level to show when data is available– Output return to acknowledge read of data– Input return to remove data

ECE 4510 22

Input/Read Handshaking

Step 1. The HC12 output pin asserts H1 to indicate its intention to input data.

Step 2. The input device puts data on the data port pins and also asserts the handshake signal H2.

Step 3. The HC12 output pin reads the data and de-asserts H1. After some delay, the input device also de-asserts H2.

Valid Data

H1

Data

H2

(a) Interlocked

ECE 4510 23

Output/Write Handshaking

Step 1. The HC12 places data on the port pins and asserts H1 to indicate that it has valid data to be output.

Step 2. The output device latches the data and asserts H2 to acknowledge the receipt of data.

Step 3. The HC12 output pin de-asserts H1 following the assertion of H2. The output device then de-asserts H2.

Valid D ata

(a) Inte r lo c ke d

H 1

H 2

D ata

ECE 4510 24

Electrical Characteristic Consideration for I/O Interfacing

• Most systems require the use of logic chips and/or peripheral devices apart from the microcontroller to perform their function

• These chips may use different types of Integrated Circuit (IC) technologies. If so, there is a concern that the resultant system may not function properly

• The ICs must be electrically compatible• Two issues involve

– Voltage-level compatibility– Current drive capacity

ECE 4510 25

Voltage and Current

• Voltage-level compatibility– High output level of an IC chip high enough to be considered as a

high for the input of another chip– Low output level of an IC chip low enough to be considered as a

low for the input of another chip

• Current drive capability– Output of an IC chip have enough current to drive its load– Can the output circuit of an IC chip sink the current of its load

• Signal timing is also an important factor for making sure that the digital circuit functions properly– The main concern about timing is whether the signal from one chip

becomes “valid enough” to be used by another IC chip in a timely (clock based?) manner

ECE 4510 26

Voltage Level compatibility

Voltage level compatibility issue arises because IC technologies differ in the following four voltages:

Input High Voltage (VIH) treated as logic 1 when applied as input to the digital circuit

Input Low voltage (VIL) treated as logic 0 when applied as input to the digital circuit

Output High Voltage (VOH) voltage level when digital circuit outputs a logic 1

Output Low Voltage (VOL) voltage level when digital circuit outputs a logic 0

ECE 4510 27

Voltage Level compatibility (2)

• In order for the digital circuit X to be able to drive circuit Y, the following conditions must be satisfied– The output high voltage of device X (VOHX) must be higher than

the input high voltage of device Y (VIHY). – The output low voltage of device X (VOLX) must be lower than

the input low voltage of device Y (VILY).

ECE 4510 28

Logic Family Voltage Levels

Logic Family VCC VIH VOL VIL VOL HCS123 5 V 3.25 V 4.2 V 1.75 V 0.8 V S4 5 V 2.0 V 3.0-3.4 V1 0.8 V 0.4-0.5 V2 LS4 5 V 2.0 V 3.0-3.4 V1 0.8 V 0.4-0.5 V2 AS4 5 V 2.0 V 3.0-3.4 V1 0.8 V 0.35 V F4 5 V 2.0 V 3.4 V 0.8 V 0.3 V HC3 5 V 3.5 V 4.9 V 1.5 V 0.1 V HCT3 5 V 3.5 V 4.9 V 1.5 V 0.1 V ACT3 5 V 2.0 V 4.9 V 0.8 V 0.1 V ABT3 5 V 2.0 V 3.0 V 0.8 V 0.52 V BCT5 5 V 2.0 V 3.3 V 0.8 V 0.42 V FCT5 5 V 2.0 V 2.4 V 0.8 V 0.55 V

1. VOH value will get lower when output current is larger. 2. VOL value will get higher when output current is larger. The VOL values of different

logic gates are slightly different 3. HCS12, HC, HCT, ACT are based on CMOS technology. 4. S, LS, AS, and F are based on bipolar technology. 5. ABT, BCT, and FCT are based on bi-CMOS technology.

ECE 4510 29

HC12 Compatibility

• 5 Volt technology compatibility– CMOS is compatible– LS TTL is not compatible

ECE 4510 30

Voltage Level compatibility (3)

Summarizing Voltage Level Compatibilities:• HCS12 cannot be driven by a bipolar device (S, LS, AS, F).• HCS12 can be driven by CMOS devices (HC, HCT)• HCS12 may not work with ACT CMOS devices, VIL=VOL• HCS12 will likely have problems with Bi-CMOS ,

VIL=VOL and VOH <= VIH(HC12) (ABT, BCT, FCT)

ECE 4510 31

Current Drive Capability

• Microcontrollers needs to drive other peripheral I/O devices in an embedded system

• Other issue is whether the microcontroller can source (when the output voltage is high) or sink (when the output voltage is low) the current needed by the I/O device that it interfaces with

• Need to make sure the following two requirements– Each I/O pin can supply and sink the current needed by the I/O

device that it interfaces with– Total current required to drive I/O devices does not exceed the

maximum current rating of the microcontroller

ECE 4510 32

Current Considerations

• Each logic chip has the following four currents that are involved in the current drive calculationsInput high current (IIH) Input current (flowing into the input pin)

when the input voltage is highInput low current (IIL) Input current (flowing out of the input pin)

when the input voltage is low

Output high current (IOH) Output current (flowing out of the output pin) when the output voltage is high

Output low current (IOL) Output current (flowing into the output pin) when the output voltage is low

ECE 4510 33

Terms: Fan-out and Fan-in

Fan-in: how many devices driven an integrated circuit to perform its function. Usually applied to logic gates

Fan-out: how many devices can be driven by a circuits output. Often done based on a technology family or typical input current

Note1: Driving analog circuits or LEDs can rapidly change the output current required.Note2: A digital output should never drive both analog and digital inputs!

IL

OL

IH

OH

II

IIFanout ,min

ECE 4510 34

Logic Family Current Levels

Logic Family VCC IIH IIL IOH IOL HCS1223 5 V 2.5 uA 2.5 uA 25 mA 25 mA S 5 V 50 uA 1.0 mA 1 mA 20 mA LS 5 V 20 uA 0.2 mA 15 mA 24 mA AS 5 V 20 uA 0.5 mA 15 mA 64 mA F 5 V 20 uA 0.2 mA 1 mA 20 mA HC3 5 V 1 uA 1 uA 25 mA 25 mA HCT3 5 V 1 uA 1 uA 25 mA 25 mA ACT3 5 V 1 uA 1 uA 24 mA 24 mA ABT3 5 V 1 uA 1 uA 32 mA 64 mA BCT 5 V 20 uA 1 mA 15 mA 64 mA FCT3 5 V 1 uA 1 uA 15 mA 64 mA

1. Values are based on the 74XX244 devices of Texas Instruments.. 2. The total HCS supply current is 65 mA. 3. The values of IIH and IIL are input leakage currents.

ECE 4510 35

Current Source and Sink

• To determine whether a pin can supply or sink currents to all peripheral pins that it drives correctly, designer needs to check the two requirements– The IOH of an output pin must be equal to or larger than the total

current flowing into all the peripheral pins that are connected to this pin.

– The IOL of an output pin must be equal to or larger than the total current flowing out from all the peripheral pins that are connected to this pin

• Also need to make sure that the total current needed to drive the peripheral signal pins do not exceed the total current the microcontroller can supply

ECE 4510 36

Fan-Out

• HC12* to HC12s

• HC12* to LS TTL

• HC12* to HC/HCT

• LS TTL to HC12

• HC/HCT to HC12

• * 2.5 mA vs. 25 mA due to spec sheet

000,15.25.2,

5.25.2min

uAmA

uAmAoutFan

5.122.05.2,

205.2min

mAmA

uAmAoutFan

500,215.2,

15.2min

uAmA

uAmAoutFan

000,65.2

24,5.2

15min

uAmA

uAmAoutFan

000,105.2

25,5.2

25min

uAmA

uAmAoutFan

ECE 4510 37

HC12 I/O

P: Those parameters are guaranteed during production testing on each individual device.

C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.

T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.

D: Those parameters are derived mainly from simulations.

MC9S12DP256B Device User Guide V02.15, Doc. No. 9S12DP256BDGV2/D, Original Release Date: 29 Mar 2001, Revised: Jan 11, 2005, Motorola, Inc

ECE 4510 38

Timing Compatibility

• Timing compatibility needs to be taken into consideration if the I/O pin is driving a flip-flop or a latch

• Latch or flip-flop has a control signal or clock signal to control the latching of an input signal

D

CLK

Q

Q

Figure 7.28 D flip-flop and its latching timing requirement

(a)

D

CLK

tsu

thd

(b)

ECE 4510 39

Timing Compatibility (2)

• Main timing consideration is the setup and hold time requirements for all flip-flop and latches

• Setup and hold time needs to be addressed in order for the system to work properly

• If the signal passes through several intermediate devices before it reaches latches or flip-flops, time delays of all intermediate devices needs to be taken into account

D

CLK

Q

Q

Figure 7.28 D flip-flop and its latching timing requirement

(a)

D

CLK

tsu

thd

(b)

ECE 4510 40

Timing Compatibility (3)

• Setup and hold times describe the timing requirement on the input of the flip-flop with respect to the clock input– Setup time is the time that the input must be valid before the flip-

flop samples– Hold time is the time that the input must be maintained valid after

the flip flop samples

• Setup and hold time define a window of time during which the input must be valid and stable in order to get the valid data on the output

D

CLK

Q

Q

Figure 7.28 D flip-flop and its latching timing requirement

(a)

D

CLK

tsu

thd

(b)

ECE 4510 41

Interfacing with Output Devices

• Many embedded devices only require interfacing with simple input and output devices such as switches, light emitting devices, keypads, seven segment displays etc

• Interfacing with LED’s:– LED’s are often used to indicate the system operation mode

• Whether the system is turned on• Whether the system operation is normal• Whether the system is in error mode etc

– An LED can illuminate when it is forward biased and has sufficient current following through it

– The current required to light an LED is nominally around 10mAThe 7-segfment displays want 20 mA.

ECE 4510 42

Interfacing with LEDs

• Three methods for interfacing with LED’s• Method A and B are recommended for use with LED’s that

need only 1 to 2mA to produce enough brightness• The circuit C is required for use with LED’s that need

larger current to light and the ECE 4510/5530 labs• Circuit C Resistor value can be between 330 ohm and 1

Kohm

74HC04

VCC

Figure 7.29 An LED connected to a CMOS inverter through a current- limiting resistor.

Portpin

(a) positive direct drive (c) buffered drive

R1

R2

R3

VCC

Portpin

Portpin(b) inverse direct

drive

ECE 4510 43

Lab LED and Light Bar Connections

• Buffer the HC12 port– Inverting buffer ‘540– Non-inverting buffer ‘541– Provide current sinking for the

LED

• Resistor between +5 and LED– If you short the LED while

probing, the resistor provides current limiting

• Resistor Value– LED needs ~1.2 to 1.8 V drop– LED wants ~ 10 mA

38010

2.15mA

VVR

32010

8.15mA

VVR

ECE 4510 44

Interfacing with Seven Segment Displays

• Seven segment displays are often used when the embedded products needs to display only a few digits– Seven segment displays are mainly used to display decimal digits and a

small subset of letters

• Although HCS12 devices have enough current to drive a seven segment display, it is not advisable to do when a HCS12 based embedded product needs to drive many other I/O devices– Best way is to use a buffer chip 74HC244 between microcontroller and

seven segment display– 74HC244 provides 5v and using a 330 ohm resistor between 74HC244

and seven segment display provides a current of 10mA, sufficient to illuminate an LED

ECE 4510 45

Lab 7-Segment Displays

• Single Digit, Red, Common Anode Display

a b c d e f g dp

1,6

10 9 8 5 4 2 3 7a

b

c

d

e

fg

dp

Data Sheet Values:• Forward Voltage 2.1-2.6 V

at I=10 mA

ECE 4510 46

Driving a Common Anode Display

• Forward Voltage 2.1-2.6 Vat I=10 mA a b c d e f g dp

1,6

1 2 3 4 5 6 7 8

916 15 14 13 12 11 10

HC12 Pin

HC12 Pin

HC12 Pin

HC12 Pin

HC12 Pin

HC12 Pin

HC12 Pin

HC12 Pin

‘540 Inverting

Buffer

10 9 8 5 4 2 3 7

mA

VtoVVR10

6.21.25

290240 R

ECE 4510 47

BCD to 7-Segment Decoder

BCDdigit a b c d e f g

Segments Corresponding Hex Number

0123456789

1011011111

1111100111

1101111111

1011011011

1010001010

1000111011

0011111011

$7E$30$6D$79$33$5B$5F$70$7F$7B

Table 7.5 BCD to seven-segment decoder

a

b

c

d

e

fg

dp

ECE 4510 48

Multiple Displays, Common Cathode

• Some applications needs to display multiple BCD digits, then time multiplexing technique will be used

• Seven segment displays consists of either a common anode or common cathode which plays a key role in turning on and off the seven segment display

• Common Cathode (Note: The lab uses common Anode)– Common cathode of the seven segment display is connected to the

collector of an NPN transistor– When a high voltage is applied to the base of the NPN transistor, it is

driven to saturation – The common cathode of the display will then be driven low allowing the

display to be lighted– By turning the NPN transistors ON and OFF many times in a second,

multiple digits can be displayed

ECE 4510 49

Multiple 7-Segment Displays, Common Cathode

.

.

.

ab

g

PB6 PB5 PB0

Figure 7.32 P ort B and P ort K together drive six seven-segment displays (M C9S12DP 256)

. . .. . .

. . .74HC244

HCS12

ab

g

.

.

.

c o m m o nc athode

c o m m o ncathode

c o m m o nc athode

ab

g

I MA

X = 7

0 m

A

.

.

.

R

R

R 2N2222

2N2222

2N2222

300

PK5

PK4

PK0

300

#5 #4 #0

ECE 4510 50

Multiple Displays, Common Anode

• Some applications needs to display multiple BCD digits, then time multiplexing technique will be used

• Seven segment displays consists of either a common anode or common cathode which plays a key role in turning on and off the seven segment display

• Common Anode– Common anode of the seven segment display is connected to the collector

of a PNP transistor– When a “low voltage” is applied to the base of the PNP transistor, it is

driven to saturation – The common anode of the display will then be driven high allowing the

display to be lighted– By turning the PNO transistors ON and OFF many times in a second,

multiple digits can be displayed

ECE 4510 51

#include <hcs12.inc>four equ $33 ; seven-segment pattern of digit 4

movb #$3F,DDRK ; configure PORT K for outputmovb #$FF,DDRB ; configure PORT B for outputbset PTK,$10 ; turn on seven-segment display #4bclr PTK,$2F ; turn off seven-segment displays #5, #3…#0movb #four,PTB ; output the seven-segment pattern to PORTP

In C language:DDRK = 0x3F;DDRB = 0xFF;PTK = 0x10;PTB = 0x33;

Example 7.4

• Example 7.4 Write a sequence of instructions to display 4 on the seven-segment display #4 in Figure 7.32.

• Solution: To display the digit 4 on the display #4, we need to: – Output the hex value $33 to port B– Set the PK4 pin to 1– Clear pins PK5 and PK3...P0 to 0

ECE 4510 52

seven-segmentdisplay

displayedBCD digit P ort B P ort K

#5#4#3#2#1#0

123456

$30$6D$79$33$5B$5F

$20$10$08$04$02$01

T able 7.6 T able of display patterns for Example 7.5

Example 7.5

• Example 7.5 Write a program to display 123456 on the six seven-segment displays shown in Figure 7.32.

• Solution: Display 123456 on display #5, #4, #3, #2, #1, and #0, respectively.

• The values to be output to Port B and Port K to display one digit at a time is shown in Table 7.6.

ECE 4510 53

Start

X address of display table

Output the byte at [X] to port BOutput the byte at [X]+1 to Port K

Increment X by 2Wait for 1 ms

X = display + 12?no

yes

Figure 7.33 Time-multiplexed seven-segment display algorithm

Time Multiplexing 7-Segment Displays

ECE 4510 54

#include "c:\miniide\hcs12.inc"pat_port = PTB ; Port that drives the segment patternpat_dir = DDRB ; direction register of the segment patternsel_port = PTK ; Port that selects the digitsel_dir = DDRK ; data direction register of the digit select port.text_main::

movb #$FF,pat_dir ; configure pattern port for outputmovb #$3F,sel_dir ; configure digit select port for output

forever: ldx #disp_tab ; use X as the pointerloop: movb 1,x+,pat_port ; output digit pattern and move the pointer

movb 1,x+,sel_port ; output digit select value and move the pointerldy #1 ; wait for 1 msjsr delayby1ms ; “ cpx #disp_tab+12 ; reach the end of the tablebne loopbra forever#include "c:\miniide\delay.asm"

disp_tab .byte $30,$20 ; seven-segment display table.byte $6D,$10.byte $79,$08.byte $33,$04.byte $5B,$02.byte $5F,$01

Code Example

ECE 4510 55

DIP Switches

• Switch is probably the simplest input device available• To make input more efficient, a set of eight switches

organized as a Dual inline package (DIP) is often used• A DIP package can be connected to any input port with

eight pins such as PortA, PortB etc• When a switch is closed, the associated port input is 0,

otherwise the associated port input is 1• Each port input is pulled up high via a 330 ohm or 1Kohm

resistor when the associated switch is open

ECE 4510 56

Connecting DIP SwitchesVCC

10K

PA0PA1PA2PA3PA4PA5PA6PA7

HCS12

Figure 7.39 Connecting a set of eight DIP switches to Port A of the HCS12

SW DIP-8

ECE 4510 57

Buffering Dip Switches

• For the ECE 4510 Lab, all dip switches should be buffered.

• One possible buffering configuration is shown here

ECE 4510 58

Reading DIP Switches Steps

Ex: Instruction to read data from DIP switches on PortA• Step1: Define the corresponding Data Direction Register

and Data Register of PortA• Step2: Set the Data Direction Register of PortA to

configure port as an input port• Step3: Read the data from the Data register of PortA

according to the requirements of the program.

• Data from the DIP switches is always available in the Data Register of the corresponding port with which it’s interfaced to

ECE 4510 59

Code Example

.area prog(abs)PORTA = $00DDRA = $02.text_main::

Ldaa #$00Staa DDRA

Loop:Ldaa PORTAStaa resultjsr delay15msecBra Loop

ECE 4510 60

Switch/Contact Bounce

• A contact is made, many transient touch may occur..

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Switch/Contact Bounce

• Contact bounce is due to the dynamics of a closing contact– The signal falls and rises within a period of about 5ms as a contact

bounces– Human being cannot press and release a switch in less than 20ms, a de-

bouncer will recognize that the switch is closed after the voltage is low for about 10ms and will recognize after that the switch is open after the voltage is high for about 10ms

• Both H/W and S/W solutions to the key bounce problem are available• H/W solution includes an analog circuit that uses a resistor and a

capacitor, and two digital solutions that uses S-R latches or CMOS buffers and double throw switches

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Switch Bounce MitigationSet-Reset Latch

• Set-Reset Latches– Before being presses, the key is touching the set input and the Q

voltage is high– When pressed the key moves towards the reset position– When the key is not touching either Set or Reset, both inputs are

pulled low by the pull-down resistor (no change in output)– When key touches the reset position, the Q voltage will go Low– If bouncing of the Set or Reset contact occurs, the “first instance”

will set or reset the device and others will have no effect

ECE 4510 63

Switch Bounce MitigationNon inverting CMOS buffer

• Non inverting CMOS buffer with high input impedance– The CMOS buffer output is identical to its input– When the switch is connected, the input to the buffer chip is

grounded/Vdd and hence Vout is forced low/high– When the key switch is not connected, the resistor R keeps the

input voltage at the same level as the output voltage• This is due to the high input impedance of the buffer, which causes a

negligible voltage drop on the feedback resistor– Once initial switch connection is made, the output moves to the

desired voltage and “no connect” bouncing will not effect the output

ECE 4510 64

Switch Bounce MitigationCapacitor

• Integrated de-bouncers– The RC constant of the integrator determines the rate at which the

capacitor charges up towards the supply voltage once the ground connection via the switch has been removed

– As long as the capacitor voltage does not exceed the logic 0 threshold value, the Vout signal will be recognized as logic 0

– The cheapest approach!

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Switch Bounce MitigationSoftware

• Software De-bouncing Technique– The most popular and simple one has been the wait and see

method. Wait to see if the switch value stabilizes.– In this method, the program simply waits for about 10 ms and

reexamines the same key again to see if it is still pressed.

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Keypad Interfacing

A Keypad is another commonly used input device• Keypad is arranged as an array of switches, which can be mechanical,

membrane, capacitors or Hall-effect in construction– Mechanical Switches Two metal contacts are brought together to

complete an electrical circuit– Membrane Switches Plastic or rubber membrane presses one conductor

onto the other– Capacitive Switches comprise of two plates of a parallel plate

capacitor. Pressing the key cap effectively increases the capacitance between the two plates

– Hall effect Switches Motion of the magnetic flux lines of a permanent magnet perpendicular to the crystal is detected as a voltage, which resembles a switch closure

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16-Button Keypad

• Series 96 by Grayhill, Inc. Web Site: www.grayhill.com– Matrix connections based on which key is pressed– Time multiplex pins 1-4 while reading pins 5-8– A keypad controller IC can be purchased to act as a peripheral

ECE 4510 68

Keypad Scanning

• Keypad scanning is usually performed row-by-row, column-by-column

• A 16-key keypad can be easily interfaced using any available I/O port

• For the keypad application the upper four pins of the port should be configured for output and the lower four pins of the port should be configured for input

• The rows and columns of a keypad are simply conductors• The keypad interface setup to HCS12 PortA is as shown in

the next slide

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Keypad Circuitry

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

10K

VC C

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

HCS12 MCU

Figure 7 .41 S ixteen-key keypad connected to the H C S12

PA7 PA6 PA5 PA4 Selected keys

1110

1101

1011

0111

0,4,8,C,

1,5,9,D,

2,6,A,E,

and 3and 7and Band F

Table 7.16 Sixteen-key keypad row selections

outputs

inputs

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Keypad Operation

• PortA pins PA3 – PA0 are pulled up to high by pull-up resistors

• Whenever a key switch is pressed, the corresponding row and column are shorted together

• In order to distinguish the row being scanned and those not being scanned, the row being scanned is driven low, where as other rows are driven high

PA7 PA6 PA5 PA4 Selected keys

1110

1101

1011

0111

0,4,8,C,

1,5,9,D,

2,6,A,E,

and 3and 7and Band F

Table 7.16 Sixteen-key keypad row selections

ECE 4510 71

More Text I/O Examples

• LCD Controller– An interface to a microcontroller that runs an LCD

• Digital to Analog Converter • Stepper Motor Control

– Drive a “positioning” motor for robotics, etc.– OK for not really fast drive motors