ECE 448: Lab 6 Using PicoBlaze Fast Sorting. Part 1: Introduction to Lab 6 Part 2: Instruction Set...

ECE 448: Lab 6

Using PicoBlazeFast Sorting

Part 1: Introduction to Lab 6Part 2: Instruction Set of PicoBlaze-6Part 3: Hands-on Session: OpenPICIDEPart 4: Lab 6 Exercise 1Part 5: Lab 5 Demos

Agenda for today

ECE 448 – FPGA and ASIC Design with VHDL

Part 1

Introduction to Lab 6

4ECE 448 – FPGA and ASIC Design with VHDL

Sources

• P. Chu, FPGA Prototyping by VHDL Examples

Chapter 14, Picoblaze Overview Chapter 15, Picoblaze Assembly Code Development Chapter 16, Picoblaze I/O Interface Chapter 17, Picoblaze Interrupt Interface

• K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6)

SSD3SSD2

BUTTON

PRNG_STATUSPRNG_CTRL

CYCLE COUNTER & OUTPUT_INTERFACE

INPUT_INTERFACE

PRNGADDR_DECODER

DATARAM

PICOBLAZE

INSTRUCTIONRAM

MEM_BANK

DO[7..0]

DI[7..0]

out_port

A[8..0]

DO[0]A[8]

port_id

A[7..0]

instruction address

addrA[7..0]

RA[7..0]

din

read_strobewrite_strobe

dout

SSD3_en, SSD2_en,SSD1_en, SSD0_en,CCOUNT_en,LED_en, MEM_BANK_en,PRNG_CTRL_en,RAM_wen

weRAM_wen

in_port

interrupt

interrupt_ack

Four 7-segmentdisplays

A[8..0]RD[7..0]

R_wen

R_wen

rinit

rinit

rinit

SSD1SSD0

register

SWITCH

Buttons, Switches

CCOUNT

Switch S7LED

000001002

. . .

0FE0FF100101102103104105106107108109

1FE1FF

255 x 8 DATARAM

MEM_BANKBUTTONSSD3SSD2

LEDPRNG_STATUS

PRNG_CTRL

MEM_BANK

MEM_BANK:

7 6 5 4 3 2 1 0A8

A8 – current memory bank number = the most significant bit of the address

BUTTON:

7 6 5 4 3 2 1 0A

A – button active (bit cleared by reading registerBUTTON or by interrupt_ack)BS – Select, BR – Right, BL – Left,BU – Up, BD - Down

BDBUBLBR

PRNG_STATUS:7 6 5 4 3 2 1 0

D

D – done: bit cleared by writingto register PRNG_CTRL, set after PRNGgenerates 255 8-bit numbers

PRNG_CTRL:

7 6 5 4 3 2 1 0I

I – initialize: after 1 is written to this bit,PRNG generates 255 8-bit numbers, and the corresponding address (index) of each number

SSD1SSD0

SWITCH

BS

CCOUNT

SWITCH:

7 6 5 4 3 2 1 0S0

S7-S0 – bits corresponding to the state of each switch

S1S2S3S4S5S6S7

CCOUNT:

7 6 5 4 3 2 1 0R

R – reset the 64-bit Cycle Counter, and start counting clock cyclesS – stop the Cycle CounterD – display the Cycle Counter (Switch S7 chooses between displaying Least Significant and Most Significant Word)

S

LED:

7 6 5 4 3 2 1 0L0

L7-L0 – bits corresponding to the status of each LED

L1L2L3L4L5L6L7

D

Task 1 – Browsing Mode (default mode)

00 0102030405….

FAFBFCFDFE

00 0102030405….

FAFBFCFDFE

Address Data

Current Address

Two 7-SegmentDisplays

(in hexadecimalnotation) (SSD1-SSD0)

Button Up = Increment Address

Button Down = Decrement Address

Value at Current Address

255x8 RAM

Two 7-SegmentDisplays

(in hexadecimalnotation) (SSD3-SSD2)

Task 2 – Initialize

00 0102030405….

FAFBFCFDFE

25 879426B5C6….

7A5B344389

Address Data

Button Left = Initialize with Pseudorandom Values

Then, returnto the browsing mode

255x8 RAM

8-bit LCG (Linear Congruential Generator)with the period of 28-1

Rn+1 = a * Rn + c (mod m)

where R is the sequence of pseudorandom values, a is the multiplier, c is the increment and m is the modulus. R0 will be the initial seed value.

LCG generates one output per 1 clock cycle.

c

a

R8

= 8-bit register with a set signal to initialize it to R0 after “soft” reset

Task 3 – Sorting

00 0102030405….

FAFBFCFDFE

7F 675344382D….

B1AA9180

Address Data

Sorting signed numbers in the descending order

255x8 RAM

Task 4 – Cycle Count Display Mode

During Sorting display: “----” on the Seven Segment Displays.

After Sorting display: Number of clock cycles used (in the hexadecimal notation)

#Cycles15…0 - 16 least significant bits #Cycles31..16 - 16 most significant bits

Switch between these two values using switch S7 S7=0 : 16 least significant bits S7=1 : 16 most significant bits

Pressing any button (other than Select) after sorting, brings the display back to the browsing mode.

Task 5 (Bonus) – Interrupts

• Modify your circuit in such a way that it generates an interrupt each time any button is pressed

• Modify your assembly language program accordingly, by replacing polling by an interrupt serving routine

• Consider using Register Bank switching in your interrupt service routine (if appropriate)

Contest for the Fastest Implementation of Sorting

Bonus points will be awarded to students who perform sorting (correctly) using the smallest number of clock cycles.

Possible optimizations:• Faster sorting algorithms in software• Efficient assembly language implementation• Faster sorting algorithms in hardware• Efficient hardware implementation


Part 2

Instruction Set of PicoBlaze-6

16

PicoBlaze-3 Programming Model


17

PicoBlaze-6 Programming Model


FFC

FFD

FFE

FFF

Bank ABank B

Syntax and Terminology

Syntax Example Definition

sX

KK

PORT(KK)

PORT((sX))

RAM(KK)

s7

ab

PORT(2)

PORT((sa))

RAM(4)

Value at register 7

Value ab (in hex)

Input value from port 2

Input value from port specified by register a

Value from RAM location 4

Addressing modes

Direct mode

ADD sa, sfINPUT s5, 2a

sa + sf saPORT(2a) s5

Indirect modeSTORE s3, (sa)INPUT s9, (s2)

s3 RAM((sa)) PORT((s2)) s9

s7 – 07 s7s2 + 08 + C s2

Immediate mode

SUB s7, 07ADDCY s2, 08

Arithmetic Instructions (1)

IMM, DIR

C ZAddition

ADD sX, sY

sX + sY => sX

ADD sX, KK

sX + KK => sX

ADDCY sX, sY

sX + sY + CARRY => sX

ADDCY sX, KK

sX + KK + CARRY => sX

Arithmetic Instructions (2)

SubtractionSUB sX, sY

sX – sY => sX

SUB sX, KK

sX – KK => sX

SUBCY sX, sY

sX – sY – CARRY => sX

SUBCY sX, KK

sX – KK – CARRY => sX

IMM, DIR

C Z

Test and Compare Instructions

TEST TEST sX, sY

sX and sY => none

TEST sX, KK

sX and KK => none

COMPARE COMPARE sX, sY

sX – sY => none

COMPARE sX, KK

sX – KK => none

C ZIMM, DIR

IMM, DIR

C = odd parity of

the result

Data Movement Instructions (1)

LOAD

LOAD sX, sY

sY => sX

LOAD sX, KK

KK => sX

IMM, DIRC Z

- -

FETCH

FETCH sX, KK

RAM(KK) => sX

FETCH sX, (sY)

RAM((sY)) => sX


DIR, IND

C Z

- -STORE

STORE sX, KK

sX => RAM(KK)

STORE sX, (sY)

sX => RAM((sY))

DIR, IND

- -

Example 1: Clear Data RAM;=========================================================

; routine: clr_data_mem

; function: clear data ram

; temp register: data, s2

;=========================================================

clr_data_mem:

load s2, 40 ;unitize loop index to 64

load s0, 00

clr_mem_loop:

store s0, (s2)

sub s2, 01 ;dec loop index

jump nz, clr_mem_loop ;repeat until s2=0

return


INPUT

INPUT sX, KK

sX <= PORT(KK)

INPUT sX, (sY)

sX <= PORT((sY))

OUTPUT

OUTPUT sX, KK

PORT(KK) <= sX

OUTPUT sX, (sY)

PORT((sY)) <= sX

DIR, IND

DIR, IND

C Z- -

- -

Edit instructions - Shifts

*All shift instructions affect Zero and Carry flags

Edit instructions - Rotations

*All rotate instructions affect Zero and Carry flags

Program Flow Control Instructions (1)

JUMP AAA

PC <= AAA

JUMP C, AAA

if C=1 then PC <= AAA else PC <= PC + 1

JUMP NC, AAA

if C=0 then PC <= AAA else PC <= PC + 1

JUMP Z, AAA

if Z=1 then PC <= AAA else PC <= PC + 1

JUMP NZ, AAA

if Z=0 then PC <= AAA else PC <= PC + 1


CALL AAA

TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA

CALL C | Z , AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1

CALL NC | NZ , AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1


RETURN

PC <= STACK[TOS] + 1; TOS <= TOS - 1

RETURN C | Z if C | Z =1 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1

RETURN NC | NZ if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1

Subroutine Call Flow


Part 3

Hands-on Session:OpenPICIDE

34

PicoBlaze Development Environments


35

KCPSM6 Assembler Files


KCPSM6.EXE

36

Directives of Assembly Language


Equating symbolic name

for an I/O port ID.

keyboard DSIN $0E

switch DSIN $0F

LED DSOUT $15

N/A

37

Differences between Mnemonics of Instructions


38

Differences between Mnemonics of Instructions


39

Differences between Programs



Example & Demo of Tools


Part 4

Lab 6 Exercise 1

42

• Develop an assembly language implementation of a Linear Congruential Generator (LCG) producing a sequence of 8-bit pseudo-random numbers.

• Then, use OpenPICIDE to debug and simulate your program.

• Recurrence relation

• Rn+1 = a * Rn + c (mod m), where m = 28

a=0x11 c=0x9D

R0=0xD7

• Additionally, assume that * represents an unsigned multiplication

Linear Congruential Generator (LCG)


Example ofa function in the PicoBlaze

assembly language

44

Notation

a Multiplicand ak-1ak-2 . . . a1 a0

x Multiplier xk-1xk-2 . . . x1 x0

p Product (a x) p2k-1p2k-2 . . . p2 p1 p0

45

Multiplication of two 4-bit unsigned binary numbers

Partial Product 0

Partial Product 1

Partial Product 2

Partial Product 3

46

Unsigned Multiplication – Basic Equations

x = xi 2i

i=0

k-1

p = a x

p = a x = a xi 2i =

= x0a20 + x1a21 + x2a22 + … + xk-1a2k-1 i=0

k-1

47

Iterative Algorithm for Unsigned MultiplicationShift/Add Algorithm

p = a x = x0a20 + x1a21 + x2a22 + … + xk-1a2k-1

= (...((0 + x0a2k)/2 + x1a2k)/2 + ... + xk-1a2k)/2 =

k times

=

p(0) = 0

p = p(k)

p(j+1) = (p(j) + xj a 2k) / 2 j=0..k-1

48

Iterative Algorithm for Unsigned MultiplicationShift/Add Algorithm

p = a x = x0a20 + x1a21 + x2a22 + … + x7a27

= (...((0 + x0a28)/2 + x1a28)/2 + ... + x7a28)/2 =

8 times

=

p(0) = 0

p = p(k)

p(j+1) = (p(j) + xj a 28) / 2 j=0..7

49

Unsigned Multiplication Computations

pH pL

8 bits

p

xj a

8 bits

pH pL

pH pLC p(j+1)

2 p(j+1)

p(j)

+ xj a 28

>> 1

PicoBlaze RegisterspH = s5 pL = s6

a = s3x = s4

+

C

50

Unsigned Multiplication Subroutine (1)

;=========================================================; routine: mult_soft; function: 8-bit unsigned multiplier using; shift-and-add algorithm; input register:; s3: multiplicand; s4: multiplier; output register:; s5: upper byte of product; s6: lower byte of product; temporary register: ; s2: index j;=========================================================

51

Unsigned Multiplication Subroutine (2)mult_soft: load s5, 00 ; clear pH load s2, 08 ; initialize loop indexmult_loop: sr0 s4 ; shift lsb of x to carry jump nc, shift_prod ; x_j is 0 add s5, s3 ; x_j is 1, pH=pH+ashift_prod: sra s5 ; shift upper byte pH right, ; carry to MSB, LSB to carry sra s6 ; shift lower byte pL right, ; lsb of pH to MSB of pL sub s2, 01 ; dec loop index jump nz, mult_loop ;repeat until i=0 return


Part 5

Lab 5 Demos

ECE 448: Lab 6 Using PicoBlaze Fast Sorting. Part 1: Introduction to Lab 6 Part 2: Instruction Set...

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