ECE 429 – Introduction to VLSI DesignLecture 18 Sequential Circuit Design I

Professor Jia WangDepartment of Electrical and Computer Engineering

Illinois Institute of Technology

March 20, 2018

ECE 429 – Introduction to VLSI Design Spring 2018 1/16

Outline

Overview: FSM and Ideal Flip-Flops

Setup Condition and Hold Condition

ECE 429 – Introduction to VLSI Design Spring 2018 2/16

Reading Assignment

I This lecture: 10.1–10.3, 10.6.1

I Next lecture: Final Project

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Outline

Overview: FSM and Ideal Flip-Flops

Setup Condition and Hold Condition

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Finite State Machine (FSM)

I A model to reason about computing systemsI StatesI State transitions

I Graph representationI States as verticesI States transitions as edgesI Quite intuitive when the system is small (tens of states or a

few bits of states)

I Functional representationI Define a current state for the machineI Represent next state and the outputs as functions of the

current state and inputsI Able to handle extremely large systems (how many states are

there in your computer?)

ECE 429 – Introduction to VLSI Design Spring 2018 5/16

Implementing FSMs as Sequential Circuits

I Implement the functional representation of FSMI Store the current state in the sequential elementsI The next state and the outputs are computed through

combinational circuitsI Also known as register transfer level (RTL)

I Synchronous circuit: a clock is introducedI Exact one state transition happens per clock cycleI Also known as cycle-accurate behavior

ECE 429 – Introduction to VLSI Design Spring 2018 6/16

Flip-Flops as Sequential Elements

I What is the desired functionality of the sequential elementsfor synchronous circuits?

I During the clock cycle, hold and provide the current state tothe combinational circuits to compute the next state and theoutputs

I At the end of the clock cycle (a time point), load thecomputed next state

I (Ideal) (Edge-triggered) Flip-flopsI Three terminals: input D, output Q, clock CLKI When the clock CLK turns from ‘0’ to ‘1’ (positive/rising

edge), the input D is loaded into the flip-flopI The loaded value is available at the output Q just after the

rising edge, and will stay there until the next rising edge comes.

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Timing for Ideal Flip-Flops

I Computing the next state and the output takes timeI We need to consider timing of combinational circuits

I Let the clock period be Tc

I Let the longest path (propagation) delay of the combinationalpaths be tpd

I Of all the paths computing the next state and the output

I The condition: tpd ≤ Tc

I Ensure the computation of the next state finises before thenext rising edge

I Same constraint applies to the output so you can connectmultiple sequential circuits driven by the same clock togetherdirectly.

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Outline

Overview: FSM and Ideal Flip-Flops

Setup Condition and Hold Condition

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Bistability and Metastability

(Fig. 10.42, Weste and Harris)

I Ideally, one flip-flop stores 1 bit of state, either ‘0’ or ‘1’I Feedbacks are necessary to compete with noise and leakageI Stable states: after small perturbations, the ball will return

back to the current positionI Bistability: 2 stable states, one for ‘0’, one for ‘1’

I However, feedbacks will result in Metastable stateI Any perturbation will cause the ball to move away from the

current positionI Not good for state storage because the state is unpredictable

ECE 429 – Introduction to VLSI Design Spring 2018 10/16

Bistability and Metastability

(Fig. 10.42, Weste and Harris)

I Ideally, one flip-flop stores 1 bit of state, either ‘0’ or ‘1’I Feedbacks are necessary to compete with noise and leakageI Stable states: after small perturbations, the ball will return

back to the current positionI Bistability: 2 stable states, one for ‘0’, one for ‘1’

I However, feedbacks will result in Metastable stateI Any perturbation will cause the ball to move away from the

current positionI Not good for state storage because the state is unpredictable

ECE 429 – Introduction to VLSI Design Spring 2018 10/16

Setup Time and Hold Time

I Flip-flops enter the metastable state only if the input D andthe rising clock edge come almost at the same time

I To avoid the metastable state, input D should be kept stablewhen the rising edge comes

I Setup time tsetupI Input D must have settled by tsetup time before the rising edgeI Known as setup condition or max-delay constraints

I Hold time tholdI Input D should not change until thold time after the rising edgeI Known as hold condition or min-delay constraints

ECE 429 – Introduction to VLSI Design Spring 2018 11/16

Setup Time and Hold Time

I Flip-flops enter the metastable state only if the input D andthe rising clock edge come almost at the same time

I To avoid the metastable state, input D should be kept stablewhen the rising edge comes

I Setup time tsetupI Input D must have settled by tsetup time before the rising edgeI Known as setup condition or max-delay constraints

I Hold time tholdI Input D should not change until thold time after the rising edgeI Known as hold condition or min-delay constraints

ECE 429 – Introduction to VLSI Design Spring 2018 11/16

Setup Time and Hold Time

I Flip-flops enter the metastable state only if the input D andthe rising clock edge come almost at the same time

I To avoid the metastable state, input D should be kept stablewhen the rising edge comes

I Setup time tsetupI Input D must have settled by tsetup time before the rising edgeI Known as setup condition or max-delay constraints

I Hold time tholdI Input D should not change until thold time after the rising edgeI Known as hold condition or min-delay constraints

ECE 429 – Introduction to VLSI Design Spring 2018 11/16

Setup Time and Hold Time

I Flip-flops enter the metastable state only if the input D andthe rising clock edge come almost at the same time

I To avoid the metastable state, input D should be kept stablewhen the rising edge comes

I Setup time tsetupI Input D must have settled by tsetup time before the rising edgeI Known as setup condition or max-delay constraints

I Hold time tholdI Input D should not change until thold time after the rising edgeI Known as hold condition or min-delay constraints

ECE 429 – Introduction to VLSI Design Spring 2018 11/16

Handle Setup and Hold Conditions

(Fig. 10.4, Weste and Harris)

I tpd : the longest path (propagation) delay of thecombinational paths

I tcd : the shortest path (contamination) delay of thecombinational paths

I The signal at the flip-flop input D is guaranteed to be stablesince tpd time in the current clock cycle until tcd time in thenext clock cycle

I We need to modify the condition tpd ≤ Tc to include setupand hold conditions

ECE 429 – Introduction to VLSI Design Spring 2018 12/16

Handle Setup and Hold Conditions

(Fig. 10.4, Weste and Harris)

I tpd : the longest path (propagation) delay of thecombinational paths

I tcd : the shortest path (contamination) delay of thecombinational paths

I The signal at the flip-flop input D is guaranteed to be stablesince tpd time in the current clock cycle until tcd time in thenext clock cycle

I We need to modify the condition tpd ≤ Tc to include setupand hold conditions

ECE 429 – Introduction to VLSI Design Spring 2018 12/16

Handle Setup and Hold Conditions

(Fig. 10.4, Weste and Harris)

I tpd : the longest path (propagation) delay of thecombinational paths

I tcd : the shortest path (contamination) delay of thecombinational paths

I The signal at the flip-flop input D is guaranteed to be stablesince tpd time in the current clock cycle until tcd time in thenext clock cycle

I We need to modify the condition tpd ≤ Tc to include setupand hold conditions

ECE 429 – Introduction to VLSI Design Spring 2018 12/16

Intrinsic Delays for Flip-Flops

(Fig. 10.4, Weste and Harris)

I The state of the flip-flop is not immediately available at theoutput Q

I tccq: clock-to-Q contamination delayI Output Q is stable and provides the previous state before tccq

time of the rising edge

I tpcq: clock-to-Q propagation delayI Output Q is stable and provides the current state after tpcq

time of the rising edge

ECE 429 – Introduction to VLSI Design Spring 2018 13/16

Intrinsic Delays for Flip-Flops

(Fig. 10.4, Weste and Harris)

I The state of the flip-flop is not immediately available at theoutput Q

I tccq: clock-to-Q contamination delayI Output Q is stable and provides the previous state before tccq

time of the rising edge

I tpcq: clock-to-Q propagation delayI Output Q is stable and provides the current state after tpcq

time of the rising edge

ECE 429 – Introduction to VLSI Design Spring 2018 13/16

Intrinsic Delays for Flip-Flops

(Fig. 10.4, Weste and Harris)

I The state of the flip-flop is not immediately available at theoutput Q

I tccq: clock-to-Q contamination delayI Output Q is stable and provides the previous state before tccq

time of the rising edge

I tpcq: clock-to-Q propagation delayI Output Q is stable and provides the current state after tpcq

time of the rising edge

ECE 429 – Introduction to VLSI Design Spring 2018 13/16

Setup Condition for Flip-Flops

(Weste and Harris)

I tpcq + tpd + tsetup ≤ Tc

I Ideally tpcq = tsetup = 0

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Setup Condition for Flip-Flops

(Weste and Harris)

I tpcq + tpd + tsetup ≤ Tc

I Ideally tpcq = tsetup = 0

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Hold Condition for Flip-Flops

(Weste and Harris)

I tccq + tcd ≥ tholdI Ideally tccq = thold = 0 and tcd is always not negative

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Hold Condition for Flip-Flops

(Weste and Harris)

I tccq + tcd ≥ tholdI Ideally tccq = thold = 0 and tcd is always not negative

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Summary

I Setup condition and hold condition

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