ECE 4110–5110 Digital System Design
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Lecture #31 Page 1 ECE 4110–5110 Digital System Design Lecture #31 • Agenda 1. von Neumann Stored Program Computer Architecture • Announcements 1. N/A.
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ECE 4110–5110 Digital System Design. Lecture #31 Agenda von Neumann Stored Program Computer Architecture Announcements 1.N/A. von Neumann Computer. - PowerPoint PPT Presentation
Transcript of ECE 4110–5110 Digital System Design
Lecture #31Page 1
ECE 4110–5110 Digital System Design
Lecture #31
• Agenda
1. von Neumann Stored Program Computer Architecture
• Announcements
1. N/A.
Lecture #31Page 2
von Neumann Computer
• Register Loads
- each register in the processing unit can be loaded by the control unit
- the input to most registers is Bus2
- the CCR input is the ALU
- the loads are synchronous to clock and occur on the following state
- we can make a register in RTL as follows:
MAR_Register : process (Clock, Reset) begin
if (Reset = '0') then MAR <= "0000";
elsif (Clock'event and Clock='1') then if (MAR_Load = '1') then MAR <= Bus2;
end if; end if;
end process;
Lecture #31Page 3
von Neumann Computer
• Control Signals
- the Bus1 and Bus2 control lines come from the control unit and drive the multiplexers
- the WRITE line is a synchronous load to memory from Memory_Out
- CCR_Load will load the status bits (NZVC), whose values depend on the previous ALU operation
- the ALU_Sel line tells the ALU which function to perform (AND, ADD, …)
• Test Signals
- the Instruction Register (IR) holds the Opcode for the Control Unit to base state decisions on
- the CCR_Result is the NZVC status bits from an ALU operation and influence state decisions
Control Unit Sub-Operations
• Fetch
– Get next instruction into IR
– PC: program counter, always points to next instruction
– IR: holds the fetched instruction
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
I/O
Control/Status
load X, 100
123101
ADD X, Y102
MAR
Y
100 load X,
Lecture #31Page 4
X
4
Control Unit Sub-Operations
• Decode
– Determine what the instruction means
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X,100
123101
ADD X,Y102
MAR X100 load X,
Lecture #31Page 5
Y4
Control Unit Sub-Operations
• Fetch operands
– Move data from memory to data-path register
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X,100
123101
ADD X,Y102
MAR X100 load X,
123
Lecture #31Page 6
Y
101
4
Control Unit Sub-Operations
• Execute
– Move data through the ALU
– This particular instruction does nothing during this sub-operation
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X, 100
123101
ADD X,Y102
MAR X100 load X,
Lecture #31Page 7
Y123
4
Control Unit Sub-Operations
• Store results
– Write data from register to memory
– This particular instruction does nothing during this sub-operation
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X,100
123101
ADD X,Y102
MAR X100 load X,
Lecture #31Page 8
Y4
123
Lecture #31Page 9
Control Unit Sub-Operations
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X,100
123101
ADD X,Y102
MAR X
Y
PC=100
100
4
123
Lecture #31Page 10
Instruction Cycles
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X,100
123101
ADD X,Y102
MAR X
Y123
PC=100
PC=101
101
4
Lecture #31Page 11
Instruction Cycles
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X,100
123101
ADD X,Y102
MAR X
Y127
PC=100
PC=101
102
4
PC=102
Lecture #31Page 12
Instruction Cycles
Processor
Control unit Datapath
ALU
Registers
IRPC
Controller
Memory
I/O
Control/Status
load X,100
123101
ADD X,Y102
MAR X
Y127
PC=100
PC=101
102
4
PC=102
Lecture #31Page 13
von Neumann Computer (again)
• CPU
1) Control Unit2) Processing Unit3) Control Signals4) Test Signals
Lecture #31Page 14
von Neumann Computer
• Instruction Execution
State 0
- put the current Program Counter value on the Memory Address Bus to read the first Opcode
RTL: MAR <= PC
Control: Bus1_Sel = PC Bus2_Sel = Bus1 MAR_Load
State 1
- bring in the contents of memory (the Opcode) and put into the IR- increment PC to point at either the Operand or next Opcode in memory
RTL: IR <= Memory_Out PC = PC + 1
Control: Bus2_Sel = Memory_Out IR_Load PC_Inc
Lecture #31Page 15
von Neumann Computer
• Instruction Execution
State 2
- the Control Unit now decodes IR
- this dictates the next state and which control signals are asserted
(IR = ADD_XY) (IR = LDX_IMM)
RTL: Z <= X RTL: MAR <= PC
Control: Bus1_Sel = X Control: Bus1_Sel = PC Bus2_Sel = Bus1 Bus2_Sel = Bus1 Z_Load MAR_Load
State 3
RTL: ALU = ADD RTL: X <= Memory_Out
Control: Bus1_Sel = Y Control: Bus2_Sel = Memory_Out Bus2_Sel = ALU X_Load ALU_Sel = ADD PC_Inc X_Load CCR_Load
