ECE 3401 Lecture 25 Review - School of...
Transcript of ECE 3401 Lecture 25 Review - School of...
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ECE 3401 Lecture 25!!
Review!!
Control State Register
Combinational Control Logic
New/ Modified Control Word
ISA: Instruction Specifications (for reference)
I n st ruction Speci fications for the Simple Comput er - Part 1 Instr u ctio n O pc ode Mnem on ic Form a t D escrip tion
St a t u s Bits Move A 0000000 MO V A RD ,RA R [DR] ← R[SA ] N , Z Increment 0000001 INC R D , RA R[DR] ← R [ SA] + 1 N , Z Add 0000010 ADD R D , RA,RB R [DR] ← R[SA ] + R[ SB] N , Z Subtr a ct 0000101 SUB R D , RA,RB R [DR] ← R[SA ] - [ SB] N , Z D e crement 0000110 DEC R D , RA R[DR] ← R[SA ] - 1 N , Z AND 0001000 AND R D , RA,RB R [DR] ← R[SA ] ∧ R[SB ] N , Z O R 0001001 OR RD ,RA,RB R[DR] ← R[SA ] ∨ R[SB ] N , Z Exclusive OR 0001010 XOR R D , RA,RB R [DR] ← R[SA ] ⊕ R[SB] N , Z NO T 0001011 NO T R D , RA R[DR] ← N, Z R[SA ]
R
I n st ruction Speci fications for the Simple Comput er - Part 2 Instr u ctio n O pc ode Mnem on ic Form a t D escrip tion
St a t u s Bits Move B 0001100 MO VB RD ,RB R [DR] ← R[SB] Shift Right 0001101 SHR R D , RB R[DR] ← sr R[SB] Shift Left 0001110 SHL R D , RB R[DR] ← sl R[SB] Load Imm e diate 1001100 LDI R D , O P R[DR] ← zf OP Add Immediate 1000010 ADI R D , RA,OP R [DR] ← R[SA] + zf OP Load 0010000 LD RD ,RA R [DR] ← M[ SA ] Store 0100000 ST RA,RB M [SA] ← R[SB] Branch on Zero 1100000 BRZ R A,AD if (R[ S A] = 0) PC ← PC + s e A D Branch on Negative 1100001 BRN R A,AD if (R[ S A] < 0) PC ← PC + s e A D J u mp 1110000 JMP R A P C ← R[SA ]
P C P C + 1
+ R [ S B ] + 1
R [ D R ] R [ S A ]
v!
R [ S B ]
R [ D R ] R [ S A ]
R [ D R ] R [ S A ]
+ R [ S B ]
R [ D R ] R [ S A ]
–
1 R [ D R ] R [ S A ]
R [ S B ]
R [ D R ] R [ S A ]
R [ S B ]
R [ D R ] R [ S A ]
0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1
0 0 0 0 0 0 0
O p c o d e
E X 0
I N F
R [ D R ] R [ S A ]
←
+ 1 R [ D R ] R [ S A ] ←
←
∧←
I R M [ P C ] ←
←
←
←
←
←
←
+
0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 0 0 1 1 0 0
R [ D R ] R [ S B ] ←
+ se AD PC PC ←
PC R [ S A ] ←
R [ D R ] zf OP ←
[ ] R [ D R ] R [ S A ] ← M
R [ S B ] ← [ ] R [ S A ] M
R [ D R ] R [ S A ] ← + zf OP
0
0
1
1
Z
N
To INF
PC<-PC+1
State Table for 2-Cycle Instructions
S t a t e I n p u t s N e x t s t a t e
O u t p u t s C o m m e n t s O p c o d e V C N Z
I L P S D X A X B X
M B F S M D
R W M M
M W I N F X X X X X X X X X X X EX0 1 00 X X X X X X X X X X X X X X X X X X 0 1 0 I R ←
M [ PC ] E X 0 0 000000 X X X X INF 0 01 0 X X X 0 X X X X X X X X 0000 0 1 X 0 M O V A R [DR ] ← R [SA]* E X 0 0 000001 X X X X INF 0 01 0 X X X 0 X X X X X X X X 0001 0 1 X 0 I N C R [DR ] ← R [S A ] + 1*
E X 0 0 000010 X X X X INF 0 01 0 X X X 0 X X X 0 X X X 0 0010 0 1 X 0 A D D R [DR ] ← R [S A ] + R [S B ]* E X 0 0 000101 X X X X INF 0 01 0 X X X 0 X X X 0 X X X 0 0101 0 1 X 0 S U B R [DR } ← R [S A ] + + 1* E X 0 0 000110 X X X X INF 0 01 0 X X X 0 X X X X X X X X 0110 0 1 X 0 D E C R [DR ] ← R [S A ] + ( - 1) * E X 0 0 001000 X X X X INF 0 01 0 X X X 0 X X X 0 X X X 0 1000 0 1 X 0 A N D R [DR ] ← R [SA] ̂ R [S B ]* E X 0 0 001001 X X X X INF 0 01 0 X X X 0 X X X 0 X X X 0 1001 0 1 X 0 O R R [DR ] ← R [SA] v!R [S B ]* E X 0 0 001010 X X X X INF 0 01 0 X X X 0 X X X 0 X X X 0 1010 0 1 X 0 X O R R [DR ] ← R [SA] R [S B ]* E X 0 0 001011 X X X X INF 0 01 0 X X X 0 X X X X X X X X 1011 0 1 X 0 N O T R [DR ] ← * E X 0 0 001100 X X X X INF 0 01 0 X X X X X X X 0 X X X 0 1100 0 1 X 0 M O V B R [DR ] ← R [S B ]* E X 0 0 010000 X X X X INF 0 01 0 X X X 0 X X X X X X X X X X X X 1 1 0 0 L D R [DR ] ← M [ R [SA]]* E X 0 0 100000 X X X X INF 0 01 X X X X 0 X X X 0 X X X 0 X X X X X 0 0 1 S T M [ R [SA]] ← R [S B ]* E X 0 1 001100 X X X X INF 0 01 0 X X X X X X X X X X X 1 1100 0 1 0 0 LDI R [DR ] ← z f OP * E X 0 1 000010 X X X X INF 0 01 0 X X X 0 X X X X X X X 1 0010 0 1 0 0 ADI R [DR ] ← R [S A ] + z f OP * E X 0 1 100000 X X X 1 I N F 0 1 0 X X X X 0 X X X X X X X X 0000 X 0 0 0 B R Z PC ← PC + s e A D E X 0 1 100000 X X X 0 I N F 0 0 1 X X X X 0 X X X X X X X X 0000 X 0 0 0 B R Z PC ← PC + 1 E X 0 1 100001 X X 1 X INF 0 10 X X X X 0 X X X X X X X X 0000 X 0 0 0 B R N PC ← PC + s e A D E X 0 1 100001 X X 0 X INF 0 01 X X X X 0 X X X X X X X X 0000 X 0 0 0 B R N PC ← PC + 1 E X 0 1 110000 X X X X INF 0 11 X X X X 0 X X X X X X X X 0000 X 0 0 0 J M P PC ← R [S A ]
R S B [ ]
R S A [ ] +
* For this state and input combinations, PC ß PC+1 also occurs
Control Unit ----------------------------------- -- controller -- ----------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity controller is Port (clk : in std_logic;
opcode : in std_logic_vector(6 downto 0); reset : in std_logic; carry : in std_logic; neg : in std_logic; zero : in std_logic; overflw : in std_logic; IL : out std_logic; PS : out std_logic_vector(1 downto 0); DX : out std_logic_vector(3 downto 0); AX : out std_logic_vector(3 downto 0); BX : out std_logic_vector(3 downto 0); FS : out std_logic_vector(3 downto 0); MB : out std_logic; MD : out std_logic; RW : out std_logic; MM: out std_logic; MW: out std_logic)
end controller; architecture Behavioral of controller is type state_type is (RES, INF, EX0); attribute enum_encoding : string; attribute enum_encoding of state_type : type is “0001 0010 0100"; signal cur_state, next_state : state_type; begin
state_register: process(clk, reset) begin if(reset='1') then cur_state<=RES; elsif (clk'event and clk='1') then cur_state<=next_state; end if; end process;
out_func: process (cur_state, opcode, carry, zero, neg, overflw ) begin (IL, PS, MB, MD, RW, MM, MW) <= std_logic_vector'(“00000000"); (DX, AX, BX)<=std_logic_vector’(X“000”); FS<=“0000"; case cur_state is
when RES => next_state <= INF; when INF => next_state<=EX0; MM <= ’1’; IL <= ‘1’; when EX0 => next_state<= INF; case opcode is when “0000000" => PS <= “01”; RW <= ‘1’; when “0000001” => PS <= “01”; RW <= ‘1’; FS <= “0001”; ……….. when “1100000” => if (zero = ‘1’) then PS <= “10”; else PS <= “01”; end if;
……….. when others=> report "Unrecognizable state" severity error; end case;
end case; end process; end Behavioral;
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Final Exam
§ May 6th (Tuesday), 10:30am-12:30pm, ITE 127
§ Open-book, open-notes, and open-homework § No cell phones, PDAs, or any other electronic
devices except calculators § Scope
• Lectures 11-24 • Homeworks 3-5
§ Final project is due at 3pm on May 10 (FIRM)
Final Exam
§ Topics • Sequential logic design
• Finite State Machines, Storage/memory
• Controller design – hardwired or micro-programmed (ASM)
• VHDL coding
• Pipelining
• Floating point arithmetic
Final Exam – Focal Points
§ ASM chart and description, conversion between ASM and FSM
§ IEEE single-precision FP binary to decimal conversion § Basic concept of pipelining, the five stages of a processor
pipeline, the function of each stage § Convert a non-pipelined datapath to pipelined datapath,
analyze different timing requirements (consider register setup time, propagation delay of register and combinational circuits, hold time, the limit on circuit frequency)
§ True/False questions: compare FPGA with custom VLSI design, pipelined latency and throughput, difference between simulatable and synthesizable design, SRAM/DRAM difference, etc.
Where do you go from here?
§ Undergraduate study • Digital Design Lab (ECE4401)
• VLSI Design (ECE3421)
• Microprocessor Lab (ECE3411/CSE4903)
• Computer Architecture (CSE 3666/CSE 4302)
• Undergraduate Research Project
• Senior Design
Where do you go from here?
§ Graduate study • Advanced VLSI design (ECE 6421) • VLSI CAD algorithms (ECE 6095) • Computer architecture • High performance computing • Computer security (GAANN fellowship) • Hardware Security and Trust • VLSI Design Verification and Test (ECE 6432)
§ Jobs • Embedded design
§ Just about any industrial product manufacturer § From automobiles to toasters § Honeywell, BAE Systems. LMI, Toyota, GM, GE, etc.
• High-performance chip design § Intel, IBM, AMD, Motorola
• EDA § Cadence, Synopsys, Mentor Graphics
• Aim high!
Where do you go from here?
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Where do you go from here?
§ Get more experience!! • Work with faculty • Get involved in more research • Try to work on larger projects • Take a couple of graduate courses
§ Check out opencores.org § Design your own boards
• Development boards from § Xilinx § Digilent (www.digilentinc.com)
• Excellent platform to allow you implement your ideas
VLSI Design Automation
§ Large number of components § Optimize requirements for higher performance
• Performance relates to speed, power and size. § Time to market competition § Cost
• Using computer makes it cheaper by reducing time-to-market.
System Specifications Chip
Manual
Automation
VLSI Design Cycle
System Specifications
Functional Design
Logic Design
Circuit Design
X=(AB*CD)+ …
Layout
VLSI Design Cycle
Physical Design
Fabrication
Packaging
IC Test
Semiconductor Processing
• How do we make a transistor?
• How do you control where the features get placed? n Photo lithography masks
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Wafer Processing Intel 4004
• First microprocessor • Designed in 1971 • 2300 transistors • 10-um process • ~100 KHz
Intel Itanium Processor
• Released in 2005 • 1.72 Billion
transistors • 90-nm process • 2 GHz
Testing Principle
Digital Circuit
1 1 0 1 0
0 1 1 1 0
0 0 0 0 1
1 0 0 1 0
1 1 0 0 0
1 0 1 1 1
Input Patterns Output Patterns
Stored Correct
Response
Comparator
Test Result
Functional Test Method – Not very efficient
ADVANTEST Model T6682 ATE
Test Head
Testers are very expensive ($150K – $20M)