ECE 314/514: Digital VLSI Design
Transcript of ECE 314/514: Digital VLSI Design
![Page 1: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/1.jpg)
ECE 314/514: Digital VLSI Design
Instructor: Sujay Deb
Meeting: Mon 11:00 AM & Wed 9:30 AM @ C03
![Page 2: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/2.jpg)
Before we start..
Please answer following questions: Please state your expectations from this course?
How will this course help you in achieving your goals?
![Page 3: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/3.jpg)
Goal of the Course
Learn the principles of VLSI Design Learn to design and implement state-of-the-art digital
Very Large Scale Integrated (VLSI) chips using CMOS technology
Understand the complete design flow
Be able to design state-of-the-art CMOS chips in industry
Employ hierarchical design methods Use integrated circuit cells as building blocks
Understand design issues at the layout, transistor, logic and register-transfer levels
Use commercial design software in the lab
![Page 4: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/4.jpg)
Course Information
Instructor: Sujay Deb ([email protected]) Office A304 (Office Hours: Mon and Wed 4-5 PM)
TA: Hemanta Kumar Mondal ([email protected] )
More on the course Course web page: We will use PIAZZA for everything! Sign up:
https://piazza.com/iiitd.ac.in/fall2014/ece314514/home Prerequisites: logic design, basic computer organization Textbook: Weste and Harris, CMOS VLSI Design: A Circuits
and Systems Perspective, 3rd Edition, 2006 Lectures and discussion in class will cover basics of course Homework, Laboratory exercise will help you gain a deep
understanding of the subject
![Page 5: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/5.jpg)
Grading structure
Homework: 5%
Reading Assignment: 5%
Quiz: 5%
Midterm: 25%
Lab Assignments: 15%
Term project: 20%
Final: 25%
Problems will be too long to complete the night before due, so please plan accordingly.
Students are expected to work individually on the homework assignments.
The lab assignments and project can be done in a group of two.
Zero tolerance towards violation of Academic Integrity
HW#0: Join PIAZZA and explore it!
![Page 6: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/6.jpg)
Overview
What is Engineering? – the purposeful use of science
We are here to employ the facts of nature to build very interesting systems
Take complicated things, build layers of abstraction, and simplify things so that we can build useful systems.
Observations Nature Engineering
Systems Abstractions
![Page 7: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/7.jpg)
Design Abstraction Levels
n+ n+
S
G D
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
![Page 8: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/8.jpg)
Course outline
Introduction to CMOS circuits
MOS transistor theory
Circuit Characterization Performance evaluation & optimization
CMOS circuit logic and design
Subsystem design
Datapath design and analysis
![Page 9: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/9.jpg)
Solid State Devices
Silicon Doping
n-type, p-type silicon Carriers
electrons and holes
P-N junctions 2 terminal devices
Transistors Bipolar Junction Transistors (BJT) Metal Oxide Semiconductor (MOS)
4 terminal devices Main emphasis of this class
History is very important. Do visit http://smithsonianchips.si.edu/ and explore other related resources
Reading Assignment #1: Submit a report on ‘Future of transistor and microprocessors’ by 11/08. Details on Piazza.
![Page 10: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/10.jpg)
Integrated circuits
nMOS and pMOS devices
Modeled as on-off switches But a lot goes on inside!
Complementary MOS (CMOS) circuit design methodology Most common and widely used technique
But several other interesting techniques exist
![Page 11: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/11.jpg)
Moore’s Law
http://www.intel.com/content/www/us/en/silicon-innovations/moores-law-technology.html
Courtesy:
![Page 12: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/12.jpg)
Moore’s Law continued..
Number of components in an integrated circuit double every 2 years
Signifies increase in computing capacity, memory and speed exponentially
![Page 13: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/13.jpg)
Moore’s law in Microprocessors
4004 8008
8080 8085 8086
286 386
486 Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010 Year
Tran
sist
ors
(M
T)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 years
Courtesy, Intel
![Page 14: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/14.jpg)
MOS structure
n-channel
p-channel
![Page 15: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/15.jpg)
Technology nodes
Scaling 0.25um,0.18um,90nm,65nm,45nm,32nm, 22nm,
14nm…
![Page 16: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/16.jpg)
Frequency
P6
Pentium ® proc 486
386 286 8086 8085
8080
8008 4004
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Fre
qu
en
cy (
Mh
z)
Lead Microprocessors frequency doubles every 2 years
Doubles every
2 years
Courtesy, Intel
![Page 17: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/17.jpg)
Power Dissipation
P6 Pentium ® proc
486
386 286 8086
8085 8080
8008 4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000
Year
Po
we
r (W
atts
)
Lead Microprocessors power continues to increase
Courtesy, Intel
![Page 18: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/18.jpg)
Power will be a major problem
5KW 18KW
1.5KW
500W
4004 8008
8080 8085
8086 286
386 486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008
Year
Po
we
r (W
atts
)
Power delivery and dissipation will be prohibitive
Courtesy, Intel
![Page 19: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/19.jpg)
Power density
4004 8008
8080 8085
8086
286 386
486 Pentium® proc
P6
1
10
100
1000
10000
1970 1980 1990 2000 2010
Year
Po
we
r D
en
sity
(W
/cm
2)
Hot Plate
Nuclear
Reactor
Rocket
Nozzle
Power density too high to keep junctions at low temp
Courtesy, Intel
![Page 20: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/20.jpg)
Current Computing Capabilities
Intel’s 80-core processor: ~Terra flops
Over a billion transistors per chip
4-5 GHz chip clock
![Page 21: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/21.jpg)
The era of Many-Core systems
How to keep up with demands on computational power?
Can not scale clock frequency
Solution: Increase number of cores - parallelism
Mass Market production of Intel, AMD dual-core and quad-core CPUs
Custom Systems-on-Chip (SoCs)
Many Core chips from Tilera for networking, cloud computing and multimedia applications.
‘Number of cores will double every 18 months’
- Prof. A. Agarwal, MIT, founder of Tilera Corporation
Adapteva’s
Epiphany
Single-chip
Cloud
Computer Intel 80 core
processor
![Page 22: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/22.jpg)
oWe are at the early stage of Many-core Processor evolution
• Many-core is going to be ubiquitous
o Immense possibilities: •Server-type performance on handheld devices
The era of Many-Core systems
![Page 23: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/23.jpg)
Issues and challenges of VLSI today
High Power dissipation
Faster operation
Methodologies to address these issues
![Page 24: ECE 314/514: Digital VLSI Design](https://reader031.fdocuments.us/reader031/viewer/2022012508/6184f565c1eb303a9109a7a1/html5/thumbnails/24.jpg)
Looking ahead
CMOS technology Stable and well understood process
Future technologies Nano devices
Molecular devices
Single electron devices
Quantum dots
Many more…
The future is basically yours to invent!