Allan Guan

ECE 3130 – Digital Electronics and Design

Lab 5Latches and Flip-Flops

Fall 2012

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What are latches and flip-flops?

• Sequential circuits that store information (i.e. memory elements – output depends not only on present inputs but also previous inputs)

• Latches – output responds to input immediately as long as the enable signal is asserted

• Flip flops – output responds only to the rising and falling edge of the enable signal

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Today’s lab

• Build and test an SR latch from NAND gates• Build an test a D latch from the SR latch• Build and test a DFF from the D latch– Master-slave implementation (MS)– Positive gate trigger implementation (PGT)

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SR Latch

Truth Table NAND Implementation

The inputs are active-low (hence the bar on top of S and R).This means that the output will change when the input is pulsed low.The latch is set (that is, storing logic 1) when Q = 1 and nQ = 0.The latch is reset (that is, storing logic 0) when Q = 0 and nQ = 1.

State nS nR Q nQ

Rest 1 1 0 1

Set 0 1 1 0

Set 1 1 1 0

Reset 1 0 0 1

Reset 1 1 0 1

Undefined 0 0 1 1

Undefined 1 1 ? ?

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Can you make an SR Latch from NOR Gates?

• Show step-by-step procedure how to replace NAND gates with NOR gates.

• Do the inputs/outputs remain the same?

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Output Waveforms for SR Latch (NAND Implementation)

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D Flip-Flop

Truth TableClock D Qn Qn+1

0 X 0 0

0 X 1 1

1 0 X 0

1 1 X 1

SR Latch Implementation

This is an SR latch!

The output follows D as long as the Clock signal is 1.Otherwise, it holds its value.

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Output Waveforms for D Latch

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D Flip-Flop (DFF)

• The value of D is stored on either the rising or falling clock edge.

• The figure below shows a positive-edge triggered DFF.

Clock

D

Q

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Master-Slave DFF

The “slave” DFF only changes when the “master” DFF changes.The “slave” DFF clock is inverted, hence, this is negative-edge triggered.For positive-edge triggering, switch the clock inputs between the “master” and the “slave”.

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Output Waveforms for Master-Slave DFF (Negative-Edge Triggered)

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PGT Schematic

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PGT Waveforms

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Can you explain the output waveform of the PGT?

• Why did we use an odd number of inverters to make a PGT?

• Could we have used an even number of inverters and replaced the AND gate by NOR, NAND, or OR gates to obtain a similar output?

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PGT-Driven DFF Schematic

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PGT-Driven DFF Waveforms

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Analysis

• Include output waveforms for all the circuits in today’s lab in your report.

• So far, you have seen that you obtain glitches or peaks in your output during transition of input from one state to another. After doing this lab, can you suggest a way to get rid of those glitches and peaks?

• Keeping the above question in mind can you state one probable use of D flip flops in digital circuits?