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ECAD VLSI LAB

IV-1st SEM

Experiment booklet

Unistring Tech Solutions Pvt Ltd.

H.NO: 16-11-741/16,FLAT NO: 101, First floor, Above Reliance fresh,

Dilshuknagar, Hyderabad, Email: info@unistring.com

www.unistring.com

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NOTE

(1) Please do not use long path names, for creating your projects. The suggested director

structure is in one of the drives you create a folder with name VLSI lab, and create a sub directory in it with your name. Path names with spaces and special characteristics shall give problems in using Electric VLSI system design tool and LTSPICE tool

(2) Please ensure that the C drive has enough disk space, preferably more than 1 GB so that

tools work fast enough. (3) Let the model files are at one single folder and in all SPICE scripts we can refer to the

same. Ensure that this path also doesn’t have any spaces and special characteristics.

(4) Do not change the color settings of the Electric; if it is not done carefully the results are unexpected.

(5) Keyboard short cuts for Electric are given in Appendix-C.

(6) Contact support@unistring.com for any help pertaining to the experiments given in this book.

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Contents

Module - 1 Using Electric VLSI design system tool for schematic and layout entry Module - 2 Using LT-SPICE for simulation Module - 3 MoS inverter DC Characteristics, AC Characteristics, Transient Analysis. Module - 4 Schematic, layout, DRC, LVS and post layout simulation for the following a. NMOS, PMOS Characteristics. b. Layout basics- INV, NAND, NOR, EXOR, EXNOR. c. Layout of adder, subtractor, multiplexer. d. Layout Comparator. Appendix-A Model files Appendix-B MOSIS 7.2 design rules Appendix-C Electric tool keyboard shortcuts

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Module 1

Using Electric VLSI design system tool for

schematic and layout entry

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Using Electric VLSI design system tool for Schematic and layout entry

Aim: To learn the Electric VLSI design system tool for creating schematics and layouts. Experiment procedure:

(1) Launch the Electric VLSI design system tool version 8.5 by double clicking

the desktop Electric short cut. In case if the icon is missing on desktop

then look for electric in folder c:\electric_jar.

(2) The Electric software must open as below.

(3) We can observe the library browser on the left and message window at

the bottom. We will continuously look at the message window to observe

the output after every step.

(4) There are some initial settings required to be done before we start working

with this tool.

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(5) Open file > preferences and set for model file path in the ‘use header

cards from file” option. Browse to the model file which is in the electric

installation folder by name t55u_lo_epi-params.txt. This is 180 nm model

file which we shall use for simulation. We can leave the options to

defaults.

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(6) Go to File > project settings Set the transistor scale to (λ value) 90 nm as

shown below.

(7) The above settings we need to set only once.

(8) Click File > new library to create new library. Enter the library name as

inverter. Observe the message window showing the new library is

created. See that the library is saved in the appropriate directory. If you

want to put in a different directory then use option File > save library as.

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Schematic entry (9) Click on cell > new cell, choose schematic option as below.

(10) Observe the library browser changes to schametic symbols on the left

side.

(11) The required components for building inverter are shown in above figure.

NMOS

PMOS

VCC

GND

port

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(12) Drag and drop the NMOS, PMOS, VCC, GND and port as shown in

below figure.

(13) To connect two nodes we need to left click on first node and right click on

second node.

(14) Notice that when mouse is moved on the ports of components white color

cross hair ( + symbol) gets highlighted. To initiate the connection we have

to left click on it and right click on another highlighted cross hair.

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(15) In schematic (not in case of layout which we will see later) the nodes

drain and source for MOS are fixed, so we need to ensure that circuit is

correctly connected. When we click on the node of NMOS (cross hair )

the status bar shows the port, as shown in below figure.

(16) Use CNTL+J option to rotate the MOS transistors such that both the

drains are shorted and become output node. Similarly make other

connections so that the circuit completes as below.

s indicates source

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(17) Change the transistor width to 3 units (3 lambda) for both PMOS and

NMOS. Double click on the MOS transistor to open the window.

(18) Export the in and out ports by selecting and pressing CNTL+E. give

names in and out respectively. Ensure that we select input and output for

export characteristics for in and out ports.

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(19) Note that the Vdd and gnd symbols automatically attached to the

respective symbols, hence no need to export them. The finished circuit

must be as below.

(20) To generate the spice script click on tool > simulation (spice) > write

spice deck

(21) Choose appropriate name and folder for the design. Open the file we

shall see the NMOS and PMOS are described in SPICE netlist format.

(22) In next module we shall see the simulation of this script using SPICE tool.

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Layout entry

(23) Click on cell > new cell, choose layout option as shown below.

(24) You can notice that the left side browser shows all the basic components

in the components tab.

(25) Click on the bottom right most NMOS array button. Then choose N-

transistor as shown below.

(26) You can drop the N transistor in the cell window.

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(27) Similarly bring the P transistor from the PMOS and drop in the cell

window.

(28) Select the NMOS and rotate it by pressing CNTL + J. More keyboard

short cuts are given in Appendix-C. Notice that the selected transistor will

be in highlighted in white color at the boundary. Notice the unselected

(left side) and selected (right side) NMOS.

(29) Use CNTL+9 to fit the design to the window.

(30) Place them at an approximate distance as shown in below figure. Note

that the green color indicates active region (n+ source or drain region in

NMOS) and pink color indicates the polysilicon which forms the gate

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region of the transistor. Use the keyboard shortcuts given below to rotate

the transistors to get the below appearance.

(31) Click on Pactive to metal1 contact icon in the components and drop it on

the both sides of PMOS.

N active contact

P active contact

See the node name at the status bar

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(32) Similarly place for NMOS the Nactive to metal contacts on both the sides.

The complete design must look like as below.

(33) To connect the PMOS active region to the metal contact click on the plus

symbol which appears by mouse movement on the edge of the transistor

active region and then right click on the metal contact. The connection

once made successfully you can see the white highlighting as shown

below.

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(34) Similarly do connections between NMOS active region to NMOS active to

metal contact points.

DRC (Design rule check) (35) Then connect the drain of the PMOS and drain of NMOS. In layout

depending which ever you connect to substrate automatically the tool

takes it as source. The completed layout must be as below. Click F5 to

check for DRC (design rule check). In case of errors then press SHIFT +

< or SHIFT + > to navigate through each error (when the cell window is

selected). As we keep pressing the error message will be shown in

message window and the error regions shall be highlighted in the cell

window. To understand the errors (and hence design rules) refer the

Appendix-B. After fixing all errors once we click F5 then it must show 0

errors and 0 warnings in the message window.

(36) Notice that automatically it takes metal 1 to connect the drain contacts of

PMOS and NMOS.

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(37) Now we shall place the “metal-1 to P Well contact” at the NMOS as

shown in below figure.

(38) If we press F5 and then we will notice one error. Rule 1.1. Check the

appendix-B it refers to minimum well size. We can fix this error by double

clicking on the well and increasing the size of the well to 6X6.

(39) Similarly place the “metal-1 to Nwell contact” near the PMOS source

region and increase its size to 6X6. Connect the source to well contact.

The finished design must look like below.

(40) Check for DRC and fix in case of any errors. Usually when we keep the

components little apart we can easily fix the DRC errors. However the

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resulting layout size shall be bigger. But during the initial stage we can

compromise on the area and try learning the tool flow.

(41) Note that when DRC has no errors, pop window doesn’t appear only in

the message window the message “0 errors and 0 warnings” comes.

(42) Connect the polysilicon ends. Place a “metal-1 to polysilicon-1 con” and

connect it to the polysilicon track connecting both the gates. Place a pure

metal node at the left side of this contact and establish contact with the

“metal-1 to polysilicon-1 con”.

(43) The design at present stage must look like as below.

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(44) Now we will export the nodes.

(45) Select the metal 1 boundary at the gate input side and press CNTL+E.

enter the name and export characteristics as below. The input must be

selected in the characteristics.

(46) To drag metal1 out of the rail connecting both the drains. Click on the

metal1 and right click outside till where ever we want to bring the metal 1

contact.

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(47) Similarly export the comman drain output, vdd and gnd with appropriate

export characteristics. The finished design must look like below.

(48) Check for DRC errors and fix if any.

(49) Now we shall export the netlist. Click on tool > simulation (spice) > write

spice deck

(50) Choose appropriate name and folder for the design. Open the file we

shall see the parasitic capacitors and resistors extracted from the layout.

(51) In next module we shall see the simulation of this script using SPICE tool.

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LVS (layout vs Schematic) (52) To perfrom the LVS click open both schematic and layout in two different

cell windows. Note that the check box edit in new window must be

selected such that both the schematics and layout are opened.

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(53) Once both the schematic and layout cells are open then click tool > NCC

> cells from two windows as shown below.

(54) We are supposed to get a message as shown below.

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(55) To chech even the transistor sizes we can click file > preferences and

modify the NCC options as shown below.

(56) Now we can run the NCC again to get the following message

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Module 2

Using LT-SPICE for simulation

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Using LT-SPICE for simulation Aim: To learn the SPICE netlist command formats and simulation of inverter schematic and layout (prepared in module-1) using LT-SPICE tool. SPICE Tool flow: SPICE stands for Simulation Program with Integrated Circuit Emphasis)

It is a general-purpose open source analog electronic circuit simulator. It is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior. Syntactical Rules:

• In SPICE every line is a different command. To continue a command in a

next line, “+” symbol helps the tool to understand as ‘same command next

line’.

• The line should start with a dot “.”

• First Letter of every command is the component for SPICE

E.g:

In the above circuit, the command for a voltage source is V1 A C 5 Starting letter V is a voltage source for a SPICE tool. After V it can be character or a number like V1 or Vs. Similarly, to denote a resistor R1 A B 50 If there are multiple resistors then command should start with R, but suffix must be different for others. Where A, B and C are nodes in the circuit.

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• SPICE is case insensitive.

• You can add a comment or ignore any statements by placing a “*” at the

beginning of the line. This is a great way to label circuit sections, include

some simple notes in the file, or remove a component.

Some commands: Devices: .C device - Capacitor.

C{name} {+node} {-node} [{model}] {value} [IC={initial}] Examples: CLOAD 15 0 20pF

CFDBK 3 33 CMOD 10pF IC=1.5v

D device - Diode. D{name} {+node} {-node} {model} [area] Examples: DCLAMP 14 0 DMOD

I device - Current Source. I{name} {+node} {-node} [[DC] {value}] [AC {mag} [{phase}]] Examples: IBIAS 13 0 2.3mA IAC 2 3 AC .001 IPULSE 1 0 PULSE(-1mA 1mA 2ns 2ns 2ns 50ns 100ns) I3 26 77 AC 1 SIN(.002 .002 1.5MEG)

J device - Junction FET. J{name} {d} {g} {s} {model} [{area]}

Examples: JIN 100 1 0 JFAST K device - Inductor Coupling. K{name} L{name} { L{name} }* {coupling} Examples: KTUNED L3OUT L4IN .8 KXFR1 LPRIM LSEC .99 L device - Inductor. L{name} {+node} {-node} [model] {value} [IC={initial}]

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Examples: LLOAD 15 0 20mH L2 1 2 .2e-6 LSENSE 5 12 2uH IC=2mA

M device - MOSFET. M{name} {d} {g} {s} {sub} {mdl} [L={value}] [W={value}]

+ [AD={value}] [AS={value}] + [PD={value}] [PS={value}] + [NRD={value}] [NRS={value}]

Examples: M1 14 2 13 0 PNOM L=25u W=12u M13 15 3 0 0 PSTRONG

Q device - Bipolar Transistor.

Q{name} {c} {b} {e} [{subs}] {model} [{area}] Examples: Q1 14 2 13 PNPNOM Q13 15 3 0 1 NPNSTRONG 1.5

STATEMENTS

AC - AC Analysis. .AC [LIN][OCT][DEC] {points} {start} {end} Examples: .AC LIN 101 10Hz 200Hz .AC DEC 20 1MEG 100MEG

.DC - DC Analysis. .DC [LIN] {varname} {start} {end} {incr} .DC [OCT][DEC] {varname} {start} {end} {points} Examples: .DC VIN -.25 .25 .05 .DC LIN I2 5mA -2mA 0.1mA VCE 10V 15V 1V

.FOUR - Fourier Analysis. .FOUR {freq} {output var}* Examples: .FOUR 10KHz v(5) v(6,7)

.IC - Initial Transient Conditions. .IC { {vnode} = {value} }* Examples: .IC V(2)=3.4 V(102)=0

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.MODEL – Device Model.

.MODEL {name} {type} Typename Devname Devtype CAP Cxxx capacitor IND Lxxx inductor RES Rxxx resistor D Dxxx diode NPN Qxxx NPN bipolar PNP Qxxx PNP bipolar NJF Jxxx N-channel JFET PJF Jxxx P-channel JFET NMOSMxxx N-channel MOSFET PMOS Mxxx P-channel MOSFET VSWITCH Sxxx voltage controlled switch Examples: .MODEL RMAX RES (R=1.5 TC=.02 TC2=.005) .MODEL QDRIV NPN (IS=1e-7 BF=30)

.NODESET – Initial bias point guess. .NODESET { {node}={value} }* Examples: .NODESET V(2)=3.4 V(3)=-1V

.NOISE - Noise Analysis. .NOISE {output variable} {name} [{print interval}] Examples: .NOISE V(5) VIN

.PLOT – Plot Output. .PLOT [DC][AC][NOISE][TRAN] [ [{output variable}*] Examples: .PLOT DC V(3) V(2,3) V(R1) I(VIN) .PLOT AC VM(2) VP(2) VG(2)

.PRINT – Print Output. .PRINT [DC][AC][NOISE][TRAN] [{output variable}*] Examples: .PRINT DC V(3) V(2,3) V(R1) IB(Q13) .PRINT AC VM(2) VP(2) VG(5) II(7)

.PROBE – Save simulation output PSPICE COMMAND. .PROBE [output variable]*

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Examples: .PROBE .PROBE V(3) VM(2) I(VIN)

.SENS - Sensitivity Analysis. .SENS {output variable}* Examples: .SENS V(9) V(4,3) I(VCC)

.SUBCKT - Subcircuit Definition. .SUBCKT {name} [{node}*] Examples: .SUBCKT OPAMP 1 2 101 102

TEMP – Temperature Analysis. .TEMP {value}* Examples: .TEMP 0 27 125

.TF – DC Transfer Function. .TF {output variable} {input source name} Examples: .TF V(5) VIN

TRAN - Transient Analysis. .TRAN {print step value} {final time} [{no print time} [{step ceiling value}]] [UIC] Examples: .TRAN 5NS 100NS

INSIDE A TYPICAL SPICE FILE The heart of your SPICE file is the netlist, which is simply a list of components and the nets (or nodes) that connect them together. As an example, we'll create a netlist for a simple low-pass RC filter. Just draw the schematic, then assign names for the resistor, capacitor, voltage source (R1, C1, VS) and node numbers (1 and 2). Ground is the only exception whose node is always numbered 0. Then generate a text file like the one below. LPFILTER.CIR - SIMPLE RC LOW-PASS FILTER *

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VS 1 0 AC 1 SIN(0VOFF 1VPEAK 2KHZ) * R1 1 2 1K C1 2 0 0.032UF * * ANALYSIS .AC DEC 5 10 10MEG .TRAN 5US 500US * * VIEW RESULTS .PRINT AC VM(2) VP(2) .PRINT TRAN V(1) V(2) * .PROBE .END Top↑ COMPONENTS As you can see, much of the netlist is intuitively obvious: name a component, designate the nodes where it's connected, and give it a value. For example, RS 1 2 1000 describes a 1000 ohm resistor connected between nodes 1 and 2. Just follow a few rules - all resistors names begin with R, capacitors with C, voltage sources with V, etc. For more information go to SPICE Command Summary. Top↑ VOLTAGE SOURCE SPICE has many voltage sources available: SINE, PULSE, AC, DC, etc. For this example, the voltage source statement has two functions. VS 1 0 AC 1 SIN(0V 0.2V 10kHz) First, it creates an AC signal source between nodes 1 and 0 for AC (frequency) Analysis. Second, it also generates a sinewave source SIN for the Transient (time) Analysis. This sine wave has a DC offset of 0 V, a peak amplitude of 0.2 V and a frequency of 10 kHz. AC AND TRANSIENT ANALYSIS

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SPICE is capable of performing both AC (frequency) Analysis and Transient (time) Analysis. SPICE also performs a number of other analyses like DC, Sensitivity, Noise and Distortion. The command .AC DEC 5 10 10MEG tells SPICE to run an AC Analysis at 5 points per DECade in the frequency range from 10 Hz to 10 MHz. The command .TRAN 0.001MS 0.2MS requests a Transient (time) Analysis TRAN for a duration of 0.2 ms and prints out the results at 0.001 mS intervals. WINDOWS PLOT VIEWER What analysis results do you want to see? Most SPICE versions today automatically open a separate plot window after running a simulation. Through pull-down menus typically named Add Plot or Add Trace, you can enter variables like V(2) or I(R1) to be plotted. Some viewers list all of the variables and you just click on the ones you want to see. As a bonus many plotting windows let you enter calculations like V(2)*I(VS) or V(2)-V(1). The more sophisticated versions go a step further by providing operations on variables like AVG( V(2) ) or RMS( V(2)*I(VS) ). NOTE : SPICE will save the variables for the plot window if you include the .PROBE statement in the netlist. Spice automatically plots the variables in the window specified by the PRINT statement. You can display the magnitude, real part, imaginary, part, phase, etc of the variables for the AC Analysis. Just add the appropriate suffix as follows:

PRINTING AND PLOTTING RESULTS

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Most versions of SPICE also print the results to a text file named filename. OUT. The PRINT command places the numerical results in a table. .PRINT AC VM(2) .PRINT TRAN V(1) V(2) The statements above print the voltage magnitude at node 2 for the AC Analysis and the voltages at nodes 1 and 2 for the Time Analysis. The PLOT command creates a line-printer like graph of the data. .PLOT TRAN V(1) V(2) .PLOT AC VM(2) Both results are generated in a text file named LPFILTER.OUT

Experiment procedure: 1) Launch LT-SPICE. It should open as below.

2) Open the spi file for schematic created in module-1 for inverter.

3) To perform he dc analysis add the following commands at the bottom of

the code, before the .end statement.

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vs vdd gnd 1.8v vin in gnd 1.8v .dc vin 0v 1.8v 0.01v

4) Run simulation button as shown below.

5) We must a get a pop up window with all the nodes list for plotting as

shown below. Select the v(in) and v(out).

Run

Path for modelfile

Additional commands added for

DC analysis

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6) You must observe the plots as given in next figure.

7) You can also add additional voltages by right clicking on the plot and

selecting “add trace” option.

8) If we want to add additional plots we can right click in the plot page and

selecting “add plot pane”

9) We can drog the v(in) and v(out) labels and drop in different plot pane.

10) Now add the current in NMOS drain in another plot pane. You must

observe the results as below.

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11) Repeat the same steps for layout extracted netlist.

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Module 3

MoS inverter DC Characteristics, AC Characteristics,

Transient Analysis

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MoS inverter DC Characteristics, AC Characteristics Transient Analysis

Aim: To perform the DC,AC and transient analysis of MOS inverter. Experiment procedure:

1) The DC analysis for MOS inverter is already covered in module-2

experiment.

2) For doing the transient analysis the following commands can be added

in spice netlist (note that the dc analysis added commands to be

removed) before .end statement.

vs vdd gnd 1.8v va in gnd pulse(0v 1.8v 2ns 1ps 1ps 2ns 4ns) .tran 1ps 10ns .print v(in) v(out)

3) To perform AC analysis the following commands can be added at the

end of code.

vs vdd gnd 1.8v va in gnd ac 1v .ac dec 1000 1HZ 10MHz .print v(out)

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Module 4

Schematic, layout, DRC, LVS and post layout simulation

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Schematic, layout, DRC, LVS and post layout simulation Aim: To design the schematic and layout of following and simulate the resulting netlists.

a. NMOS, PMOS Characteristics. b. NAND, NOR, EXOR. c. half Adder, full adder and multiplexer. d. decoder

Note that the model file path is to be changed as per the location where model file is kept before simulating the spi netlists given in the course CD.

Experiment procedure: (a) NMOS and PMOS characteristics

To draw the NMOS characteristics follow the below procedure

Place one NMOS transistor in schematic editor and export the nodes. Add DC commands to sweep the Vds and plot Id for various values of Vgs We must get the V-I drain characteristics of minimum size NMOS transistor (L=0.18 micron, W=0.27 micron), simulated with 0,18 micron model file as shown below.

Vds

Id Vgs = 1.8V

Vgs = 1.6V

Vgs = 1.4V

Vgs = 1.2V

Vgs = 1V

Vgs =0.8V

Vgs = 0.6V

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Repeat the same steps for PMOS characteristics. NAND Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

Results

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NOR Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

Results

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EXOR Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

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Results

Half Adder Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

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Results

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Full adder Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

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Results

Subtractor Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

Results

Multiplexer Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

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Results

Decoder Generate the schematic and layouts as below and perform transient analysis to observe the results. Refer the course CD for already prepared schematics and layouts. Transistor sizing is done to maintain same rise time and fall time.

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Results

Assignment: (a) Modify the XOR schematic to make XNOR and simulate

(b) Modify the full adder to get full subtractor and simulate

(c) Complete the layout and schematic for 2 bit comparator.

Note that the course CD also has AND and OR layouts which can also be experimented. For simulating and spi files change the model file path.