EC6302 Digital Electronics III Semester - DCE · EC6302 Digital Electronics III Semester Department...

EC6302 Digital Electronics III Semester

Department of Electronics and Communication Engineering 104

EC6302 DIGITAL ELECTRONICS

UNIT I

MINIMIZATION TECHNIQUES AND LOGIC GATES

PART A

De-Morgan’s Theorem

1. State and prove De Morgan’s theorem. [N/D – 10]

De Morgan suggested two theorems that form important part of Boolean algebra.

They are:

i. The complement of a product is equal to the sum of the complements.

(AB)' = A' + B'

ii. The complement of a sum term is equal to the product of the complements.

(A + B)' = A'B'

2. Apply De Morgan’s theorem for the function ((𝑨 + 𝑩 + 𝑪)𝑫)′. [N/D – 08]

𝐹 = ((𝐴 + 𝐵 + 𝐶)𝐷)′

= (A+B+C)' + D'

= A'. B'. C' + D'

3. Simplify the following using De Morgan’s theorem ((𝑨𝑩)′𝑪)′𝑫′.

𝐹 = ((𝑨𝑩)′𝑪)′𝑫′

= ((AB)' + C'). D'

= ( A'+B'+C').D'

4. Find the complement of the following functions by applying De Morgan’s theorem

𝒂) 𝑭𝟏 = 𝒙′𝒚𝒛′ + 𝒙′𝒚′𝒛 𝒃) 𝑭𝟐 = 𝒙(𝒚′𝒛′ + 𝒚𝒛)

Solution:

i. F1’ = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z')

ii. F2' = [x(y'z' + yz)]' = x' + (y'z' + yz)'

= x' + (y'z')'(yz)'

= x' + (y + z)(y' + z')

5. Define – Duality Property



Duality property is defined as; every algebraic expression deducible from the

postulates of Boolean algebra remains valid, if the operators and identity elements are

interchanged. If the dual of an algebraic expression is desired, we have to simply

interchange OR and AND operators and replace 1's by 0's and 0's by 1's.

Minimization of Boolean expressions

6. State the two canonical forms of Boolean algebra. [A/M – 07]

The two canonical forms of Boolean algebra are:

i. Sum of products

ii. Products of Sum

7. Simplify: (𝑿 + 𝑿′𝒀) [A/M – 10]

Z= X + X'Y = X + XY + X’Y since X + XY = X

Z= X + Y (X + X') since X + X' = 1

Z = X + Y

8. State the basic properties of Boolean algebra.

The basic properties of Boolean algebra are:

i. An identity element with respect to +, designated by 0: A + 0 = 0 + A = A

An identity element with respect to . (dot), designated by 1: A . 1 = 1 . A = A

ii. Commutative with respect to + : A + B = B + A

Commutative with respect to . (dot) : A . B = B . A

iii. Distributive property of . (dot) over + : A . (B + C) = (A . B) + (A . C)

Distributive property of + over . (dot) : A + (B . C) = (A + B) . (A + C)

iv. Associative property of + (dot): A + (B + C) = (A + B) + C

Associative property of . (dot): A . (B . C) = (A . B) . C

9. Simplify: 𝑨𝑩 + (𝑨𝑪)′ + 𝑨𝑩′𝑪(𝑨𝑩 + 𝑪)

AB + (AC)' + AB'C (AB + C) = AB + (AC)' + AAB'BC + AB'CC

= AB + (AC)' + AB'CC [A.A' = 0]

= AB + (AC)' + AB'C [A.A = 1]

= AB + A' + C' +AB'C [(AB)' = A' + B']

= A' + B + C' + AB'C [A + AB' = A + B]

= A' + B'C + B + C' [A + A'B = A + B]

= A' + B + C' + B'C

=A' + B + C' + B'



=A' + C' + 1

= 1 [A + 1 =1]

10. Simplify the following expression, Y = (𝑨 + 𝑩)(𝑨 + 𝑪′)(𝑩′ + 𝑪′).

Y = (A + B)(A + C' )(B' + C' )

= (AA + AC' +AB +BC' )(B' + C') [A.A = A]

= (A + AC' +AB +BC') ( B' + C' )

= (A ( 1+ C' + B) + BC') ( B' + C' ) [A+1 = 1]

= (A + BC') ( B' + C' )

= AB' + AC' + BB'C' + BC'C'

= AB' + AC' + BC'

= A (B' + C') + BC'

11. Prove that (𝑿 + 𝒀′ + 𝑿𝒀)(𝑿 + 𝒀′)(𝑿′𝒀) = 𝟎.

(X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y') (X' + Y) [A + A'B = A + B]

= (X + Y') (X + Y') (X'Y) [A + A' = 1]

= (X + Y') (X'Y) [A.A = A]

= X.X'Y + Y'.X'.Y [A + A = A]

= 0 [A.A' = 0]

12. Prove that (𝑨𝑩𝑪 + 𝑨𝑩𝑪′ + 𝑨𝑩′𝑪 + 𝑨′𝑩𝑪) = (𝑨𝑩 + 𝑨𝑪 + 𝑩𝑪).

LHS

ABC + ABC' + AB'C + A'BC = AB(C + C') + AB'C + A'BC [A + A' = 1]

=AB + AB'C + A'BC

=A(B + B'C) + A'BC [A + A'B = A + B]

=A(B + C) + A'BC

=AB + AC + A'BC

= B(A + A'C) + AC

=B(A + C) + AC

=AB + BC + AC

=AB + AC +BC = RHS Hence Proved

13. List out the methods adopted to reduce Boolean function.



The methods adopted to reduce Boolean function are:

i. Karnaug map

ii. Tabular method or Quine Mc-Cluskey method

iii. Variable entered map technique

Sum of Products (SOP) and Product of Sums (POS)

14. What is the complement of (𝑨 + 𝑩𝑪 + 𝑨𝑩)? [N/D – 08]

F = (A+ BC+ AB)

F’ = (A+ BC+ AB)'

= A'. (BC)'. (AB)'

= A'. (B'+ C'). (A'+ B')

15. Convert the given expression to canonical Sum of products form:

𝒀 = (𝑨𝑪 + 𝑨𝑩 + 𝑩𝑪)

Y = AC + AB + BC

=AC (B + B' ) + AB(C + C' ) + (A + A')BC

=ABC + AB'C + ABC + ABC' + ABC + A'BC

=ABC + AB'C + A'BC

CMOS Logic and their characteristics

16. What is meant by propagation delay? [A/M – 09]

The propagation delay, or gate delay, is the length of time which starts when the

input to a logic gate becomes stable and valid, to the time that the output of that logic

gate is table and valid. Often this refers to the time required for the output to reach from

10% to 90% of its final output level when the input changes. Reducing gate delays in

digital circuits allows them to process data at a faster rate and improve overall

performance.

17. List out the advantages of CMOS logic. [A/M – 09]

The advantages of CMOS logic are:

i. Low power consumption: CMOS process provides lower power consumption and

is easy to scaling down.

ii. High input impedance: Gate of CMOS needs much lower driving current than

base current of bipolar.

iii. Reduced silicon area: Scaling down increases CMOS speed and reduces the area

of the chip.

iv. Mature technology: CMOS processes are well established and continue to become

more mature. The powerful trust by leading edge digital memory and processors

has led to continuous improvement and down scaling of CMOS processes.



18. Define – Noise Margin [N/D – 08]

Noise Margin is defined as the maximum noise voltage added to an input signal of

a digital circuit that does not cause an undesirable change in the circuit output. It is

expressed in volts.

19. Define – Power Dissipation and Propagation Delay [A/M – 05]

Power dissipation is defined as the measure of power consumed by the gate when

fully driven by all its inputs.

Propagation delay is defined as the average transition delay time for the signal to

propagate from input to output when the signals change in value. It is expressed in ns.

20. Write the important characteristics of digital ICs.

The important characteristics of digital ICs are:

i. Fan out

ii. Power dissipation

iii. Propagation Delay

iv. Noise Margin

v. Fan In

vi. Operating temperature

vii. Power supply requirements

NAND–NOR implementations

21. Prove that a bubbled input AND gate, functions like a NOR gate. [A/M – 04]

Truth Table for NOR Gate and bubbled input AND gate

A A’ B B’ A+B Y= (A+B)’

(NOR Gate)

Y= (A’.B’)

(Bubbled input

AND gate)

0 1 0 1 0 1 1

0 1 1 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 1 0 0

Thus

(A+B)’ = A’. B’



22. How is NAND gate used as an inverter? [A/M – 04]

Logic Diagram for Inverter

The two input terminals of the NAND gate will be shorted and given as single input.

Now the above NAND gate act as a inverter

Karnaugh map Minimization

23. What is a Karnaugh map?

A Karnaugh map or k map is a pictorial form of truth table, in which the map

diagram

is made up of squares, with each squares representing one minterm of the function.

24. State the limitations of Karnaugh map.

The limitations of Karnaugh map are:

i. It is limited to six variable map (i.e) more then six variable involving expression

are not reduced.

ii. The map method is restricted in its capability, since, they are useful for

simplifying only Boolean expression represented in standard form.

25. Define – Don’t Care Conditions

In some logic circuits, certain input conditions never occur; therefore, the

corresponding output never appears. In such cases, the output level is not defined, it can

be either HIGH or LOW. These output levels are indicated by ‘X’ or ‘d’ in the truth

tables and are called don’t care outputs or don’t care conditions or incompletely

specified functions.

26. Define– Prime Implicant

A prime implicant is defined as the product term obtained by combining the

maximum possible number of adjacent squares in the map.

27. What is essential prime implicant?

A prime implicant is defined as the product term obtained by combining the



maximum possible number of adjacent squares in the map.

If a min term is covered by only one prime implicant, the prime implicant is said to be an

essential prime implicant

Logic Gates

28. List out the universal gates.

The NAND and NOR gates are known as universal gates, since any logic function can be

implemented using NAND and NOR gates.

29. Define – Fan-out and Fan-in of a Logic Gate [N/D – 08]

Fan out is defined as the number of standard loads that the output of the gate can drive

without impairment of its normal operation.

Fan in is defined as the number of inputs connected to the gate without any degradation

in the voltage level.



Unit II - COMBINATIONAL CIRCUITS

Half adder and Full Adder

1. What is a combinational logic circuit? Write an example. (M/J – 08)

When logic gates are connected together to produce a specified output for certain

specified combinations of input variables, with no storage involved, the resulting circuit

is called ‘combinational logic circuit’.

A combinational circuit consists of input variables, logic gates and output variables. For

example, consider following Boolean expression:

Y = AB + BC + AC

The combinational logic circuit for this would require 3 AND gates and 1 OR gate which

are follows:

2. What is a half adder and a full adder? (D/J – 08)

Half adder : The logic circuit which performs the arithmetic sum of two bits is called

a half adder.

Full adder : The logic circuit which performs the arithmetic sum of three bits ( bit 1:

input 1, bit 2:input 2, bit 3: carry from the previous addition) is called a full adder.



Half subtractor and Full subtractor

3. What is a half subtractor and a full subtractor? (M/J – 09)

Half subtractor: It is a combinational circuit that subtracts two bits and produces

their difference and borrow.

Full subtractor: It is a combinational circuit that performs a subtraction between 2 bits.

It also takes into account borrow of the lower significant stage.

Parallel binary adder/ Subtractor

4. Compare binary serial adder with binary parallel adder. (D/J – 11)

S.No Serial Adder Parallel Adder

1 Serial adder uses shift registers. Parallel adder uses registers with parallel

load capacity.

2 The serial adder requires only one

full-adder circuit.

The number of full-adder circuits in the

parallel adder equal to the number of bits

in the binary numbers.

3 The serial adder is a sequential

circuit.

Excluding the registers, the parallel

adder is a purely combinational circuit.

4 Time required for addition depends

on number of bits.

Time required for addition does not

depend on the number of bits.

5 It is slower. It is faster.

5. List the differences between a half adder and a full adder. (D/J – 07)

Half adder Full adder

Half adder takes two binary-inputs i.e

augend and addend bits and gives out

two binary outputs as sum and carry.

Full-adder alongwith augend and addend takes third

additional bit Cin as input. Cin represents the carry

from the previous lower significant position.



Half-adder is not used in practice Full-adder is used in practice.

Block diagram:

A Carry

B Outputs

Sum

Block diagram:

A Carry

B Sum

Carry Look Ahead adder

6. What is meant by carry propagation delay? (D/J – 09)

In parallel adders, sum and carry outputs of any stage cannot be produced until the

input carry occurs. This time delay in the addition process is called carry propagation

delay. This delay increases with increase in the number of bits to be added in an adder

circuit.

7. What is a A ripple ─ carry – adder?

A ripple ─ carry – adder is parallel adder in which the carry-out of each full adder

is the carry-in to the next most significant adder.

8. How does the look-ahead-carry speed up the addition process?

The Look-ahead-carry adder speeds up the addition process by eliminating the ripple

carry delay. It examines all the input bits simultaneously, and also generates the carry-in-

bits for all the stages simultaneously.

Serial Adder/Subtractor

9. What is a serial adder?

A serial adder is a sequential circuit used to add serially binary numbers.

Magnitude Comparator

10. Write a short note on one bit comparator. (M/J - 08)

It is a special combinational circuit designed primarily to compare the relative

magnitudes of two binary numbers. An n-bit comparator receives two n-bit numbers, A

and B outputs are: A>B, A=B and A<B. As per the magnitudes of the two numbers, one

of the outputs will be high

11. Suggest a solution to overcome the limitation on the speed of an adder. (D/J – 09)

It is possible to increase speed of adder by eliminating inter-stage carry delay.

Full

Adder

Half

Adder



This method utilizes logic gates to look at the lower – adder bits of the augend and

addend to see if a higher-adder carry is to be generated.

Multiplexer/Demultiplexer

12. Differentiate between a demultiplexer and a decoder. (D/J – 09)

S.No Decoder Demultiplexer

1 Decoder is a many inputs to many

outputs device.

Demultiplexer is a one input to

many outputs device.

2 There are no selection lines. The selection of specific output line

is controlled by the value of

selection lines.

13. What is a data selector?

Multiplexer is a digital switch. Particularly, it has 2n input lines and n selection

lines whose bit combinations determine which input line is selected and routed onto

available only single line.

Hence, multiplexer is a selector of one out of several data sources available at its

input lines, to connect it to output line. Simply it is a ‘Many into one’ device and also

called ‘data selector’.

14. List out the differences between DEMUX and MUX. (M/J – 09)

Parameter Multiplexer Demultiplexer

Definition Multiplexer is a digital switch

which allows digital

information from several

sources to be routed on to a

single output line.

Demultiplexer is a circuit that

receives information on a

single line and transmits this

information on one of 2n

possible output lines.

Number of data

inputs

2n 1

No of data outputs 1 2n

Relationship of input

and Output

Many to one One to many



Applications 1. Used as a data selector.

2. In time division in

multiplexing at the transmitting

end.

1. Used as a data distributor.

2. In time division

multiplexing at the receiving

end.

15. What are the applications of Multiplexer and Demultiplexer? (D/J – 08)

The application of Multiplexer are:

i. They are used in time multiplexing systems.

ii. They are used in frequency multiplexing systems.

iii. They are used in data acquisition systems.

The applications of Demultiplexer are:

i. It can be used as a decoder.

ii. It can be used as a data distributer.

iii. It can be used to implement Boolean expressions.

Encoder/Decoder

16. What is the maximum number of outputs for a decoder with a six bit data word?

(M/J – 09)

The number of data inputs bits = 6.

The maximum number of outputs for decoder 26=64

17. What is the type of display used in calculators?

The type of display used in calculators is 7-segment LED/LCD.

BCD adder

18. How are BCD adders different from a binary adder?

While adding BCD numbers, the output is required to be corrected this is not

required in the case of binary adders.

Parity checker and parity generators

19. What is a parity bit generator?

A parity bit generator is a digital circuit that generates a bit called the parity bit to

be added to the data bits.



Unit III - SEQUENTIAL CIRCUITS

Flip-flops:

1. What are synchronous sequential circuits? (M/J – 10)

Synchronous sequential circuits are those in which signal can affect the memory

element only at discrete instants of time. Clocked flip-flops are examples of

synchronous sequential circuits.

2. Write the characteristic equation and draw the state diagram of JK Flip-flop.

(M/J – 10)

Characteristic equation: Qn+1= JQ’n=KQn

State Diagram:

3. Draw the logic diagram of SR Flip-flop. (M/J – 10)

SR Flip-flop

4. Define – Sequential Logic Circuit. Write an example. (M/J – 08)

The circuits in which the output variables depend not only on the present input but

they also depend upon the past outputs, which are known as sequential logic circuits.

Flip-flops, counters and registers are the examples of sequential logic circuit.



5. Define – Race Around Condition

In a JK flip-flop , when J = K = 1 and for every clock pulse applied the output

changes its state.ie. the output toggles for every clock pulse applied. This condition is

called as ‘race around condition’.

6. What is a master-slave flip-flop? Write an example.

` A master-slave flip-flop consists of two flip-flops where one circuit serves as a

master and the other as a slave. When c = 1, the first flip flop is enabled and thus the

master is enabled. When c = 0, the slave flip flop (second one) is enabled.

Master slave S-R flip flop

7. Write the excitation table for RS FF.

The excitation table for RS FF:

Qn Qn+1 R S

0 0 X 0

0 1 0 1

1 0 1 0

1 1 0 X

8. Write the excitation table for JK flip-flop.

The excitation table for JK flip-flop:

Qn Qn+1 J K

0 0 0 X

0 1 1 X

1 0 X 1



1 1 X 0

9. Write the excitation table for D flip-flop

The excitation table for D flip-flop:.

Qn Qn+1 D

0 0 0

0 1 1

1 0 0

1 1 1

10. Write the excitation table for T flip-flop.

The excitation table for T flip- flop:

Qn Qn+1 T

0 0 0

0 1 1

1 0 1

1 1 0

11. Draw the logic diagram for SR latch using two NOR gates.



SR Latch

Asynchronous and Synchronous counter

12. What is meant by programmable counter? What are its applications?

(May 10)

A programmable counter is a device in which an input frequency is loaded by a

number or count value, which can be programmed and is called programmable counter.

Applications of programmable counter are:

i. Frequency division

ii. Digital clock

iii. Stop watch

iv. Programmable logic controllers

13. Draw the state diagram of MOD-10 counter. (D/J – 08)

State diagram for mod-10

14. What is synchronous counter? (D/J – 06)

When counter is clocked such that each flip-flop in the counter is triggered at the

same time, the counter is called synchronous counter.

15. What is a self starting counter? (M/J – 10)

In a counter, if the next state of some unused state is again an unused state and if

by chance, the counter happens to find itself in the unused states and never arrived at a

used state, then the counter is said to be in the lockout conditions. The counter which

never goes in lockout condition is called self starting counte

Shift register

16. What is a shift register? List its types. (D/J – 10 )

The binary information in a register can be moved from stage to stage

within the register or into or out of the register upon application of clock pulses.



This type of bit movement or shifting is essential for certain arithmetic and logic

operations used in microprocessors. This gives rise to group of registers called shift

registers.

There are five types. They are:

i. Serial in serial out shift register

ii. Serial in parallel out shift register

iii. Parallel in serial out shift register

iv. Parallel in parallel out shift register

v. Bi─ directional shift register

17. What is the difference between serial transfer and parallel transfer? What is the

type of register used in each case? (D/J – 07)

When data is transferred one bit at a time, the process of transfer is known as

serial transfer. When multiple bits are transferred at a time, the process is known as

parallel. For parallel transfer, we can use parallel in and parallel out register. For serial

transfer we can use left shift or right shift register.

18. What are the basic building blocks of an Algorithmic State Machine? (M/J – 11)

The basic building blocks of an ASM chart are:

i. State box

ii. Decision box and

iii. Conditional box



UNIT – IV – MEMORY DEVICES

Classification of Memories

1. State the various types of ROM

The various types of ROM are

i. The Mask Programmable Memory or ROM

ii. Programmable Read Only Memory or PROM

iii. Erasable EPROM

iv. Electrically Erasable PROM (EEPROM or E2PROM)

v. Electrically Alterable Programmable Read only memory( EAPROM)

2. What is meant by memory expansion? Mention its limitations.

Memory IC’s can be connected together to expand

i. The number of memory words

ii. The number of bits per word.

Example: 512 x 4 bit memory can be constructed using two 256 x 4 bit PROM. This is

an example for increasing the memory words by using two 256 x 4 bit chips.

3. What is access time and cycle time of a memory?

Access Time:

The access time of memory is the time required to select a location in memory to

read/write.

Cycle Time:

The cycle time of memory is the time required to complete a write/read operation.

4. What is volatile memory? Write an example.

Memory units that lose stored data, when power is turned off are said to be

volatile. Example: Static RAM, Dynamic RAM.

5. Define – Memory Locations

Memory locations are defined as the memory cells or word locations that are

separated in space, each word occupying one particular location.



6. Compare static RAM with Dynamic RAM

7. Define – Memory cell. Write an example.

A Memory cell (or) binary cell is defined as basic building block of a memory

unit that stores one bit of information.

8. What is a static memory?

A static memory is a semiconductor memory that consists of internal latches (D Flip

Flop) to store the binary information. The stored information remains valid as long as

power is applied to the memory unit. Thus a static memory can also be called as volatile

memory.

9. What is a ROM?

A ROM (Read Only Memory) is a programmable logic device in memory device

S.No. STATIC RAM DYNAMIC RAM

1

In a static RAM, information is stored

in the internal latches as voltage

levels.

In dynamic RAM binary information is

stored in the form of electric charges on

capacitors provided in the chip by

MOS transistors. The charge stored in

capacitors tends to discharge with time.

Thus need periodical refreshing to

retain the charge.

2

Volatile memory stored information is

available as long as power is applied

to the unit.

Requires as special refreshing current.

3

It does not required refresher. Since

it uses latches to store information.

SRAM has more power consumption

when compared to DRAM.

MOS as devices that use less power.

Thus, Consumes low power.

4 Speed is high.

Speed is low.



in which permanent binary information is stored. This binary information is specified by

the designer and is then embedded in the unit to form a required interconnection pattern.

10. How is the memory size specified?

The capacity of a memory unit is specified in terms of width and length bytes that

the unit can store. It is specified in terms of

1K = 210

=1 Kilobyte

11. A Memory has 16 bit address bus. How many locations are there in this?

No. of address lines = 16

Thus the capacity of the memory = 216

= 26.

210

= 64 * 2

10

= 64 Kilo byte memory locations

Programmable logic devices

12. What is a PLA?

PLA stands for Programmable Logic Array which consists of array of AND gates and

array of OR gates that can be programmed by the programmer. The AND gates are

programmed to provided the product terms for the Boolean functions, which are logically

summed in each OR gate.

13. Write the comparison of PROM, PAL and PLA

PROM: A PROM has a fixed AND array constructed as a decoder and programmable

OR array.

PAL: A PAL consists of programmable AND array and Fixed OR array.

PLA: PLA consists of AND array and OR array that are programmable by the user.



14. What are the two types of erasable PROM’s?

The two types of erasable PROM’s are:

i. EPROM –Erasable PROM

ii. EEPROM – Electrically Erasable (E2PROM)

15. How does individual location in an EEPROM programmed or erased?

In an EEPROM, a previously programmed memory location can be erased or

programmed using electrical signals in a separate circuit called reprogramming

circuit.

This memory device is made up of floating gate MOS or Metal–Nitride Oxide

Silicon (MNOS). Application of appropriate voltages at the control gate terminal in

the floating structure permits the storage and removal of charge from the floating

gate.

16. What is FPGA?

FPGA stands for Field Programmable Gate Array. An FPGA consists of an array

of hundreds or thousands of logic blocks surrounded by programmable input and

output block. There are connected together via programmable interconnections.

17. What is a combinational PLD?

A combinational PLD is an integrated circuit with programmable gates divided

into an AND array and an OR array to provide AND-OR implementation.



The three major types of combinational PLD’s are:

i. Programmable Read-Only Memory (PROM)

ii. Programmable Array Logic (PAL)

iii. Programmable Logic Array (PLA)

19. What are the advantages of PLD’s over fixed function IC’s?

The advantages of PLD’s over fixed function IC’s are

i. Larger circuits can be stuffed into a much smaller area with PLD’s.

ii. The logic design of circuits can be easily changed without rewiring or replacing

components.

iii. The time taken for implementing a design in PLD is much lesser when compared

to implementing the same circuit using fixed function ICs.

20. Which are the technologies used for the fabrication of ICs?

The technologies used for the fabrication of ICs are

i. Transistor Transistor Logic(TTL)

ii. Diode Transistor Logic (DTL)

iii. CMOS Logic



Unit V -SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Synchronous Sequential Circuits

1. How does the operation of an asynchronous input differ from that of a synchronous

input? (D/J – 05 )

Asynchronous sequential circuits do not use clock pulses. The change of interval

state occurs during the short time of the pulse transition.

Synchronous sequential circuits use clock pulses. The clock pulses determine the

computational activity which should occur within the circuit.

2. What is a fundamental mode asynchronous sequential circuit? (M/J – 03)

In fundamental mode asynchronous sequential circuits, the external inputs can

change at any time and a transition from one state to another state occurs only when

changes in the input occur. The inputs and outputs are represented by voltage levels rather

than by pulses.

3. What is a flow table in asynchronous sequential circuits? (M/J – 07)

A flow table is similar to a transition table except that the internal states are

symbolized with letters rather than binary numbers. The flow table includes the output

values of the circuit for each stable state.

4. Define – Primitive Flow Table (D/J – 08)

It is a flow table which has exactly one stable state for each row in the table.

Asynchronous Sequential Circuits

5. List the various types of asynchronous sequential circuit. (M/J – 11)

The various types of asynchronous sequential circuit are

i. Fundamental mode asynchronous sequential circuits

ii. Pulse mode asynchronous sequential circuits.

Problems in Asynchronous Circuits

6. What is meant by a cycle? (M/J – 05)

A circuit which goes through a unique sequence of unstable states is said to have a

cycle.

7. What are races? (D/J – 08)

A race condition is said to exist in an asynchronous sequential circuit when two or

more binary state variables change value in response to a change in an input variable.



8. Define – Critical Race (D/J – 10)

The race condition is critical if the circuit goes to two or more different stable states

depending on the order are which the state variables change.

9. What are hazard? (D/J – 09)

Hazard is defined as the unwanted switching transient that can occur in a digital

circuit. It is the transient that is produced as a result of the varying propagation delays in

different paths from input to output of the circuit.

10. What are the causes of essential hazards? (D/J – 04)

The causes of essential hazards are

i. An essential hazard occurs due to unequal delays with two or more paths that

originate from the same input.

ii. An excessive delay through an inverter circuit in comparison to the delay associated

with the feedback path causes essential hazard.

11. What are meant by incompletely specified machines?

In incompletely specified machine, either state transitions and/or output variables

are not completely specified.

12. What is a merger graph?

Merger graph is a state reducing tool used to reduce states in an incompletely

specified machine.

Classification of sequential circuits

13. Differentiate Moore machine from Mealy machine. (D/J – 10)

S.No Moore machine Mealy machine

1. In Moore machine, the output is

a function of present states only.

In mealy machine, the output is a

function of present state and present

input.

2. The Moore machine requires

more number of states for

implementing same function.

The mealy machine requires less

number of states for implementing

same function.

3. Input changes do not affect. Input changes may affect the output of

the circuit.



14. Draw the block diagram of Moore model. (M/J – 10)

Moore Circuit model

Combinational and Sequential circuits using VERILOG

16. Write a note on Verilog. (D/J – 11)

Verilog Hardware Description Language is a software tool used to describe the

combinational and sequential circuits using a module. A module is the building block in

verilog. It is declared by the keyword module and is always terminated by the keyword

endmodule.

17. Write a verilog model of a full subtractor circuit. (D/J – 10)

module fs(a, b, c, borrow, difference);

input a,b,c;

output borrow, difference;

wire d,e,f;

assign y=~a

xor(difference,a,b,c);

and(d,y,b);

and(e,b,c);

and(f,y,c);

or(borrow,d,e,f);

endmodule

In

p

ut

s

Outputs Next

state

Decoder

Memory

Elements

EC6302 Digital Electronics III Semester - DCE · EC6302 Digital Electronics III Semester Department...

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