EC303 - Chapter 2 LOGIC DESIGN & COMPUTER ARCHITECTUR

11

LOGIC DESIGN & COMPUTER ARCHITECTURE


222



Sub Topic 2.1: Computer Aided Design

Learning OutcomeAt the end of this presentation, you will be able to:

2.1.1 Define the primary approaches to IC chip designa. Mask-programmable ICsb. Standard-cell devicesc. Custom devicesd. PLD and VHDL

2.1.2 Explain Schematic logic design using CPLDa. Overview of Schematic Design Methodsb. Design Flow Summaryc. Generated Reports after compilation schematic.d. Simulation concept

3

IC DESIGN METHODOLOGY

DESIGN METHODOLOGY TREE DIAGRAM


STANDARD IC

Standard IC : • Integrated circuits designed and fabricated for

general purpose use.

• Standard IC is available in the market at a very low cost.

• Examples of standard ICs: 74 - SERIES TTL, 4000 - SERIES CMOS, OP-AMP, TIMER, INSTRUMENTATION AMPLIFIER, MEMORY, MICROCONTROLLER, etc.


EXAMPLES OF STANDARD IC

74-series TTL

4000 series CMOS

Op-Amp Timer

Memory

Microcontroller


EXAMPLES OF STANDARD IC


ASICs

• Progress in the fabrication of IC's has enabled the designer to create fast and powerful circuits in smaller and smaller devices.

• This also means that we can pack a lot more of functionality into the same area.

• The biggest application of this ability is found in the design of ASICs.


ASICs

ASICs stands for : Application Specific Integrated Circuits

• ASICs are IC's that are created for specific purposes - each device is created to do a particular job.

• ASICs are produced for only one or a few customers or applications.

• ASICs are devices made for a specific application such as a mobile phone.

EXAMPLES OF ASICs


IC DESIGN METHODOLOGYEXAMPLES OF ASICs

GRAPHIC MEDIA ACCELERATOR

GRAPHIC MEDIA ACCELERATOR

SMART CARD CHIPSSMART CARD CHIPS


FULL CUSTOM DESIGNAll the circuits and mask layouts are completely

designed for the requirements of a particular IC.

A microprocessor is an example of a full-custom design IC—designers spend many hours squeezing the most out of every last square micron of microprocessor chip space by hand.


SEMI CUSTOM DESIGN

To make ASICs economic at lower volumes, the semi-custom concept was introduced where many applications share the same basic configuration of logic cells.

The mask layers are customized to fulfill the requirements of a particular IC.

Often used for speedy design with less effort compared to full custom design.


SEMI CUSTOM DESIGN

There are 3 types of semi custom design:-

1. Gate array (mask-programmable ICs)

2. Standard Cell

3. Programmable Logic Device (PLD)

IC DESIGN METHODOLOGYSEMI CUSTOM IC

GATE ARRAY (mask –programmable ICs)

1. Gate arrays are integrated circuits containing large numbers of digital gates or transistor cells, which can be interconnected in different ways to implement various logic functions.

2. Gate array consists of transistors, usually arranged in two pairs of PMOS and NMOS.

3. ASIC vendors offer a selection of gate array cells, with a different total numbers of transistors on each cell, for example, gate arrays with 50k-, 75k-, and 100k-gates.


GATE ARRAY FLOOR PLAN

IC DESIGN METHODOLOGYSEMI CUSTOM IC – gate array

Gate array

IC DESIGN METHODOLOGYSEMI CUSTOM IC – gate array


STANDARD CELL

1. Standard cell design involves the use of pre-designed standard cell @ library cell that has been and stored in database.

2. Standard cell @ library cell consists of simple circuit such as inverter or logic gates (AND, OR, XOR, XNOR, flip-flop), and complex circuit such as register, adder, ROM and RAM.


STANDARD CELL

3. Design is carried out by simply using the pre-designed cells from the library and then connect the cells so that certain functions can be implemented.

4. To facilitate placement and routing, the standard cells are designed to have equal height but variable widths, so that the final IC layout will have a regular pattern with rows of cells

and interconnect routing running between the rows.

3. Design is carried out by simply using the pre-designed cells from the library and then connect the cells so that certain functions can be implemented.

4. To facilitate placement and routing, the standard cells are designed to have equal height but variable widths, so that the final IC layout will have a regular pattern with rows of cells

and interconnect routing running between the rows.

STANDARD CELL FLOOR PLAN


I/O Pads

LOGIC BLOCK

BLOCK

Standard Cell

Routing

Standard Cell

Routing

Standard Cell

Routing

Standard Cell

Routing

PROGRAMMABLE LOGIC DEVICE (PLD)

PLD is an array of logic gates that can be programmed by the user which contains functions of a small number of logic circuits in a single chip.


PLD MANUFACTURERS



GENERAL CHARACTERISTICS OF PLD IC

1. PLD does not require a common mask layout in design.

2. The design time is shorter.

3. It consists of a large block of internal connections that can be a programmed.

4. Programming can be done at different stages: i) at the earliest, it is programmed by the

semiconductor vendor (standard cell, gate array).

ii) by the designer prior to assembly or field deployment.

iii) by the user in circuit.

Programmable logic device as a black box.

Logic gates and

programmableswitches

Inputs

(logic variables) Outputs

(logic functions)

IC DESIGN METHODOLOGYPROGRAMMABLE LOGIC DEVICE

DESIGN METHODOLOGY DIFFERENCES

Design method

Design cost Chip sizeOperation

speedPower

dissipationNo. of mask

Design time

Full custom

The most expensive

The smallest

Highest speed

5x Smaller

Numerous

Time-consumi

ng

Standard cell

Average Small High-speed3x

smallerMany Average

Gate array

Cheaper Large Slow2x

Smaller1@2 piece

Fast

PLDThe

CheapestLargest Slowest

1x Smaller

NoneThe

fastest


PLD programming

• Schematic Entry• Text-Based Entry

VHDL

• VHDL is the VHSIC Hardware Description Language.

• VHSIC is an abbreviation for Very High Speed Integrated Circuit

• a language to describe the structure and behaviour of digital electronic hardware designs, such as ASICs and FPGAs as well as conventional digital circuits.

D Flip-flop Model

Bit values are enclosed in single quotes

Design Entry Techniques

• Schematic – Designer draws the equivalent design using gates and other logic circuits (can include IC’s such as JK FF or 74xxx parts)

• Waveform – Design draws the desired input and output waveforms for the device

• Text Design Files – Design specifies the design using a design language such as Altera Hardware Design Language (AHDL)

Example of Schematic Design

Example of Waveform Design


2.2 Realize element logic in computer logic

2.2.1 Define clocking in terms of a digital computer. 2.2.2 Explain function clocks (wave form) in digital computer. 2.2.3 Explain gated flip-flop: a. SR flip-flop b. D flip-flop c. Master-slave flip-flop d. JK flip-flop 2.2.4 Use schematic CPLD to simulate digital output for above flip-flop.

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Element Logic in Computer Logic

37

Introduction

• Latch is a type of temporary storage device that has two stable states (bistable).

• Latches and Flip-flops are used in sequential circuits.• Differences between sequential circuits and

combinational circuits.

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Introduction

• Latch is normally placed in a category separate from that flip – flops.

• The main difference between latch and FF is in the method used for changing their state.

• Term synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK).

Logic circuits are classified into two groups:

Combinational logic circuits

Sequential logic circuits

Basic buildingblocks include:

Basic building blocksinclude FLIP-FLOPS:

Element Logic in Computer Logic

Logic gates make decisions

Flip Flops have memory

FLIP-FLOPS• Flip-flops are memory elements that change state on clock signals.

• Memory elements capable of storing one bit

• Flip Flops are wired to form counters, shift registers, and various memory devices.

command Memory element stored value

Q

clock

41

Edge – Triggered Flip - Flops

• Change state either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse.

• Sensitive to its inputs only at this transition of the clock.

• Three types of edge triggered FF1. SR 2. D3. T4. JK

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Edge – Triggered Flip – FlopsLogic Symbols

43

Positive edges Negative edges

Positive pulses

CLOCK SIGNAL The clock signal is generally a rectangular pulse train or square wave, as shown below :

• Circuits in computers are “clocked”• At each clock rising (or falling) edge, some specified actions are done,

usually within the next rising (or falling) edge

TRIGGERING OF FLIP-FLOPS

• Level-triggering is the transfer of data from input to output of a flip-flop anytime the clock pulse is proper voltage level.

45

SR FFLogic Symbols

46

SR FFTruth Table

Inputs OutputsComments

S R CLK Q Q

0 0 X Qo Qo No change

0 1 0 1 RESET

1 0 1 0 SET

1 1 ? ? Invalid condition

= clock transition LOW to HIGH

X = Irrelevant (“don’t care”)

Qo = output level prior to clock transition

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SR FFExample

48

D FF

• D flip – flop is useful when a single data bit (1 or 0) is to be stored.

• The addition of an inverter to an S – R flip flop creates a basic D flip – flop.

49

D FFTruth Table


S CLK Q Q

1 1 0 SET (stores a 1)

0 0 1 RESET (stores a 0)


50

D FFExample

51

• Versatile and is widely used type flip – flop.• The difference between J – K and S – R is that J – K flip – flop

has no invalid state as does S – R flip – flop.

JK FF

52

• Transitions illustrating the toggle operation when J = 1 and K = 1.

JK FF

53

JK FFTruth Table


J K CLK Q Q

0 0 Qo Qo No change

0 1 0 1 RESET

1 0 1 0 SET

1 1 Qo Qo Toggle



54

JK FFExample

55

Asynchronous Preset and Clear Inputs

• Independent of the clock.• Active level on the preset input will set the flip – flop.• Active level on the clear input will reset it.

Note : for synchronous operation, both preset and clear inputs must

both kept HIGH.

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Asynchronous Preset and Clear InputsLogic Diagram

57

Asynchronous Preset and Clear InputsExample

58

Master – Slave Flip – Flops

• Data are entered into the flip flop at the leading edge of the clock pulses, but the output does not reflect the input state until the trailing edge.

• Pulse – triggered master – slave flip – flop does not allow data to change while the clock pulse is active.

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Pulse – Triggered Master – Slave Flip – Flops

Master Slave JK Flip-flop

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• Composed of two sections, the master section and the slave section.

• A master section is basically a gated latch.• The slave section is the same except that it is clocked on the

inverted clock pulse and is controlled by the outputs of the master section rather than by the external J – K inputs.

Pulse – Triggered Master – Slave Flip – Flops

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Pulse – Triggered Master – Slave Flip – Flops – Truth Table


J K CLK Q Q

0 0 Qo Qo No change

0 1 0 1 RESET

1 0 1 0 SET

0 1 Qo Qo Toggle



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Pulse – Triggered Master – Slave Flip – Flops – Logic Symbol


2.3 Realize flip-flop application

2.3.1 Explain Shift Register operation. 2.3.2 Design Shift Register using flip-flop JK. 2.3.3 Determine kinds of binary counter 2.3.4 Explain binary counter operation using: a. Flip-flop SR b. Flip-flop JK 2.3.5 Design a sequence counter (3 bit) 2.3.6 Design sequential magnitude comparator 2.3.7 Design BCD to seven segment decoder

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64

Flip-Flop Applications• Applications of Flip-Flop:-

– Counters• Asynchronous Counter

• Synchronous Counter

– Register

65

Shift Register Shift registers are constructed using several flip-

flop, connected in such a way to STORE and TRANSFER digital data.

Basically, D flip-flop is used. The input data (either ‘0’ or ‘1’) is applied to the D terminal and the data will be stored at Q during positive/negative-edge transition of the clock pulse.

D Q

Q

1 1

positive edge transition of CLK

66

One D FF is used to store 1-bit of data. Thus, the number of flip-flops used is the same with the number of bit stored.

Shift register mean that the data in each FF can be transferred/move to other FF upon edge triggering of the clock signal.

Four types of data movement in shift register are:-

Parallel in / parallel out (PIPO)

Serial in / serial out (SISO)

Parallel in / serial out (PISO)

Serial in / parallel out (SIPO)

Shift Register

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Serial Data VS Parallel Data movement

Serial Parallel

•Movement of N-bit data require N number of CLK pulses. Thus, the operation is slow.

•Only one FF is required to be connected at the output terminal, thus only one wire is required.

•Require only one CLK pulse to transfer all N-bit of data. Thus, operation is faster than serial.

•Required N number of connection to the output terminal, which is proportional to the number of bit. Thus, too many connection is required.

Shift Register

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Parallel in / parallel out (PIPO) Flip-flop configuration for PIPO register.

D Q2

CP

D Q1

CP

D Q3

CP

D Q0

CP

CLK

D3 D2 D1 D0

Q3 Q2 Q1 Q0

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PIPO data movement.

Q3

Q2

CLK

Q1

Q0

1 0 1 1 1

0

0

0

0

1 0 10 0

0

0

1 1 1 1

0 0 1 0

D3

D2

D1

D0

1

0

1

0

0

1

1

0

Parallel in / parallel out (PIPO)

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Serial in / serial out (SISO) Flip-flop connection for SISO.

D Q1

FF1

CP

D Q2

FF2

CP

D Q0

FF0

CP

D Q3

FF3

CPCLK

DIN

1st CLK 2nd CLK 3rd CLK 4th CLK

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SISO data movement. Binary data 10111 is transferred!

DATA-IN

Q0

Q1

1st

CLK

2nd 3rd 4th 5th

Q2

Q3

Serial in / serial out (SISO)

1 0 1 1 1

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Flip-flop connection for SIPO.

D Q1

FF1

CP

D Q2

FF2

CP

D Q0

FF0

CP

D Q3

FF3

CPCLK

DIN

1st CLK 2nd CLK 3rd CLK 4th CLK


Q0 Q1 Q2 Q3

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SIPO data movement. Binary data 10111 is transferred!

DATA-IN

Q0

Q1

1st

CLK

2nd 3rd 4th 5th

Q2

Q3


1 0 1 1 1

1

1

0

1

74

Flip-flop connection for PISO.


D Q1

FF1

CP

D Q2

FF2

CP

D Q0

FF0

CP

D Q3

FF3

CPCLK

D0 D1 D2 D3SHIFT/LOAD

Serial data out

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PISO data movement.

SHIFT/LOAD

CLK

Q3

0

0 1 1 1

1 0 1

0

0

0

1

1 1 1 1

0 0 1 1

D0

D1

D2

D3

1 0


0 1 0 1

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A shift register counter is a shift register whose output being fed back (connected back) to the serial input. This shift register would count the state in a unique sequence!

Two types of shift register counter:-

The ring counter

The Johnson counter

Shift Register Counters

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Ring Counter

Q3 Q2 Q1 Q0

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Ring Counter (continue)

0 0 0 1

1 0 0 0

0 1 0 0

0 0 1 0

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80


Ring counters are used to construct “One-Hot” countersIt can be constructed for any

desired MOD numberA MOD-N ring counter uses N flip-flops connected in the

arrangement as shown in fig. a)In general ring-counter will

require more flip-flops than a binary counter for the same

MOD number

81


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Johnson Counter Or Twisted-ring counter

Johnson counter constructed exactly like a normal ring counter except that the inverted output of the last flip-flop is fed back to

first flip-flop

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Johnson Counter (Continue)

A

B

C

0 1 1 1

0 0 1 1

0 0 0 1

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Johnson Counter (Continue)

85

Chips for shift registers

• 74164 is a 8-bit SIPO shift register

74164

CLK

CLR

AB

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

86


• 74165 is a 8-bit PISO register

74165

CLK

CLK INH

SH/LDSER

D0 D1 D2 D3 D4 D5 D6 D7

Q7

Q7

87


• 74195 can be used as a 4-bit PIPO register

74195

CLK

SH/LD

JK

Q0 Q1 Q2 Q3

CLR

D0 D1 D2 D3

88


• 74194 is a 4-bit universal bidirectional shift register

74194

CLK

SR SER

CLRS0

S1

Q0 Q1 Q2 Q3

SL SER

D0 D1 D2 D3

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Counters• A counter is a register that goes through a

predetermined sequence of states upon the application of clock pulses.– Asynchronous counters – Synchronous counters

• Async. counters (or ripple counters)– the clock signal (CLK) is only used to clock the first FF.

– Each FF (except the first FF) is clocked by the preceding FF.

• Sync. counters, – the clock signal (CLK) is applied to all FF, which means that all

FF shares the same clock signal,

– thus the output will change at the same time.

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Flip-Flop Applications• Applications of Flip-Flop:-

– Counters• Asynchronous Counter

• Synchronous Counter

91

Asynchronous counters• Modulus (MOD) – the number of states it counts

in a complete cycle before it goes back to the initial state.

• Thus, the number of flip-flops used depends on the MOD of the counter (ie; MOD-4 use 2 FF (2-bit), MOD-8 use 3 FF (3-bit), etc..)

• Example: MOD-4 ripple/asynchronous up-counter.

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Asynchronous Counters (continue)

• The asynchronous counter that counts 4 number starts from 00011011 and back to 00 is called MOD-4 ripple (asynchronous) up-counter.

• Next state table and state diagram Present State Next State

Q1Q0 Q1Q0

00 01

01 10

10 11

11 00

00

01

10

11

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• MOD-4 Asynchronous up-counter

J Q

K Q

CLK

1 J Q

K Q

CLK

1

Q0 (LSB) Q1 (MSB)

CLKQ1 0 0 1 1 0 0 1 1 0

Q0 0 1 0 1 0 1 0 1 0

Binary 0 1 2 3 0 1 2 3 0


CLK

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• MOD-8 Asynchronous up-counter

J Q

K Q

CLK

1 J Q

K Q

CLK

1 J Q

K Q

CLK

1

C B A

A 0

B 0

C 0

CLK


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• Next state table and state diagramPresent

StateNext State

ABC ABC000 001001 010010 011011 100100 101101 110110 111111 000

0

1

2

3

7

6

5

4


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• Exercise:– Design a MOD-16 ripple up-counter

– Design a MOD-4 ripple down-counter

– Design a MOD-8 ripple down counter

– Design a MOD-16 ripple down counter


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• 2-bit Asynchronous down counter

J Q

K Q

CLK

1 J Q

K Q

CLK

1

B (LSB) A (MSB)

CLKB 0 1 0 1 0 1 0 1 0

A 0 1 1 0 0 1 1 0 0

Binary 0 3 2 1 0 3 2 1 0


CLK

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• So far, we have design the counters with MOD number equal to 2N, where N is the number of bit (N = 1,2,3,4….) (also correspond to number of FF)

• Thus, the counters are limited on for counting MOD-2, MOD4, MOD-8, MOD-16 etc..

• The question is how to design a MOD-5, MOD-6, MOD-7, MOD-9 which is not a MOD-2N (MOD 2N) ?

• MOD-6 counters will count from 010 (0002) to 510(1012) and after that will recount back to 010 (0002) continuously.


99

Asynchronous Counters• MOD-6 ripple up-counter (MOD 2N)Present

St.Next St.

ABC ABC000 001001 010010 011011 100100 101101 000(110)

01

23

5

4

Reset the state to 0002 when 1102 is detected

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• Circuit diagram for MOD-6 ripple up-counter (MOD 2N)

J Q

K CLR

Q

CLK

1 1 1

C B A

J Q

K CLR

Q

CLK

J Q

K CLR

Q

CLK

Detect the output atABC=110 to activate

CLR. NAND gate is used to detect outputs that generates ‘1’!

CLK

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Chip for Asynchronous counters

• 74293 IC for Asynchronous counter with Reset (MR1 and MR2) MR1

MR2Q0Q1Q2Q3

CP0

CP174293

J Q

K

CLR Q

CLK

1 1 1

Q0 Q1 Q2

J Q

K

CLR Q

CLK

J Q

K CLR

QCLK

1 J Q

K

CLR Q

CLK

Q3

MR1MR2

CP0

CP1

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Chip for Asynchronous counters (continue)

• Using 74293 IC to design MOD 16 asynchronous up-counter!

• Exercise: – use 74293 IC to design MOD-10 ripple up-counter

MR1

MR2

Q0Q1Q2Q3

CP0

CP174293

1 0 1 0

103


• Exercise:

– Determine the MOD for each configuration shown below?

MR1

MR2

Q0Q1Q2Q3

CP0

CP174293

MR1

MR2

Q0Q1Q2Q3

CP0

CP174293

1 0 1

104


• Determine the MOD for each configuration shown below? MR1

MR2

Q0Q1Q2Q3

CP0

CP174293

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Asynchronous counters• Disadvantages of Asynchronous Counters:-

– Propagation delay is severe for larger MOD of counters, especially at the MSB.

– Existence of ‘glitch’ is inevitable for MOD 2N counters.

– Difficult to design random counters (i.e:- to design circuit that counts numbers in these sequence 56723156723156….)

• Solution, use SYNCHRONOUS COUNTERS.

106

Synchronous counters• For synchronous counters, all the flip-flops are using the

same CLOCK signal. Thus, the output would change synchronously.

• Procedure to design synchronous counter are as follows:-STEP 1: Obtain the State Diagram. STEP 2: Obtain the Excitation Table using state

transition table for any particular FF (JK or D). Determine number of FF used.

STEP 3: Obtain and simplify the function of each FF input using K-Map.

STEP 4: Draw the circuit.

107

Synchronous counters• Design a MOD-4 synchronous up-counter, using JK FF.

STEP 1: Obtain the State transition Diagram

0

1

2

3

00

01

10

11Binary

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Synchronous countersSTEP 2: Obtain the Excitation table. Two JK FF are

used.

Present State Next State

A B A B JA KA JB KB

0 0 0 1 0 X 1 X

0 1 1 0 1 X X 1

1 0 1 1 X 0 1 X

1 1 0 0 X 1 X 1

OUTPUT TRANSITIONQN QN+1

FF INPUTJ K

0 0 0 X0 1 1 X1 0 X 11 1 X 0Excitation table

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Synchronous countersSTEP 3: Obtain the simplified function using K-Map

BA 0 1

0 0 1

1 X X

JA = B

BA 0 1

0 X X

1 0 1

KA = B

BA 0 1

0 1 X

1 1 X

JB = 1

BA 0 1

0 X 1

1 X 1

KB = 1

110

Synchronous countersSTEP 4: Draw the circuit diagram

JB Q

KB Q

CLK

1JA Q

KA Q

CLK

B (LSB) A (MSB)

111

Synchronous counters• Exercise:-

– Design MOD-4 sync up-counter using D flip-flop.

– Design MOD-8 sync up-counter using D flip-flop.

– Design MOD-8 sync up-counter. Use T FF for MSB, D FF for second bit and JK FF for LSB.

– Design MOD-16 sync up-counter using T flip-flop.

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Synchronous counters• Design a MOD-4 synchronous down-counter, using JK

FF?

STEP 1: Obtain the State transition Diagram

0

3

2

1

00

11

10

01Binary

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Synchronous counters– Obtain the Excitation table. Two JK FF are used.

Present St.

Next St.

A B A B JA KA JB KB

0 0

0 1

1 0

1 1

OUTPUT TRANSITIONQN QN+1

FF INPUTJ K

0 0 0 X0 1 1 X1 0 X 11 1 X 0

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Synchronous counters– Obtain the simplified function using K-Map

BA 0 1

0

1

JA =

BA 0 1

0

1

KA =

BA 0 1

0

1

JB =

BA 0 1

0

1

KB =

115

Synchronous counters– Draw the circuit diagram

JB Q

KB Q

CLK

JA Q

KA Q

CLK

B

A

116

Synchronous counters• Exercise:-

– Design MOD-4 sync down-counter using D flip-flop.

– Design MOD-8 sync down-counter using D flip-flop.

– Design MOD-8 sync down-counter. Use T FF for MSB, D FF for second bit and JK FF for LSB.

– Design MOD-16 sync down-counter using T flip-flop.

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Chip for synchronous counter 74163

74163

CLR

LOADENTENPCLK

D0 D1 D2 D3

Q0 Q1 Q2 Q3

RCO

EC303 - Chapter 2 LOGIC DESIGN & COMPUTER ARCHITECTUR

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Transcript of EC303 - Chapter 2 LOGIC DESIGN & COMPUTER ARCHITECTUR