Easily Build Designs Using Altera’s Video and Image Processing Framework

Click here to load reader

  • date post

    01-Jan-2016
  • Category

    Documents

  • view

    28
  • download

    2

Embed Size (px)

description

Easily Build Designs Using Altera’s Video and Image Processing Framework. 2010 Technology Roadshow. Agenda. What is the video framework?                 Six steps to building a video system Video design demo using SOPC Builder Summary    . Altera Video Design Framework. - PowerPoint PPT Presentation

Transcript of Easily Build Designs Using Altera’s Video and Image Processing Framework

Altera Video Design FrameworkProcessing Framework
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Agenda
Six steps to building a video system
Video design demo using SOPC Builder
Summary    
© 2010 Altera Corporation—Public
Altera Video Design Framework
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Altera Video Design Framework
*
*
Video processing especially as the world makes a transition to 1080p HD resolutions is a natural fit for FPGAs. Altera recognized this transition nearly 4 years ago and we invested in a video design framework to help our customers get their designs done faster. The result of this significant engineering investment was the 1080p video design framework – which edged out the Xilinx design tools to win the prestigious EDN Innovation Award for 2009.
While other FPGA vendors have some disparate video functions – Altera is the only vendor that gives you a design framework that includes 18 video functions, a streaming video interface standard, half dozen hardware verified reference designs and a range of video development kits.
Also we have FAEs trained in the complexities of video processing to help you get the development done faster.
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Video IP Building Blocks: IPS-Video
‘Interlacer’ core in v10.1
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Open, Low-Overhead, Interface Standard:
Avalon Streaming (ST) Video
*
*
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Portfolio of Reference Designs
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Video Development Kits
*
*
Building a Video System
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
General Video System Design Flow
Full Software Implementation
OK?
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Implementation
Always follow the steps!
1. Implement top-level HDL
2. Implement video output
Can be removed later if not required
4. Implement video input
6. Integrate video processing functions
*
OK?
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Hardware Implementation—Video Output
Test Pattern Generator
Use a TPG Instead of Video Source to Test Video Output
Clocked Video Output
Top level (HDL)
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Hardware Implementation—Nios II Processor
Test Pattern Generator
Clocked Video Output
Top level (HDL)
Add Nios II processor. Write Software for Control and Debug
LEDs
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Hardware Implementation—Video Input
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Hardware Implementation – Memory Controller
*
*
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Hardware Implementation – Video Processing
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Video Design Demo Using
© 2010 Altera Corporation—Public
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Summary
Altera video design framework enables rapid development
Mix and match existing IP—leverage Altera’s open interface standard
Automatically integrate embedded processors and arbitration logic
Leverage building block IP provided by Altera
Use existing reference designs as starting points
Rapid prototyping
*
For more information visit: www.altera.com
Thank you for viewing today’s program, Introducing 28-nm Stratix V FPGAs and HardCopy V ASICs: Built for Bandwidth brought to you by Altera Corporation.
If you'd like to learn more about this topic, you can click on the links located under the “Additional Resources” section of your player.
If you still have questions, please enter them in the question field located on your player and you will receive an email response within 3 business days.