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台大電子所 李致毅教授 -...
Transcript of 台大電子所 李致毅教授 -...
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Equalizers
Professor Jri Lee台大電子所 李致毅教授
Electrical Engineering DepartmentNational Taiwan University
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Outline
IntroductionPre-Emphasis and DriversPost-Emphasis and EqualizersDesign of Building BlocksCase Study
Reference: “Digital Communications” by John Proakis (4th Edition).
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[Courtesy, Srikanth Gondi]
High-Speed Data Transfer (Electrical)
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[Courtesy, Srikanth Gondi]
Serial Link Architecture
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[Courtesy, Srikanth Gondi]
Intersymbol Interference (ISI)
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Universal Expression of Wire Loss
Coefficients ks and kd vary significantly for different media.
For example, backplane traces suffer from skin effect more seriously.
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[Courtesy, Srikanth Gondi]
Loss Mechanisms in Microstrips
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Time-Domain Analysis of Pre-Emphasis
ISI occurs!
Insufficient bandwidth leads to ISI.
What happen if we force point to zero?
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Time-Domain Analysis of Pre-Emphasis
ISI gets reduced by boosting transition bits.
Two-Tap FIR Filter
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Time-Domain Analysis of Pre-Emphasis
0
1- α
- αTime (ns)
1
100 % EyeOpening
No Jitter
0 0.5 1
Am
plitu
deα = exp(−Tb/τ)For any arbitrary τ, we choose
Complete eye opening and zero transition jitter!(Of course, it is too good to be true!!)
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Frequency Response of Two-Tap FIR
b1)( sTesH −−= α
b2 cos21)( TsH ωαα −+=
)()()( bTtxtxtz −−= α
[ ]b1)()( sTesXsZ −−= α
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Multi-Tap FIR Filter with Zero-Forcing
Impulse response reveals what appears in the output.Since the actual waveform is a linear combination of all taps, properly selecting coefficients can eliminate ISI.
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Zero-Forcing Technique
Since , we have⎩⎨⎧ =
== ∑=
− elsewhere00for1
-nnknk
kxy
N
Na
⎥⎥⎥⎥⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢⎢⎢⎢⎢
⎣
⎡
=
⎥⎥⎥⎥⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢⎢⎢⎢⎢
⎣
⎡
⎥⎥⎥⎥⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢⎢⎢⎢⎢
⎣
⎡
+++
00
1
00
1-
0
1-
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01-1-22
1-2-1-2-21-2
-1--01-
12-2-1-01
2-1-2--1-0
M
M
M
M
LL
LL
MM
LL
MM
LL
LL
N
N
N
N
NNN
NNN
NNNN
NNN
NNN
xxxxxxxxxx
xxxxx
xxxxxxxxxx
aa
a
aa
Zero ISI requires infinite length.Zero forcing only occurs at sampling points (discrete behavior), issues such as transition jitter are not considered here.
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[Courtesy, Srikanth Gondi]
Equalizer Filter Design
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[Courtesy, Srikanth Gondi]
Second Order Structures
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[Courtesy, Srikanth Gondi]
Equalizer Filter: Intuitive Approach
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[Courtesy, Srikanth Gondi]
Parallel Path Approach
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Review of Prior Art
[Courtesy, Srikanth Gondi]
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[Courtesy, Srikanth Gondi]
RC Source Degeneration
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Conventional Filter Stage
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Filter Stage with Inductive Peaking
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[Courtesy, Srikanth Gondi]
Problem of Adaptation
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[Courtesy, Srikanth Gondi]
Rectifier & Integrator
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Case Study I
[Choi, 04]
Dual loop architecture to balance low- and high-frequency parts.
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Case Study II
[Gondi, 05]
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Case Study II
[Gondi, 05]