Dynamic Performance Analyses of Current Sharing Control for … · 2020. 9. 25. · Dynamic...

Dynamic Performance Analyses of Current

Sharing Control for DC/DC Converters

Juanjuan Sun

Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

Doctor of Philosophy in

Electrical Engineering

APPROVED

Fred C. Lee, Chairman Fei Wang Ming Xu Yilu Liu

Douglas J. Nelson

June 13, 2007 Blacksburg, Virginia

Keywords: current sharing, dynamic performance, high frequency,

distributed power systems

© 2007, Juanjuan Sun

Dynamic Performance Analyses of Current

Sharing Control for DC/DC Converters

Juanjuan Sun

(Abstract)

Paralleling operation of DC/DC converters is widely used in today’s distributed

power systems due to the request of high reliability and ease of standardization. Usually, it

is desired to distribute the load equally among paralleled converters. However, because of

limited component tolerances, as well as asymmetric layout or position of converters, their

output currents might be significantly different. Therefore, special provisions are usually

necessary to balance the load current equally among the paralleled modules. For this

purpose, different current sharing control methods have been proposed and practiced by

the industry.

It has been analyzed and demonstrated that active current sharing control methods

can achieve steady-state current balance with adequate accuracy; however, their dynamic

performance has not been clearly explored and compared. Meanwhile, the fundamental

relationship between the current sharing control and the voltage regulation control has not

been clarified for different control structures. In the first chapter of this dissertation, the

concept of output impedance is introduced as a powerful tool to investigate both of these

two aspects. Then in the second chapter, the influences on dynamic current sharing and

voltage regulation from the critical current sharing loop gain are analyzed from the output

impedances point of view. Three different control structures with active current sharing are

analyzed and compared from many aspects, such as dynamic current sharing and dynamic

voltage regulation performances. Among them, the dynamic current sharing response

speed of outer-loop current sharing scheme is inherently limited, while dual-loop and

inner-loop structures can achieve higher gain and bandwidth of the current sharing control

loop. Nevertheless, the dynamic current sharing performance always needs to be traded

with dynamic voltage regulation performance for all three structures. It is concluded that

the inner-loop current sharing scheme is superior for applications requiring good dynamic

current sharing performance after considering all aspects.

While the traditional modeling technique can handle the dynamic current sharing

analyses for low-frequency perturbations, it is not valid when the perturbation frequency is

close or higher than half of the switching frequency. However, the need of high-frequency

dynamic current sharing study also exists in reality. For example, due to the possibility of

extremely fast transients from the microprocessor, its power supply, multiphase voltage

regulator (VR), needs to face the dynamic current sharing issue with high-frequency

perturbations. A very special phenomenon has been observed that the large-magnitude

beat-frequency oscillations occur in the phase currents when the load transient frequency is

approaching to or higher than the switching frequency. This is a severe issue for the

industry since these oscillations greatly reduce a system’s reliability. Yet there is a lack of

related research to help people understand and deal with this issue. Therefore, it is essential

to study the high-frequency dynamic current sharing performance as well.

However, the conventional output impedance concept is no longer suitable for the

high-frequency analysis, because it does not include any beat-frequency information.

Therefore, to understand and study the beat-frequency related high-frequency dynamic

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current sharing issue, chapter three explores a new methodology of extended describing

functions. Similar as output impedance, the proposed extended describing function also

represents the terminal characteristic of a converter. However, this describing function

approach makes it possible to study circuit response which is not at the same frequency as

the perturbation. After reviewing the scenario of beat-frequency’s generation in the pulse-

width-modulator, an unconventional multi-frequency model is proposed to obtain related

describing functions. It is demonstrated that the dynamic current sharing error can now be

predicted up to the switching frequency. Moreover, critical design considerations and

tradeoffs can be identified based on the proposed model. To reduce the beat-frequency

oscillations while not impacting the voltage regulation feedback loop’s performance,

possible solutions are proposed and discussed. Among them, the coupled-inductor solution

is very promising due to many additional benefits. Simulation and experimental results are

provided as verifications.

Furthermore, if the load transient frequency goes much higher than the switching

frequency, which is also possible in VR applications, the dynamic current sharing issue

related to the higher-order beat-frequency oscillations becomes another concern.

Therefore, to complete the work, the proposed multi-frequency model is extended to cover

frequency range higher than the switching frequency in chapter four.

In summary, both low-frequency and high-frequency dynamic current sharing

performances are studied in this dissertation. The output impedance concept and its

extension in the form of extended describing function are utilized as the tools for

researches. With these powerful tools, more insights are obtained to help better design of a

paralleling system.

iv

TO MY HUSBAND

YANG QIU

v

Acknowledgments

I would like to express my sincere appreciation to my advisor, Dr. Fred C. Lee, for

his continued guidance, encouragement and support. It is an honor to be one of his students

here at the Center for Power Electronics Systems (CPES), one of the best research centers

in power electronics. In the past years, I am always amazed by his great intuition, broad

knowledge and accurate judgment. The most precious things I learned from him are the

ability of independent research and the attitude toward research, which can be applied to

every aspects of life and will benefit me for the rest of my life.

I am grateful to the other members of my advisory committee, Dr. Daan van Wyk,

Dr. Fei Wang, Dr. Ming Xu, Dr. Yilu Liu, and Dr. Douglas J. Nelson for their support,

comments, suggestions and encouragement.

In addition, I would also like to thank Dr. Ming Xu for his enthusiastic help during

my research at CPES. His selfless friendship and leadership helped to make my time at

CPES enjoyable and rewarding. From him, I learned so much not only in the knowledge of

power electronics but also in the research methodologies. His valuable suggestions helped

to encourage my pursuing this degree.

I am especially indebted to my colleagues in the DPS group, the ARL group and the

VRM group. It has been a great pleasure to work with the talented, creative, helpful and

dedicated colleagues. I would like to thank all the members of my teams: Dr. Wei Dong,

Dr. Bing Lu, Dr. Shuo Wang, Dr. Francisco Canales, Dr. Bo Yang, Dr. Qun Zhao, Dr.

Kaiwei Yao, Dr. Jia Wei, Mr. Mao Ye, Dr. Jinghai Zhou, Dr. Yuancheng Ren, Mr. Yu

Meng, Dr. Ching-Shan Leu, Mr. Doug Sterk, Mr. Kisun Lee, Mr. Julu Sun, Dr. Xu Yang,

vi

Mr. Yonghan Kang, Mr. Chuanyun Wang, Mr. Arthur Ball, Mr. Andrew Schmit, Mr.

David Reusch, Mr. Yan Dong, Mr. Jian Li, Mr. Yucheng Ying, Mr. Yi Sun, Mr. Qiang Li,

Dr. Yugang Yang, and Dr. Yan Xing. It was a real honor working with you guys.

I would like to thank my fellow students and visiting scholars for their help and

guidance: Dr. Peter Barbosa, Dr. Jinghong Guo, Dr. Lingyin Zhao, Dr. Rengang Chen, Dr.

Bin Zhang, Dr. Xigen Zhou, Dr. Qian Liu, Mr. Dianbo Fu, Mr. Xiangfei Ma, Dr. Wei

Shen, Dr. Haifei Deng, Ms. Yan Jiang, Dr. Huiyu Zhu, Mr. Pengju Kong, Dr. Jian Yin, Dr.

Wenduo Liu, Dr. Ning Zhu, Dr. Zhiye Zhang, Ms. Jing Xu, Ms. Yan Liang, Ms. Michele

Lim, Dr. Chucheng Xiao, Mr. Hongfang Wang, Mr. Ya Liu, Mr. Bin Huang, and Mr. Rixin

Lai.

I would also like to thank the wonderful members of the CPES staff who were

always willing to help me out, Ms. Teresa Shaw, Ms. Linda Gallagher, Ms. Teresa Rose,

Ms. Ann Craig, Ms. Marianne Hawthorne, Ms. Elizabeth Tranter, Ms. Michelle

Czamanske, Ms. Linda Long, Mr. Steve Chen, Mr. Robert Martin, Mr. Jamie Evans, Mr.

Dan Huff, Mr. Callaway Cass, and Mr. David Fuller.

My heartfelt appreciation goes toward my parents, Xiangsheng Sun and Huiquan Liu,

who have always provided support and encouragement throughout my further education.

Finally, with deepest love, I would like to thank my husband, Dr. Yang Qiu, who not

only selflessly guided my researches during the past 5 years, but also supported and

encouraged me all the time no matter what difficulties are encountered in my life.

vii

This work was supported by the PMC consortium (Analog Devices, C & D

Technologies, Crane Aerospace and Electronics, Delta Electronics, Freescale

Semiconductor, Hipro Electronics, Infineon, Intel, International Rectifier, Intersil, Linear

Technology, National Semiconductor, NXP Semiconductors, Primarion, Renesas, and

Texas Instruments), the U.S. Army Research Lab (ARL), and the Engineering Research

Center Shared Facilities supported by the National Science Foundation under NSF Award

Number EEC-9731677. Any opinions, findings and conclusions or recommendations

expressed in this material are those of the author and do not necessarily reflect those of the

National Science Foundation.

This work was conducted with the use of SIMPLIS software, donated in kind by

Transim Technology of the CPES Industrial Consortium.

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Table of Contents

Chapter 1. Introduction.......................................................................................................1

1.1 Distributed Power Systems.......................................................................................1

1.2 Review of the Passive Droop Current Sharing Methods ..........................................5

1.2.1 Implementations of the Droop Methods.............................................................7

1.2.2 Voltage Regulation Issue of the Droop Methods .............................................12

1.2.3 Dynamic Current Sharing Issue with Droop Methods.....................................16

1.3 Impedance Approach to Investigate Dynamic Current Sharing .............................17

1.4 Current Sharing with Active Controls ....................................................................22

1.4.1 Active Current Sharing Control Configurations..............................................22

1.4.2 Active Current Sharing Control’s Influence on Output Impedances ...............29

1.5 Dynamic Current Sharing Issue with Repetitive Loads .........................................33

1.6 Dissertation Objective and Outlines .......................................................................44

Chapter 2. General Study about the Dynamic Current Sharing Performance............45

2.1 Introductions ...........................................................................................................45

2.1.1 Introduction of the Output-Impedance Approach............................................46

2.1.2 An Example of Applying the Output-Impedance Approach .............................48

2.2 Dynamic Current Sharing Analyses with Active Current Sharing Controls ..........56

2.2.1 Outer-Loop Current Sharing Control ..............................................................57

2.2.2 Dual-Loop Current Sharing Control ...............................................................75

2.2.3 Inner-Loop Current Sharing Control...............................................................91

2.2.4 Summary.........................................................................................................103

ix

2.3 Experimental Implementations.............................................................................105

2.4 Summary...............................................................................................................108

Chapter 3. Current Sharing Issue under High-Frequency Dynamics ........................110

3.1 Generation and Attenuation of the Beat-Frequency Oscillations .........................117

3.2 Multi-Frequency Model for Current Mode Controlled Converters ......................135

3.3 Multi-Frequency Model for Multiphase Interleaved Buck VRs...........................149

3.4 Prediction of Dynamic Current Sharing Error for Both Perturbation and Beat

Frequency Components ..................................................................................................161

3.5 Reduce the Beat-Frequency Oscillations in Phase Currents.................................173

3.6 Summary...............................................................................................................190

Chapter 4. Current Sharing Study under Ultra-High-Frequency Dynamics ............192

4.1 Observations .........................................................................................................192

4.2 The Extended Multi-Frequency Model for 2-phase VR.......................................197

4.3 The Extended Multi-Frequency Model for N-phase VR ......................................200

4.4 Avoid the Worst Case by Making Use of the Cancellation of Higher-Order Beat-

Frequency Components ..................................................................................................205

4.5 Summary...............................................................................................................207

Chapter 5. Conclusions....................................................................................................209

5.1 Conclusions...........................................................................................................209

5.2 Future Works ........................................................................................................216

References .........................................................................................................................217

Vita ....................................................................................................................................225

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List of Tables

Table 2.1. Values of passive components in Figure 2.2. .....................................................49

Table 2.2. Resistances comparison: without and with droop method..................................54

Table 2.3. Summary for outer-loop current sharing control. ...............................................74

Table 2.4. Summary for dual-loop current sharing control..................................................91

Table 2.5. Summary for inner-loop current sharing control. .............................................102

Table 2.6. Comparison of three active current sharing structures......................................104

Table 3.1. Summary of the simulation results in Figure 3.53: |io(fp)|=10A........................168

Table 3.2. Inductance comparison for ωp and ωbeat with 2-phase coupling. ......................184

Table 3.3. Inductance comparison for ωp and ωbeat with N-phase coupling.......................186

Table 5.1. Comparison of three active current sharing structures......................................211

xi

List of Figures

Figure 1.1. A typical distributed power system. ....................................................................2

Figure 1.2. Paralleled converters with current limit functions...............................................4

Figure 1.3. A paralleling system with the droop current sharing method..............................6

Figure 1.4. Output characteristics of paralleled modules with the droop method. ................6

Figure 1.5. Output characteristics of paralleled buck converters running in DCM. ..............8

Figure 1.6. Output characteristics of series resonant converters............................................8

Figure 1.7. Droop realization for a current-mode converter with low voltage compensator

DC gain..........................................................................................................................10

Figure 1.8. Droop realized via the output current feedback.................................................11

Figure 1.9. With droop method, steady-state current sharing accuracy is depended on the

voltage reference set point accuracy..............................................................................13

Figure 1.10. A high cost distributed power system with Vicor’s VI200 converters............14

Figure 1.11. A high cost droop implementation with extreme accuracy for the voltage

references.......................................................................................................................14

Figure 1.12. A fair cost distributed power system with Intel’s VRM specification. ...........15

Figure 1.13. Practical accuracy leads to insufficient current sharing in paralleled VRM

system. ...........................................................................................................................15

Figure 1.14. Paralleled converters under single-step load transients. ..................................17

Figure 1.15. Dynamic current sharing performance without and with droop current sharing

. ......................................................................................................................................17

Figure 1.16. Output impedances of paralleled modules.......................................................19

Figure 1.17. Output impedances of paralleled modules with added droop resistors. ..........20

xii

Figure 1.18. Dynamic current sharing performance without and with droop current sharing.

.......................................................................................................................................21


.......................................................................................................................................21

Figure 1.20. Master-slave configuration. .............................................................................23

Figure 1.21. Master-slave current sharing with current-mode control.................................24

Figure 1.22. Fatal failure of the system would occur because of the master module’s

malfunction....................................................................................................................25

Figure 1.23. Automatic average current sharing technique proposed by K. Small. ............27

Figure 1.24. Democratic current sharing with diodes connecting the current sharing bus..28

Figure 1.25. Output impedances of paralleled modules with active current sharing control.

.......................................................................................................................................29

Figure 1.26. Two paralleled modules with an active current sharing control scheme.........30

Figure 1.27. Output impedances improvements with active current sharing control. .........31

Figure 1.28. Current sharing improvement with active current sharing control..................32

Figure 1.29. Output impedances improvements with active current sharing control. .........33

Figure 1.30. Interleaved multiphase buck VR with repetitive loads....................................34

Figure 1.31. Dynamic current sharing with peak-current mode control: tested under low-

frequency transients: switching frequency fs=300kHz; load transient frequency

fp=10kHz........................................................................................................................35

Figure 1.32. Beat-frequency oscillations under high-frequency repetitive perturbations:

tested with peak-current mode control. Switching frequency fs=300kHz; load transient

frequency fp=280kHz.....................................................................................................35

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Figure 1.33. Blue screen error due to current unbalance in highly dynamic CPU load......37

Figure 1.34. A single-phase, open-loop buck converter. .....................................................38

Figure 1.35. Spectra of , , and under different relationship between fp and fs. .........39 cv dv ov

Figure 1.36. Time domain waveforms with different relationship between fp and fs...........39

Figure 1.37. Multifrequency model for the single-phase, closed-loop buck converter. ......40

Figure 1.38. Circuit and waveforms for 2-phase interleaved buck VR: fp=990kHz,

fs=1MHz. .......................................................................................................................41

Figure 1.39. Output impedances and their extension for different frequency components. 42

Figure 2.1. Use output impedances to evaluate dynamic current sharing performance. ....46

Figure 2.2. A paralleling system of two boost converters: without current sharing. ...........49

Figure 2.3. Control-to-output transfer function of boost converter #1. ...............................50

Figure 2.4. Voltage feedback loop gain of boost converter #1. ...........................................50

Figure 2.5. Dynamic performance of the paralleling system without current sharing

control............................................................................................................................51

Figure 2.6. The paralleling boost system with passive droop current sharing. ....................52

Figure 2.7. Dynamic current sharing performance is not improved with the droop method.

.......................................................................................................................................53

Figure 2.8. The output impedance approach for paralleling system with active current

sharing control. ..............................................................................................................56

Figure 2.9. Outer-loop current sharing control with two paralleled converters..................58

Figure 2.10. The small-signal model of module #1. ...........................................................60

Figure 2.11. Further simplified small-signal model of module #1. ....................................61

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Figure 2.12. Simplified small-signal model of the paralleling system with outer-loop

current sharing. ..............................................................................................................62

Figure 2.13. The paralleling boost system with outer-loop current sharing. .......................65

Figure 2.14. Change of output impedances after applying outer-loop current sharing

control: Zo1 and Zo2 – without current sharing; Zcs1 and Zcs2 – with current sharing

control (Tcs crossovers at 30 Hz). .................................................................................66

Figure 2.15. The dynamic current sharing responses comparison. ......................................66

Figure 2.16. Low Tcs bandwidth is resulted with a simple Hcs.............................................67

Figure 2.17. High Tcs bandwidth is achieved with proposed Hcs. ........................................68

Figure 2.18. Change of output impedances after applying outer-loop current sharing

control: Zo1 and Zo2 – without current sharing; Zcs1 and Zcs2 – with current sharing

control (Tcs crossovers at 6 kHz). ..................................................................................69

Figure 2.19. The dynamic current sharing responses comparison. ......................................70

Figure 2.20. Output impedances’ change with outer-loop current sharing (faster Tcs

design). ..........................................................................................................................73

Figure 2.21. Total output impedance comparison: Zo – without CS, Zcso – with CS (faster

Tcs design)......................................................................................................................73

Figure 2.22. Output voltage response with outer-loop current sharing................................74

Figure 2.23. Dual-loop current sharing control structure.....................................................75

Figure 2.24. Applying dual-loop current sharing to the paralleling boost system...............78

Figure 2.25. Tcs design for dual loop current sharing control. .............................................79

Figure 2.26. Change of output impedances after applying dual-loop current sharing control:

Zo1 and Zo2 – without CS; Zcs1 and Zcs2 – with dual loop CS. ........................................80

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Figure 2.27. Dynamic current sharing performance comparison.........................................80

Figure 2.28. Comparison of the total output impedances with dual-loop and outer-loop

controls: OLR case– Tcs crossover at 30 Hz; OLR case– Tcs crossover at 18 kHz;. .....82

Figure 2.29. Output voltage responses comparison between dual-loop and outer-loop

controls. .........................................................................................................................82

Figure 2.30. Mismatching of the modules leads to more poles and zeroes in Gvd1/ZOL2. ....84

Figure 2.31. Mismatching of the modules leads to more poles and zeroes from Tv1 and Tv2.

.......................................................................................................................................84

Figure 2.32. Mismatching of the modules leads to delays in Tcs around the voltage loop

bandwidth. .....................................................................................................................85

Figure 2.33. Possible issue for Tcs design with dual-loop current sharing...........................86

Figure 2.34. Output currents and voltage responses with dual-loop current sharing in

Figure 2.33(b). ...............................................................................................................86

Figure 2.35. Dual loop with noise perturbation on the current sharing bus.........................88

Figure 2.36. Output voltage’s response to noise perturbation on the current sharing bus for

dual loop current sharing structure. ...............................................................................89

Figure 2.37. Output voltage’s response to noise perturbation on the current sharing bus for

outer loop current sharing structure...............................................................................90

Figure 2.38. Inner-loop current sharing control structure. ...................................................92

Figure 2.39. Inner-loop current sharing control with voltage loop open. ............................93

Figure 2.40. Inner-loop current sharing control with voltage loop closed...........................95

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Figure 2.41. Change of output impedances after applying inner-loop current sharing

control: ZOL1 and ZOL2 – open-loop impedances; Zcc1 and Zcc2 – with current loop

closed while voltage loop open. ....................................................................................97

Figure 2.42. Change of output impedances after applying inner-loop current sharing

control: Zcc1 and Zcc2 – with current loop closed while voltage loop open; Zcs1 and Zcs2

– with both current and voltage loop both closed; ........................................................97

Figure 2.43. Dynamic current sharing for two paralleled converters with inner-loop current

sharing. ..........................................................................................................................98

Figure 2.44. Overall impedance comparison between inner-loop and outer-loop structures.

.....................................................................................................................................100

Figure 2.45. Inner loop current sharing scheme with noise perturbation on the current

sharing bus...................................................................................................................101

Figure 2.46. Output voltage’s response to noise perturbation on the current sharing bus

with inner-loop current sharing scheme. .....................................................................101

Figure 2.47. The DPS system for a high-voltage, pulsed-power charging application. ....106

Figure 2.48. The hardware implementation of the whole charging system. ......................107

Figure 2.49. The experimental waveforms of the charging system. ..................................107

Figure 3.1. Load profile for multiphase VR systems. ........................................................110

Figure 3.2. Output impedances for a 2-phase interleaved buck VR. .................................111

Figure 3.3. Use output impedance to predict dynamic current sharing performance when

the perturbation frequency, fp, is lower than fs/2. ........................................................111

Figure 3.4. Time domain waveforms with 10-kHz repetitive load transient. ....................112

Figure 3.5. Unexplainable phenomenon when fp is close to fs. ..........................................114

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Figure 3.6. High-frequency dynamic current sharing issue for an industry demon-board,

tested on a 4-phase interleaving buck VR with fs=273kHz.........................................115

Figure 3.7. A single-phase, 1MHz open-loop buck converter. ..........................................117

Figure 3.8. The beat-frequency component can be ignored when fp<<fs. ..........................118

Figure 3.9. The beat-frequency component becomes dominant when fp is close to fs. ......119

Figure 3.10. The signal flow paths of different frequency components in Figure 3.7.......119

Figure 3.11. A single-phase, 1MHz closed-loop buck converter.......................................120

Figure 3.12. Feedback loops of Figure 3.11 considering the beat-frequency components.

.....................................................................................................................................120

Figure 3.13. The beat-frequency component is effectively attenuated by feedback loop gain

in a single-phase, closed-loop buck converter when fp>fs/2. .......................................121

Figure 3.14. A 2-phase interleaved, 1MHz open-loop buck VR. ......................................122

Figure 3.15. Signal flow paths of Figure 3.14 considering the beat-frequency components.

.....................................................................................................................................123

Figure 3.16. The fs-fp component is cancelled at vo in a 2-phase interleaved, open-loop buck

VR. ..............................................................................................................................123

Figure 3.17. Signal flow path of io1....................................................................................124

Figure 3.18. The fs-fp oscillations are severe at io1 in a 2-phase interleaved, open-loop buck

VR. ..............................................................................................................................125

Figure 3.19. The fs-fp oscillations are severe at io1 and io2 but unobservable in vo for a 2-

phase interleaved, open-loop buck VR........................................................................126

Figure 3.20. A 2-phase interleaved, 1MHz average-current-mode-controlled buck VR...127

Figure 3.21. The simplified model for Figure 3.20............................................................127

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Figure 3.22. Simplified signal flow path of io1 and io2 in Figure 3.20 when fp fs. ...........128

Figure 3.23. Attenuation of beat-frequency for multiphase, average-current-mode-

controlled VR. .............................................................................................................129

Figure 3.24. A 2-phase interleaved, 1MHz peak-current-mode-controlled buck VR with

perturbations. ...............................................................................................................130

Figure 3.25. Attenuation of beat-frequency for multiphase, peak-current-mode-controlled

VR. ..............................................................................................................................131

Figure 3.26. Response of io1 as fp changes from low to high frequency with peak-current

mode control................................................................................................................132

Figure 3.27. Simulation circuit for a 2-phase interleaving peak-current-mode controlled

buck VR.......................................................................................................................133

Figure 3.28. The simulated response of io1(fs-fp)/io(fp) for a 2-phase interleaved, peak-

current-mode-controlled buck VR...............................................................................134

Figure 3.29. A single-phase, peak-current-mode-controlled buck VR. .............................136

Figure 3.30. Multi-frequency model for a single-phase peak-current-mode controlled buck

converter. .....................................................................................................................137

Figure 3.31. PWM function of the peak-current mode control..........................................139

Figure 3.32. The PWM function: from the control voltage to duty cycle..........................140

Figure 3.33. Frequency domain relationship between the control voltage and the duty

cycle.............................................................................................................................141

Figure 3.34. Frequency-domain relationship between and . .....................................141 Li cv

Figure 3.35. Frequency-domain model for peak-current-mode control with the outer

voltage loop open. .......................................................................................................142

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Figure 3.36. The small-signal model of peak-current mode controlled PWM comparator.

.....................................................................................................................................144

Figure 3.37. Complete small-signal model of a single-phase, peak-current-mode controlled

buck converter, with high-frequency load current perturbation..................................145

Figure 3.38. Prediction and attenuation of the beat-frequency component in a 1MHz

single-phase peak-current-mode-controlled buck VR.................................................148

Figure 3.39. A 2-phase interleaved buck VR with peak-current mode control. ................150

Figure 3.40. The small-signal models of PWM comparators for a 2-phase interleaved buck

VR using peak-current mode control. .........................................................................150

Figure 3.41. The multi-frequency model of Figure 3.39....................................................151

Figure 3.42. ωbeat component part of a 2-phase interleaved buck VR. ..............................152

Figure 3.43. Waveforms of )(1 beatov ω , )(2 beatov ω and )( beatov ω with symmetric phases. 153

Figure 3.44. Simplified multi-frequency model for 2-phase buck VR with peak-current

mode control................................................................................................................155

Figure 3.45. Terminal characteristics for a 2-phase buck considering beat-frequency

components..................................................................................................................157

Figure 3.46. Simplified terminal characteristics for a 2-phase interleaved buck VR. .......159

Figure 3.47. Multifrequency model to calculate X1 and X2................................................160

Figure 3.48. The bode plot of Zcs1 and Zcs2. .......................................................................163

Figure 3.49. Dynamic current sharing error at fp. ..............................................................164

Figure 3.50. Bode plot of X1 and X2. ..................................................................................165

Figure 3.51. Dynamic current sharing error at beat-frequency..........................................166

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Figure 3.52. Evaluate dynamic current sharing performance for both fp and fbeat

components..................................................................................................................167

Figure 3.53. Simulation waveforms of dynamic current sharing error with different fp....168

Figure 3.54. The model from ip(fp) to iL1(fbeat). ..................................................................170

Figure 3.55. |iL1(fbeat)/io(fp)| for 2-phase interleaved buck VR............................................171

Figure 3.56. Smaller Se is preferred to reduce fbeat oscillations..........................................172

Figure 3.57. An example of the notch filter design............................................................174

Figure 3.58. Design the notch filter to make |iL1(fbeat)/io(fp)| below 0 dB...........................175

Figure 3.59. Improvement of the beat-frequency oscillations with notch filter solution...176

Figure 3.60. The average-current mode control.................................................................177

Figure 3.61. The average-current mode control leads to smaller beat-frequency oscillations.

.....................................................................................................................................178

Figure 3.62. Simulation comparison of average and peak current mode control. .............178

Figure 3.63. Change the switching frequency to reduce beat-frequency oscillations........179

Figure 3.64. Change the interleaving operation to reduce fbeat oscillations: fp=990kHz,

fs=1MHz. .....................................................................................................................179

Figure 3.65. Using inversely coupled inductor in multiphase VRs. ..................................181

Figure 3.66. Equivalent circuit of Figure 3.65(a)...............................................................183

Figure 3.67. Small-signal model of Figure 3.66 for ωp components. ................................183

Figure 3.68. Small-signal model of Figure 3.66 for ωbeat components. .............................183

Figure 3.69. The ratio of fbeat oscillations between non-coupled and 2-phase coupled

inductor case................................................................................................................185

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Figure 3.70. The ratio of fbeat oscillations between non-coupled and N-phase coupled

inductor case................................................................................................................187

Figure 3.71. The experimental waveforms of the fbeat oscillations: fs=273kHz, fp=260kHz,

transient inductance=120nH, load current jumps from 5 to 15A. Channel 1: iL1

(25A/div); Channel 2: iL3 (25A/div); Channel 3: vo (50mv/div); Channel 4: io

(10A/div). ....................................................................................................................188

Figure 4.1. A 2-phase VR system subjected to load transients, fs=1MHz. ........................192

Figure 4.2. Simulation waveforms of the phase currents in a 1-MHz 2-phase interleaved

buck VR with 5A sinusoidal perturbation in load currents. ........................................193

Figure 4.3. Spectra with different perturbation frequencies. .............................................195

Figure 4.4. Using terminal characteristics for higher order beat frequency study.............196

Figure 4.5. Simplified kωs-ωload frequency component model for 2-phase buck. .............197

Figure 4.6. Simplified kωs-ωload component model for 2-phase buck when k is an odd

number.........................................................................................................................198

Figure 4.7. Zcso of the VR leads to the higher magnitude of 3rd-order beat-frequency

oscillations...................................................................................................................199

Figure 4.8. Simulation waveforms of the phase currents in a 1-MHz 2-phase buck VR with

5A sinusoidal perturbation in load currents: fload=1.99MHz, fs=1MHz. .....................200

Figure 4.9. N-phase interleaved, peak-current mode controlled buck VR.........................201

Figure 4.10. Small signal model of the kωs-ωload components for a N-phase interleaved VR.

.....................................................................................................................................201

Figure 4.11. The cancellation of kωs-ωload component with 4-phase at different fload........203

xxii

Figure 4.12. Experimental waveforms of a 4-phase interleaved buck VR with fs=295kHz.

Load current jumps from 0 to 10A. Channel 1: iL1 (25A/div); Channel 2: iL3 (25A/div);

Channel 4: io (10A/div). ..............................................................................................204

Figure 4.13. Change the phase number to avoid the worst scenario (5-A sinusoidal

perturbation was added at load current for all simulations). .......................................206

Figure 5.1. Output impedances of the paralleled modules.................................................210

Figure 5.2. Output impedance concept is expanded for beat-frequency studies................213

xxiii

Chapter 1. Introduction

1.1 Distributed Power Systems

With the development of information technology, telecom, computer and network

systems have become a large market for power supply industry. Recent statistic data show

that the demands for these systems are continuously increasing [1]. Meanwhile, because of

the improving of integrated circuit technology, more powerful and compact silicon chips

are becoming available for the telecom and computer equipments. Therefore, the power

supplies for the telecom, computer and network applications are required to provide more

power with less size and cost [2][3].

To meet these requirements, the distributed power system (DPS) is widely adopted.

Instead of using a single bulky power supply to provide the final voltages required by the

load, the distributed power system is characterized by distribution of the power processing

functions among many power processing units [4]. One typical DPS structure is the

intermediate bus structure [5][6], as shown in Figure 1.1. In this system, the voltages that

are needed for loads are generated through two stage approach. In first stages, several

power factor correction (PFC) modules and front-end DC/DC converters are paralleled

together to generate the intermediated bus voltage, which is normally 48 V, or 12 V. After

that, the following point-of-load (POL) converters transfer the intermediate bus voltage

into the voltages that are needed by different loads. Because of this modular approach,

DPS system has many advantages comparing with conventional centralized power system,

such as less distribution loss, faster current slew rate to the loads, better standalization and

ease of maintenance [7][8].

1

Juanjuan Sun Chapter 1. Introduction

AC

AC line

POL Converter

Load

VRM CPU

PFCPFC Front EndDC/DC

Front EndDC/DC

PFCPFC

PFCPFC

Front EndDC/DC

Front EndDC/DC

Front EndDC/DC

Front EndDC/DC

48V DC

VRMOn-board converter

400V DC

Figure 1.1. A typical distributed power system.

Paralleling, as shown in Figure 1.1, for both front-end and POL converters, has been

used successfully in various power systems. The paralleled modules can be centrally

located to replace a centralized power supply. Such a configuration is often referred to as a

modular power supply system. In a DPS with an intermediate bus, paralleled modules can

be used for the front-end and/or load converters. In either case, paralleling is used to

achieve the following characteristics [9]:

• Thermal management: In the parallel configuration, each power processing unit

handles only a part of the total power. Since less power is dissipated in each unit,

the thermal design is simplified.

• Reliability: Paralleling reduces electrical and thermal stresses on semiconductor

devices. Although the number of components in a parallel structure is increased,

the overall system reliability is improved.

• Redundancy: An important characteristic of parallel operation is the possibility of

configuring a redundant system using more modules than the minimum required

by the load. Usually N+1 modules are used, where N is the minimum number of

2


modules required in the high-reliability applications, including mainframe

computer, space and military applications. With one module fails to supply the

output, the system is able to cut it off without impacting the load.

• Modularity: The parallel structure is very suitable for modular system designs.

The advantages of modular design include eases of system reconfigurations and

flexibilities. For example, if the power demand is increased, additional modules

can be added to provide the required power. Since only standard modules need to

be designed, the system development time as well as the engineering and

manufacturing costs is reduced, and safety approvals can be obtained more

quickly.

• Maintainability: A properly designed parallel configuration allows the on-line

replacement (hot-swapping) of defective modules. This provides means for non-

interrupting maintenance and repair, a very desirable feature in high-reliability

systems operating in a continuous fashion.

• Size reduction: Modular design can provide increased power density because

lower power modules can operate at higher frequencies with reduced filter

component size. Interleaving (phase-shifting of clock signals) of paralleled

modules increases the ripple frequency, leading to reduction of the overall filter

size.

However, it is the nature of voltage sources that only one unit can establish the

voltage level in a paralleling system. The output resistances of the power supplies are

extremely low. Thus, even a small difference in the output voltage between the paralleled

modules will cause the one that is a few milli-volts higher to hog all the current. The lower

3


the output voltage of the module, the more severe this problem is. Besides, even with the

same voltage references, the steady-state current sharing error is determined by the

difference of two parallel modules’ output DC resistance.

+_LoadLoadRo1

Vref2+_

Vref1

Io1

Vo

Ro2

+

-

Module #1

Module #2 Io2

Io

Vref3+_

Ro3

Module #3 Io3

(a) A paralleling system without current sharing scheme.

Io

Vo

Vref1Vref2Vref3

Io3

Io1, Io2

Ro1

Ro2Ro3

(b) The steady-state current distribution among modules.

Figure 1.2. Paralleled converters with current limit functions.

4


In the extreme case, as any module reaches its capacity limit, its current limit

circuitry is activated, causing its output voltage to drop and the current flows from the

other modules to increase to the load [9]. Figure 1.2 demonstrates this situation, where

Vref1, Vref2 and Vref3 are the open-load output voltages, and Ro1, Ro2 and Ro3 are the output

resistances of three power supplies respectively. Only one module ends up controlling the

voltage while the others “overloaded” into their current-limiting mode. Of course, there is

no current sharing at all except for the units which are in current limiting, and it could be

expected that the dynamic load regulation, particularly as each current limit threshold is

passed, would be less than desirable.

With unequal load sharing, the stress placed on the individual modules will be

imbalanced, resulting in some units operating with higher temperatures — a recognized

contributor to reduced reliability. Therefore, the challenge in paralleling modular supplies

is to ensure predictable, uniform current sharing-regardless of load levels and the number

of modules.

1.2 Review of the Passive Droop Current Sharing Methods

In the past, a variety of current sharing approaches have been proposed and practiced

by the industry, and a complementary classification of the existing current sharing methods

for DC/DC converters has been documented [11]. Among them, the simplest and most

straightforward way is the droop method. As the word “droop” implies, this method of

paralleling is accomplished by designing the individual power modules with a finite output

resistance, Rdroop, so that the output voltage falls slightly as the load current is increased.

5


Figure 1.3 illustrates the basic concept of droop method. Figure 1.4 demonstrates

how increasing Rdroop improves the current sharing accuracy. In Figure 1.3(a), the steady-

state current sharing error is calculated as:

21

12

21

2121

)()(2

oo

ooo

oo

refrefoo RR

RRIRRVV

II+

−⋅+

+

−⋅=− . (1.1)

+_LoadLoad

Ro1

Vref2+_

Vref1

Io1

Vo

Ro2

+

-

Module #1

Module #2 Io2

Io

-+_LoadLoad

Ro1

Vref2 +_

Vref1

Io1

Vo

Ro2

+

Module #1

Module #2 Io2

Io

Rdroop

Rdroop

(a) Without droop. (b) With droop.

Figure 1.3. A paralleling system with the droop current sharing method.

Ro1

Io2

Io

Vo

Io1

#2 #1

Io/2Ro2

Vo Vref2 Vref1

Io2

Io

Vo

Io1

#2 #1

Io/2

Vo Vref2 Vref1

Rdroop+Ro1Rdroop+Ro2

(a) Without Rdroop. (b) With Rdroop.

Figure 1.4. Output characteristics of paralleled modules with the droop method.

The voltage regulation is determined by:

6


21

21

21

1221

oo

ooo

oo

oreforefo RR

RRIRR

RVRVV

+⋅

++

+= . (1.2)

After adding the droop resistor, Rdroop, the original output impedances becomes

Ro1+Rdroop and Ro2+Rdroop. From (1.1), it is clear demonstrated that with higher output

resistance values, the current sharing error is reduced. Not requiring any communication

links between the paralleled modules is the major benefit of droop methods. The

disadvantages are also obvious: based on (1.2), the voltage regulation has to be degraded to

achieve fairly good current sharing, and it’s difficult to achieve current sharing between

modules with different power ratings [12]. In the remaining of this section, the details

about the implementations and limitations of the droop methods are discussed.

1.2.1 Implementations of the Droop Methods

The droop resistance, Rdroop, can be implemented in many different ways

[13][14][15][16]. The different implementations of droop method and their characteristics

are briefly introduced in the following part of this section.

(a) Converters with Inherent Droop Features

A simple scheme to set up a parallel system is to choose converter modules with a

droop feature. Some converters, such as buck and boost converters operating in the

discontinuous inductor current mode (DCM), have the inherent load-sharing ability, and

are able to be used in a paralleling system without tight regulation requirements [13].

Figure 1.5 gives an example of the output characteristics of two paralleled buck converters

running in DCM. Because of the inherent droop features, certain degree of current balance

is obtained without extra effort.

7


CCM

DCM

Io

Vo

Boundary

Io1

Io2

Vo

CCM

DCM

Io

Vo

Boundary

Io1

Io2

Vo

Figure 1.5. Output characteristics of paralleled buck converters running in DCM.

Another category of converters with the inherent droop functions are the resonant

converters. As the output characteristics shown in Figure 1.6, because the relationship

between the output voltage and the load resistance are nonlinear for a certain switching

frequency, the resulted I-V performance has an inherent droop function. Therefore, it is

possible to utilize this droop behavior to share current among resonant converters.

f

Vo

f0

Smaller RLoad

Io

Vo

(a) DC gain characteristic. (b) I-V characteristic.

Figure 1.6. Output characteristics of series resonant converters.

8


(b) Voltage Droop due to External Series Resistances

In this parallel scheme, the output droop is implemented by adding external resistors

to each module. All of the paralleled supplies have an initial setting that, via a

potentiometer, are made almost identical. A resistor is placed in series with the output to

provide an I*R voltage drop in the output [14].

Obviously, the major disadvantage of this approach is the high power dissipation on

the series resistors if the droop in output voltage is large. For example, one supply in a

redundant 1+1 system shuts down and the other supply has to provide the full system load.

For a 12-V, 10-A power supply with a 0.05-Ω series resistor, a 0.5-V droop is obtained at

10 A (0.25 V if 2 supplies are paralleled). The power dissipation is

WRI droop 505.01022 =×= . (1.3)

With 50% derating, a 10-W resistor is required. Therefore, this scheme normally is used

only for low power linear post-regulators.

(c) Current-Mode Control with Low Voltage Compensator DC Gain

There is a rather common droop scheme that some vendors use to parallel regulators.

It has fairly good current sharing and an excellent transient response. This scheme depends

upon a fixed relationship between a change in error voltage (output of error amplifier) and

a change in pulse width. This droop method is implemented by eliminating the series

capacitor (DC isolation capacitor) in the feedback path of the error amplifier [12][14][17].

This greatly reduces the DC gain of the error amplifier, thus producing a droop in the

output voltage. A block diagram of a current-mode controlled converter with a finite DC

gain is shown in Figure 1.7.

9


Vref+-

Vin

IL1IL1

d

+- Ki

VC+-

+-+-

Vo

Hi

Rf

R2

R1

Hv

load

Figure 1.7. Droop realization for a current-mode converter with low voltage compensator DC gain.

From the block diagram, the predicted droop in the output voltage is given by the

following equation:

if

Linitialoo KRRIVV ××−= 1

1_ , (1.4)

where Ki is the gain of the current sense circuit, and Vo_initial represents the equivalent initial

value of output voltage:

)1( 1

2

1_

frefinitialo R

RRRVV ++= . (1.5)

Hence, the equivalent droop resistance is determined by

fidroop R

RKR 1= . (1.6)

(d) Voltage Droop via Output Current Feedback

In this method, the output current is sensed. As shown in Figure 1.8, with the current

information added on the fed back voltage, a droop is realized which is proportional to the

output current of the supply [14]. With an infinite DC gain in the voltage loop

compensator, Hv, the output droop characteristic is expressed as:

10


v

oirefo K

IKVV 1−

= . (1.7)

Therefore, the equivalent droop resistance is given by:

v

idroop K

KR = . (1.8)

Clearly, this method shows the same performance as utilizing a series resistor at the

output. However, by using a small sensing resistor instead of a large droop resistor, the

power dissipation is greatly reduced with this implementation. Meanwhile, the droop value

can be programmed conveniently in the feedback control circuit.

Io1Vin

+

-

Power Stage

PWMController

++

HV

Vo

Ki KV

Vref

load

Figure 1.8. Droop realized via the output current feedback.

This droop method has also been used to realize the active voltage position (AVP)

function in voltage regulators (VRs) powering the microprocessors [18].

(e) Summary

Although there exist different implementations for the droop method, the converter’s

output characteristic is similar. As a result, their steady-state and dynamic performance are

11


similar. Therefore, it is convenient to study the limitations of current sharing with droop

means through the example with the output current feedback.

1.2.2 Voltage Regulation Issue of the Droop Methods

B. T. Irving has studied the accuracy of current sharing with droop methods [12].

Generally, the current sharing accuracy, i.e. the difference between the output current of

the individual modules, is determined by the difference between the reference voltages of

individual modules, and by the droop resistance, Rdroop. Assuming the same output

resistance values, Figure 1.9 illustrates the dependence of the current sharing accuracy,

represented by ΔIo_max, on the mismatch of the reference voltages, ΔVo_SPA. In Figure 1.9,

the steady-state current sharing error is calculated by

avgo

oss I

I

_

max_Δ=Δ , (1.9)

where Io_avg is the total output current averaged by number of converters.

Meanwhile, system’s output voltage has to meet certain accuracy requirement no

matter it is running in what load condition. This means that Rdroop cannot be selected too

large, otherwise 2*ΔVo_max in Figure 1.9(b) would be too large to satisfy the output voltage

specification.

Therefore, from current sharing accuracy point of view, large Rdroop is desired. On the

other hand, Rdroop should be small to guarantee fair voltage regulation accuracy. This

conflict inherently limits the usage of droop method in the applications requiring both

accurate current sharing and voltage regulation.

12


+_LoadLoadRo

Vref2+_

Vref1

Io1

Vo

Ro

+

-

Module #1

Module #2 Io2

Io

Vref3+_

Ro

Module #3 Io3

(a) A paralleling system with droop current sharing.

Io1

Io

Vo

max_oIΔ

SPAoV _Δ

Io3

Io2

Vref3 Vref2 Vref1

Io_full

Vo

max_*2 oVΔ

(b) The difference between reference voltages leads to current sharing error.

Figure 1.9. With droop method, steady-state current sharing accuracy is depended on the voltage

reference set point accuracy.

13


Figure 1.10 illustrates an example of commercial paralleled converter modules [19].

The output voltage regulation accuracy is specified at ±3.5%. Meanwhile, it is desired to

keep the full-load current sharing accuracy below 12.5%. Therefore, it is mandatory to

have extremely high output voltage set-point accuracy, as shown in Figure 1.11. In the

practice of [19], the products have the set-point accuracy of 0.3%, i.e., only 15 mV

tolerance for the 5-V output power supplies. To maintain such high set-point accuracy over

entire temperature and time range, it requires extremely high cost and/or fine tuning for

each module during the production.

Converter #1

io1Vo=5V

io2

Rdroop

Rdroop

Converter #2

Vin=48V

ioLoad

Figure 1.10. A high cost distributed power system with Vicor’s VI200 converters.

0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

Set point accuracy (%)oSPAo VV /_Δ

Δ ss(%

)

Extreme high accuracy of 0.3%

Fair accuracy of 11%

Higher cost

High cost solution

Figure 1.11. A high cost droop implementation with extreme accuracy for the voltage references.

14


Another example is shown in Figure 1.13 with a paralleled VRM system [20].

According to Intel’s specification [21], the output voltage regulation accuracy is ±5%.

Meanwhile, the state-of-the-art set-point accuracy over life and temperature is about

±0.8%. Under this condition, it is found that the full-load relative current sharing error is

25%, which is much larger than the 10% requirement. On the other hand, to keep the full-

load current sharing accuracy below 10%, it is necessary to have the output voltage set-

point accuracy better than ±0.35%. However, the set-point-accuracy of ±0.35% over entire

temperature and time range is not achievable today with acceptable cost.

Converter #1

io1

io

Vo=1.3V

io2

Rdroop

Rdroop

Converter #2

Vin=12V

Load

Figure 1.12. A fair cost distributed power system with Intel’s VRM specification.

0 0.2 0.4 0.6 0.8 10

10

20

30

40

Set point accuracy (%)oSPAo VV /_Δ

Δ ss(%

)

Practical accuracy of 0.8%

Fair accuracy of 25%

Higher cost

Practical application

Figure 1.13. Practical accuracy leads to insufficient current sharing in paralleled VRM system.

15


In summary, the usage of passive droop current sharing methods is limited by the

conflict between voltage regulation and current sharing accuracy. Therefore, they may be

used in applications where the requirement for current sharing accuracy is low and/or when

higher cost is affordable.

1.2.3 Dynamic Current Sharing Issue with Droop Methods

Another issue of the passive droop method is the dynamic current sharing issue.

Figure 1.14 shows that the dynamic current sharing performance of a paralleling system

can be evaluated with a single-step load change. As shown in Figure 1.15(a), without

droop current sharing, there exist dynamic current sharing error, Δdyn, as well as steady-

state current sharing error, Δss. Δdyn is the response to the step load change. Figure 1.15(b)

shows the dynamic response of io1 and io2 with droop current sharing. Clearly, the droop

method only decreases Δss. However, for the dynamic current sharing error, Δdyn, there is

no improvement regarding the settling time and current overshoot. The huge overshoot

current caused by the load transient would trigger the protection function and interrupt the

normal operation of parallel systems. This makes dynamic current sharing performance a

very important aspect for the designers to consider.

With the evolution of requirements of the distributed power systems, dynamic

perturbations to the power supplies are occurring more frequently. Therefore, the dynamic

current sharing performance has become one of the critical design criteria. Without careful

design, the dynamic current sharing response could be unacceptable due to slow reaction or

large oscillations. Therefore, it is necessary to investigate a system’s current sharing

performance from the dynamic response aspect as well as the steady-state operation.

16


Load

Module #2

Module #1

io1

io

vo

io2

LoadLoad

Module #2Module #2

Module #1Module #1

io1

io

vo

io2

Figure 1.14. Paralleled converters under single-step load transients.

io1, io2 (A)

ΔssΔdyn+Δss

io1, io2 (A)io1, io2 (A)


ΔssΔssΔdyn+ΔssΔdyn+Δss ΔssΔssΔdyn+ΔssΔdyn+Δss

(a) Without droop scheme. (b) With droop current sharing.

Figure 1.15. Dynamic current sharing performance without and with droop current sharing .

1.3 Impedance Approach to Investigate Dynamic Current Sharing

For parallel systems, a lot of work has been presented [22][23][24][25][26], but the

researches have been mostly focused on the steady-state current sharing performance and

system stability analysis. So far, the dynamic property study of current sharing schemes

has not been widely reported, and the design limitations have not been clearly understood

for different control structures. Meanwhile, to investigate the dynamic current sharing

performance for different configurations, it is desired to derive a generic approach which is

independent of bus configurations and control structures. Therefore, it is essential to study

17


the fundamental questions like what determines the transient current sharing response, and

how does the current sharing scheme impact the voltage regulation during both steady-

state and dynamic operations.

When a paralleling converter/phase system is subjected to transients that are caused

by single step changes (load or input line changes, or any other one step actions), or caused

by low frequency perturbations (perturbation frequency is much lower than half of the

switching frequency), the dynamic current sharing response can be predicted by the

conventional modeling techniques. However, for a simple system with two converters in

parallel, when utilizing the small-signal model [24], multiple loop gains needs to be

defined to assess system stability and performance. Therefore, the analysis is complicated

and it is not stated clearly what are the physical meanings of those loop gains by this

approach. Moreover, when paralleling of more than two modules is investigated, the

number of feedback loops grows dramatically, which makes the transfer function analysis

suggested in [24] impractical. A more promising way to address the study of paralleled

systems was proposed in [25][26], where the output impedance concept is utilized as a

powerful tool to help understanding and analysis.

As shown in Figure 1.16, with Zo1 and Zo2 representing the terminal characteristics of

individual modules, they can be utilized for current sharing analyses. The definitions are:

111ˆ/ˆ ooo ivZ −= , (1.10)

222ˆ/ˆ ooo ivZ −= , (1.11)

2121 //)ˆˆ/(ˆˆ/ˆ oooooooo ZZiivivZ =+−=−= . (1.12)

18


Since vo=vo1=vo2, it can be derived from (1.10)~(1.12) that the dynamic current sharing

error under a load transient is evaluated by:

21

12

2121

21 )11(ˆˆˆˆ

oo

oo

ooo

oo

oo

ZZZZ

ZZZ

iiii

+−

=−⋅=+−

. (1.13)

Zo1+

-

Module #1

Module #2

+

-

+

-

oi

ov

2oi

1ov

2ovZo2

1oi Zo

Load

Δio

Figure 1.16. Output impedances of paralleled modules.

Clearly, it is the relative difference between Zo1 and Zo2 that determines the dynamic

current sharing response. It means that it is desirable to minimize the absolute difference

between Zo1 and Zo2. Meanwhile, it is also preferred to enlarge both the magnitudes of Zo1

and Zo2. Therefore, to investigate the dynamic current sharing performance, it is necessary

to investigate the influence on the impedance differences from the current sharing control

methods.

One special case of the impedance approach is predicting the steady-state current

sharing error. It is simplified from (1.13) that

21

1221

oo

oo

o

oo

RRRR

III

+−

=−

. (1.14)

19


Here, Ro1 and Ro2 are the DC output resistances of module #1 and #2, respectively.

Therefore, the difference between Ro1 and Ro2 leads to steady-state current sharing error.

Another part of the steady-state current sharing error is contributed by the reference

voltage set-point difference.

If droop resistors are inserted to each converter, as shown in Figure 1.17, their output

impedances are modified from Zo1 and Zo2 to Zo1’ and Zo2’. Apparently,

droopoo RZZ += 11 ' , (1.15)

droopoo RZZ += 22 ' . (1.16)

+

-

Module #1

Module #2

+

-

+

-

oi

ov1ov

2ov

Zo’

Rdroop Zo1’

1oi

Zo2’

2oi

Rdroop

Load

Δio

Figure 1.17. Output impedances of paralleled modules with added droop resistors.

Figure 1.18 compares the output impedances without and with droop resistors.

Because the droop resistors are equivalently in series with the original impedances, at the

frequency range where the original output impedances are higher than the droop value, the

original ones still dominate. At the rest part, especially at low frequencies, the droop

resistance is able to help the current sharing. However, in the entire frequency range, the

major difference between two impedances appears around 3~4 kHz. Therefore, the

20


dynamic current sharing error at this frequency range cannot be improved with the droop

scheme, as shown in Figure 1.15 and repeated in Figure 1.19.

10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

Zo1

Zo2

Frequency (Hz)

Out

put I

mpe

danc

es (d

B) fs/2

ΔZo

ΔRo Zo1’Zo2’

Frequency (Hz)

Out

put I

mpe

danc

es (d

B) fs/2

ΔZo’

ΔRo’

(a) Without current sharing. (b) With droop current sharing.


io1, io2 (A)

ΔssΔdyn+Δss



ΔssΔssΔdyn+ΔssΔdyn+Δss ΔssΔssΔdyn+ΔssΔdyn+Δss

(a) Without droop scheme. (b) With droop current sharing.


In another word, when there is a load transient, there is no improvement on the

overshoot and the settling time with droop current sharing, because they are determined by

the mismatched part of the impedances. If the dynamic current sharing performance is

desired to be improved with the droop method, the droop resistance needs to overwhelm

the original output impedance of the converters in the entire frequency region. For

21


example, in this case, a droop resistance higher than 6.3 Ω is needed. Clearly, this is

impractical because it leads to huge power losses and output voltage regulation error [12].

Therefore, the passive droop scheme is not capable of high-accuracy current sharing both

from the steady-state and the transient aspects.

1.4 Current Sharing with Active Controls

Because of the aforementioned voltage regulation and dynamic current sharing issues

of the droop scheme, the active current sharing technique has been developed for systems

requiring precise regulations. The basic feature of active current sharing methods is the

existence of a current sharing bus communicating among the paralleled power modules. It

usually provides a common current reference. Each module then adjust its own control to

follow this common reference thus the load current will finally evenly distributed among

these modules.

1.4.1 Active Current Sharing Control Configurations

To avoid the conflict between voltage regulation and current sharing, the “master-

slave” concept has been used since early 1980s. In a master-slave system, only one module

is regulating the output voltage, while the others provide equal amount of the load current.

After that, the democratic current sharing approaches are developed to improve the

reliability of the system.

(a) Master-Slave Configuration

The master-slave control (MSC) scheme was proposed to achieve a uniform current

distribution among converter modules connected in parallel [22][27][28][29][30]. This

22


scheme is applicable to non-identical converters and can even be adapted to a system with

different converter topologies connected in parallel. The MSC controlled system consists

of a single master module and a set of slave modules. In this scheme, slave modules are

controlled such that their output currents track the master converter’s output current.

Figure 1.20 illustrates the concept of the master-slave control.

Master supply

Slave supply No. 1

Power supply No. n

load

Im

Is1

Isn

Voltage sense

Con

trol v

olta

ge

Figure 1.20. Master-slave configuration.

The master-slave concept can be implemented in different ways. One of the earliest

implementations is based on the current-mode control of PWM converters [9][31][32], as

shown in Figure 1.21, where the power supplies are controlled by feeding back both the

inductor current and the output voltage.

Clearly, because there is only one voltage compensator, there is no issue due to the

different voltage reference settings. Meanwhile, all the modules’ current levels are

programmed by the single voltage control loop. With all the modules’ currents controlled

by the master module’s output of voltage compensator, an accurate current sharing control

is easily obtained. At the same time, the output voltage is regulated by the master supply,

23


the voltage regulation accuracy can be guaranteed. On the other hand, the current sharing

controllers force the slaves to track the master’s output current. With properly designed

compensators for both the voltage loop and the current sharing loops, the current sharing

error can be significantly reduced comparing to the droop method.

Figure 1.21. Master-slave current sharing with current-mode control.

Therefore, the major benefit of this master-slave current sharing scheme is the

accurate current sharing at both the steady state and during transient. Meanwhile, because

each converter operates under lower output power requirement, they are less possible to

fail. However, the disadvantage is also obvious with this approach: should a master fail

then the entire system fails, defeating the purpose of a redundant supply. In another word,

the redundancy is achieved only with the slave units, not with the master. For example, as

24


shown in Figure 1.22, if there is a single-point failure at the master module’s voltage

compensator, both the voltage regulation and the current sharing lose the control. In

addition, because the master’s structure is different from that of the slaves, they are not

interchangeable. This makes the system more complicated than a system utilizing simple,

compatible supplies with no external circuitry. In order to solve these issues and improve

system performance, the democratic current sharing controls are then proposed.

Figure 1.22. Fatal failure of the system would occur because of the master module’s malfunction.

(b) Democratic Configuration

From the system reliability aspect, the most attractive current sharing approaches are

those providing desired current sharing accuracy without implementing a master-slave

configuration or requiring a separate current-share controller. These “democratic” (also

25


referred to as autonomous or independent) current sharing approaches, which allow each

module to operate either as a stand-alone unit or in parallel with other modules, make it

possible for the implementation of the true N+ 1 redundant system.

Generally, the democratic current sharing can be implemented using two approaches.

The first approach is the passive droop method discussed in the previous section, which is

simple to realize and does not require any communication among the paralleled modules.

However, the major deficiency of the droop method, as demonstrated above, is the poor

load regulation, which makes it not suitable for applications requiring tight output voltage

regulations.

The other method ensures desired current sharing by active feedback controls. This

current sharing technique requires a single-wire communication (current sharing bus) to

provide the current reference for each module. Meanwhile, although each module must

have its own voltage sensing and reference circuitry, they all need to be regulated to the

same common output voltage level. Since there will always be differences between the

individual voltage references – no matter how slight – this technique need to solve the

voltage regulation conflict problem. There are many different means proposed in the past

[33][34][35][36][37][38][39].

In 1988, K. Small developed and patented the automatic average output current

sharing technique [33]. As shown in Figure 1.23, this method adjusts the reference

voltages of the voltage feedback error amplifiers of the individual modules so that

deviations of the modules’ currents from the average current are eliminated.

Figure 1.23 illustrates that there is no master and slaves anymore, and the current

sharing bus is occupied by the average current information. The average current

26


information, io_avg, is obtained on the share bus by connecting all output currents through

resistors with the same value. Clearly, with a high gain of the current sharing controller,

Hcs, each module’s output current is forced to follow the current sharing bus.

iosupply #1

vin vo

-+

vref1

Hv -+

Hcs

Rshare

io1

PWM

supply #2vo

-+

vref2

Hv -+Hcs

Rshare

io2

PWM

supply #nvo

-+

vrefn

Hv -+Hcs

Rshare

ion

PWM

+

+

++

+

+

io_avg

Tcs1Tv1

Tcs2Tv2

TcsnTvn

Figure 1.23. Automatic average current sharing technique proposed by K. Small.

With the configurations in Figure 1.23, although all the modules’ current information

is included in the current sharing bus, the failure of a single converter might also lead to

the crash of the whole system. Therefore, additional protection circuits are needed to cut

the input of the failed converter off the current sharing bus. To simplify the control circuit,

the democratic current sharing is improved with diodes connecting the current sharing bus,

as shown in Figure 1.24.With the series resistor replaced by a diode, the reference is

27


allowed to adjust only in an upward direction. The shared bus now represents the highest

current among the paralleled modules. This is because only the module with the highest

output current can forward-bias its diode and drive the current sharing bus. Modules

initially supplying lower output currents would use the share bus voltage as an input

command for their adjust amplifiers. Their reference voltages will be adjusted upwards to

increase their output currents until the voltage at the output of the current monitor equals

that on the share bus. In this approach, the master and slaver are automatically determined

and their roles are interchangeable. Today, some the current sharing control ICs, such as

UC3907 and UCC39002 [22][40], has been using this idea.

iosupply #1

vin vo

-+

vref1

Hv -+

Hcs

io1

PWM

supply #2vo

-+

vref2

Hv -+Hcs

io2

PWM

supply #nvo

-+

vrefn

Hv -+Hcs

ion

PWM

+

+

+

+

+

+

io_max

Tcs1Tv1

Tcs2Tv2

TcsnTvn

Figure 1.24. Democratic current sharing with diodes connecting the current sharing bus.

28


1.4.2 Active Current Sharing Control’s Influence on Output Impedances

With the active current sharing control, the dynamic current sharing performance can

still be analyzed using the output impedance concept. However, with the current sharing

control as shown in Figure 1.25, the output impedances are modified to Zcs1 and Zcs2. Still,

Zcs1 and Zcs2 are used to represent the terminal characteristics of power converters:

111ˆ/ˆ oocs ivZ −= , (1.17)

222ˆ/ˆ oocs ivZ −= , (1.18)

21 //ˆ/ˆ cscsoocso ZZivZ =−= . (1.19)

Zcs1+

-

Module #1

Module #2

+

-Zcs2

oi

ov

2oi

1ov

2ov

1oi Zcso

Load+

-

CS control

Δio

CS bus

Figure 1.25. Output impedances of paralleled modules with active current sharing control.

Because

21 ooo vvv == , (1.20)

the dynamic current sharing error under a load transient is evaluated by:

29


21

12

2121

21 )11(ˆˆˆˆ

cscs

cscs

cscscso

oo

oo

ZZZZ

ZZZ

iiii

+−

=−⋅=+−

. (1.21)

Therefore, to investigate the dynamic current sharing performance, it is necessary to

investigate the influence on the impedance differences from the current sharing control

methods.

An example of the active current sharing control is illustrated in Figure 1.26. With

the average current sharing bus, both modules become controlled current source with their

currents following the bus command. Meanwhile, they still have the voltage source

behavior due to the voltage regulation feedback loops.

Tv1

Tv2

Zcs1

Zcs2

Zcs1

Zcs2

Zo1Zo1

TcsTcs Zo2Zo2

Figure 1.26. Two paralleled modules with an active current sharing control scheme.

The current sharing loop gain, Tcs, plays a very important role in determining Zcs1 and

Zcs2. When there is no active current sharing control, the original output impedances of

30


paralleled modules are Zo1 and Zo2 in Figure 1.26. After considering the influence from Hcs,

the output impedances are modified to Zcs1 and Zcs2. Comparing with Zo1 and Zo2, Zcs1 and

Zcs2 are pulled toward each other inside the bandwidth of the current sharing loop, Tcs, as

shown in Figure 1.27. With its bandwidth at 6 kHz, where the Zo1 and Zo2 have the

maximal discrepancy, Tcs attenuates the original impedances’ difference. Therefore, the

dynamic current sharing performance is improved as well as the steady-state current

sharing accuracy, as shown in Figure 1.28.

1 10 100 1 .10 3 1 .10 4 1 .10 560

40

20

0

201 10 100 1 .10 3 1 .10 4 1 .10 5

40

20

0

20

40

60

801 10 100 1 .10 3 1 .10 4 1 .10 5

60

40

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

fs/2Zo1 ΔZoZo2

ΔRo

Loop

gai

n T c

s(d

B)

Out

put I

mpe

danc

es (d

B)

Tcs

fc=6kHz

Zcs2

Zcs1

ΔZcs

ΔRcs

Figure 1.27. Output impedances improvements with active current sharing control.

31


io1, io2 (A)

ΔssΔdyn+Δss


ΔssΔssΔdynΔdyn

ΔssΔssΔdyn+ΔssΔdyn+Δss

(a) Without current sharing. (b) With active current sharing.

Figure 1.28. Current sharing improvement with active current sharing control.

On the other hand, because the bandwidth of Tcs is not sufficiently wide, the

impedances’ difference cannot be totally eliminated. Therefore, there still exists certain

dynamic current sharing error. Nevertheless, the active current sharing scheme is able to

reduce the output impedances’ difference inside the current sharing loop bandwidth.

Therefore, it is a better choice than passive droop methods when high dynamic current

sharing performance is required.

Different from the voltage regulation requirements for the output impedance, it is the

discrepancy of the paralleled modules’ impedance, but not the magnitude of the impedance

of the system that determines the current sharing error. Therefore, although the current

sharing is improved, the voltage regulation is degraded because of higher overall

impedances, as shown in Figure 1.29.

In the control structure in Figure 1.26, the current sharing loop is outside of the

voltage regulation loop. Therefore, Tcs’s bandwidth limited by Tv. It is not practical for this

structure to have high Tcs bandwidth. Thus, the improvement of dynamic current sharing

performance could be limited with this control scheme. Nevertheless, it is possible to select

32


different active current sharing control methods if necessary. Because of this,

understanding the limitations for different active current sharing structures becomes a very

important matter.

10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B) w/ CS fs/2

time/mSecs 500? ecs/div

5 5.5 6 6.5 7

V

560

570

580

590

600

610vo (V)

w/o CS

w/o current sharingw/ active current sharing

560

580

600

5 5.5 6 6.5 (ms)

(a) Overall output impedance. (b) Output voltage response.

Figure 1.29. Output impedances improvements with active current sharing control.

To understand the different dynamic current sharing performances for different

control structures, it is necessary to investigate the current sharing structure’s behavior of

the output impedances. In the next chapter, each structure’s influence on parallel modules’

output impedances will be analyzed in detail in the next chapter.

1.5 Dynamic Current Sharing Issue with Repetitive Loads

There are numerous applications for the switching converters. Consequently, the

transient condition for the current sharing varies from case to case. Most of the converters

only need to deal with the single load step. However, some converters supplying highly

dynamic load, such as point-of-load voltage regulators (VRs), needs to handle the

repetitive load transients [41], as shown in Figure 1.30. The current sharing function is

realized by the peak-current mode control in Figure 1.30(a).

33


Ti1

Ti2

TiN

(a) Multiphase interleaved buck VR with peak-current mode control.

Time

CPU Power

Time

CPU Power

(b) Load profile for multiphase VR systems.

Figure 1.30. Interleaved multiphase buck VR with repetitive loads.

Available literatures about the current sharing study are all based on low-frequency

transients. What would happen with high-frequency perturbations is unknown to us.

However, this is a practical concern in certain applications such as VRs. The dynamic

current sharing performance when the load transient frequency is close to or higher than

34


the switching frequency is becoming a more and more important criteria as the

microprocessor increasing its computing speed. Therefore, it is necessary to study the

dynamic current sharing performance and related control design issues for both low-

frequency and high-frequency transients, which is the major target of this dissertation.

iL1, iL3 (20A/div)

io(50A/div)

20A*4phase

20A

(50us/div)

Figure 1.31. Dynamic current sharing with peak-current mode control: tested under low-frequency

transients: switching frequency fs=300kHz; load transient frequency fp=10kHz.

io (15A/div)4A*4phase

17A

(10us/div)iL1, iL3 (10A/div)

Figure 1.32. Beat-frequency oscillations under high-frequency repetitive perturbations: tested with

peak-current mode control. Switching frequency fs=300kHz; load transient frequency fp=280kHz.

The dynamic current sharing performance under the repetitive load transients is

different from the single step load, because the current sharing response is now related to

35


the load transient frequency. The experimental waveform in Figure 1.31 shows a good

dynamic current sharing performance with low-frequency load transients. The test is based

on a 300-kHz, 4-phase interleaved buck VR with peak-current mode control, which

belongs to the inner-loop category. The load current waveform and the phase currents from

two phases, iL1 and iL3, are measured in Figure 1.31.

When the transient is repeated in a low-frequency fashion (much lower than the

switching frequency), it can be seen that the dynamic current sharing performance is

acceptable in Figure 1.31. The reason is that inner-loop schemes can normally provide a

relatively high current sharing loop bandwidth; therefore the dynamic current sharing

should be well controlled when the load repetitive frequency is below the bandwidth.

Meanwhile, the conventional output impedance concept can still be used for dynamic

current sharing study.

However, there also exists possibility of high-frequency perturbations, such as in VR

systems [41]. Even with acceptable dynamic current sharing performance under low-

frequency transients, the current unbalance under high-frequency load transients may still

become too large. The experimental waveforms in Figure 1.32 demonstrate the special

beat-frequency oscillation problem when the perturbation frequency of the load transient,

fp, is approaching the switching frequency, fs. Huge low-frequency oscillations in the phase

currents are observed. This low-frequency oscillation is determined by fs-fp. Namely, it is

the beat-frequency oscillation, denoted as fbeat oscillation later. In this particular test, the

oscillation magnitude of each phase current is about 4 times higher than the rated value.

36


(a) Before the current unbalance. (b) Blue screen after the current unbalance.

Figure 1.33. Blue screen error due to current unbalance in highly dynamic CPU load.

The beat-frequency oscillations is an undesired phenomenon from the system

reliability aspect, since large oscillations can result in extra electrical and thermal stress on

components, as well as the possibility of magnetic saturations. In some cases, especially

with video games, there is additional concern if the oscillations are in the auditable

frequency range. If the worst scenario happens, converter failure can be resulted from the

huge current peak value, leading to the blue screen error on the computer, as shown in

Figure 1.33. Moreover, this large-magnitude beat-frequency oscillation is difficult to

eliminate because its frequency might be very low and cannot be easily filtered.

This special beat-frequency current sharing issue is not well recognized, although it

is a widespread issue for today’s VRs. As required by Intel, VR needs to deal with load

transient frequencies up to 1~2 MHz, depending on software running by the

microprocessor. Meanwhile, the switching frequency of a typical VR is from 200-kHz to

1-MHz. Therefore, it is very likely that with certain kinds of software, the perturbation

frequency, fp, is fixed around fs. Hence, it is vital to study this beat-frequency current

oscillation issue.

37


The fundamental reason of the beat-frequency oscillation’s generation is the

sampling characteristic of the PWM modulator [42][43]. As illustrated in Figure 1.34, with

a single-phase open-loop buck converter, supposing there is a perturbation with frequency

fp in the control signal, vc, it is sampled when going through the PWM modulator. Due to

the time-varying nature of a sampler, sideband components such as fs+fp, fs-fp, 2fs+fp, 2fs-fp

are generated at the output of the modulator, i.e., the duty cycle. The spectra are illustrated

in Figure 1.35. After being fed into the power stage and attenuated by its low-pass filter,

the sideband component fs-fp causes the beat-frequency oscillations in the output voltage

and current. However, the beat-frequency components are negligible when fp is much

lower than fs, as shown in Figure 1.36(a). Under this condition, the low-pass filters in the

power stage attenuate the high-frequency fs-fp components. On the other hand, when fp is

close to fs, there is little function for the low-pass filter on the beat-frequency components;

therefore, fs-fp component dominates the output current, as in Figure 1.36(b).

LvoVin

Cfs

fp

vcvr

vd

Rod

PWM

io

Figure 1.34. A single-phase, open-loop buck converter.

38


pf− pf

cv~

pf− pf

cv~

ps ff −− ps ff +ps ff −ps ff +− pf− pf

dv~sfsf−


dv~sfsf−


v o~

sfsf−

LPF

pf− pf

cv~

pf− pf

cv~

ps f2f +− ps f2f −ps ff −ps ff +−pf− pf

dv~sfsf−

ps f2f +− ps f2f −ps ff −ps ff +−

LPF

pf− pf

v o~

sfsf−

(a) When fp is much lower than fs. (b) When fp is close to fs.

Figure 1.35. Spectra of , , and under different relationship between fcv dv ov p and fs.

ti / S 100? /di

4.6 4.7 4.8 4.9 5

VO /

V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4


4.6 4.7 4.8 4.9 5

Vc /

mV

890892894896898900902904906908910

100us/div

V o(V

)V c

(mV)

100us/div

fp=10kHz

fp=10kHz

ti / S 100? /di

4.6 4.7 4.8 4.9 5

VO /

V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

V c(m

V)V o

(V)

100us/div

fp=990kHz

5us/divfs-fp=10kHz

(a) When fp is much lower than fs. (b) When fp is close to fs.

Figure 1.36. Time domain waveforms with different relationship between fp and fs.

39


To model this behavior in a closed-loop system, based on the extended describing

function approach, the multi-frequency model has been proposed to investigate the loop

gain at the perturbation frequency considering the influence from the sideband components

[43]. In Figure 1.37, the concept is briefly illustrated: the sideband component at fs-fp has

been included into the model. However, in the past, the research was focus on the

influence from the sideband components, such as the bandwidth limitations.

Tv

(a) Closed-loop single-phase buck converter.

Tv

(b) Concept of the multifrequency model.

Figure 1.37. Multifrequency model for the single-phase, closed-loop buck converter.

40


The multifrequency model can be extended for multiphase circuit as well. Therefore,

it is expected to combine the multifrequency model with the output impedance concept for

the dynamic current sharing study. However, as shown in Figure 1.38, although there are

significant beat-frequency oscillations in the currents, the same frequency component is

unobservable at the output voltage. This makes the conventional transfer function of

impedance unusable in analyzing beat-frequency oscillation of currents. Therefore, the

conventional impedance cannot be directly used to study the beat-frequency related issues.

In order to extend the impedance concept for high-frequency studies, the key is to

understand that there are different frequency components inside the circuit. As the result,

the response and perturbation may not have the same frequency.

(a) 2-phase interleaved buck VR. (b) Output currents and voltage waveforms.

Figure 1.38. Circuit and waveforms for 2-phase interleaved buck VR: fp=990kHz, fs=1MHz.

In order to predict the dynamic current sharing error at fs-fp, as well as fp, the

conventional output impedance concept can be extended to included different frequency

components. The essence of the output impedance concept is to reflect the terminal

41


information of output voltage and current. Therefore, with similar concept, extended

describing functions representing the terminal information including different frequency

components can be defined for our purpose of predicting the beat-frequency oscillation of

currents. As show in Figure 1.39, the extended describing functions X1 and X2 are defined

to represent the terminal characteristics for different frequency components:

)(1

)(1

fpfso

fpo

iv

X−

−= , (1.22)

)(2

)(2

fpfso

fpo

iv

X−

−= . (1.23)

Because X1 and X2 express the relationship between the output voltage and current at

different frequencies, they are no longer the traditional impedances. Nevertheless, they

provide us with a very convenient tool which can be used just as conventional output

impedances.

)(1

)()(1

fpo

fpofpcs i

vZ −=

)(

)()(

fpo

fpofpcso i

vZ −=

)(1

)()(1

fpfso

fpofpfs i

vX

−− −=

)(2

)()(2

fpo

fpofpcs i

vZ −=

)(2

)()(2

fpfso

fpofpfs i

vX

−− −=

Figure 1.39. Output impedances and their extension for different frequency components.

42


Thus, the current sharing error at beat-frequency as the response of high-frequency

load transient can be expressed as:

)11()(

)()(

21)(

21

XXZ

fiffiffi

fpcsopo

psopso −⋅=−−−

. (1.24)

Compared with the perturbation frequency current sharing error of

)11()(

)()(

)(2)(1)(

21

fpcsfpcsfpcso

po

popo

ZZZ

fififi

−⋅=−

, (1.25)

they have the similar expression, except the traditional output impedances of individual

modules are replaced by the newly defined X1 and X2. It is found that the beat-frequency

dynamic current sharing error is determined by the difference between X1 and X2, which

have the form of extended describing functions. However, it will be discussed in Chapter 3

that X1 and X2 are negative to each other. This means their difference is actually the sum of

their magnitudes. Because of this, the beat-frequency current sharing error could be very

large even with same magnitudes of X1 and X2.

Meanwhile, based on (1.24), the traditional total impedance also is a determinative

factor. However, there is no direct relationship between Zcso and X1, X2, which is another

difference between the fp and fbeat current sharing. Therefore, with a higher Zcso, there is

larger beat-frequency current sharing error.

In summary, by utilizing the output impedance concept and its expansion in the form

of describing functions, the dynamic current sharing performance can be conveniently

evaluated for both low-frequency and high-frequency transients. This is exactly the

approach adopted in this work.

43


1.6 Dissertation Objective and Outlines

The objective of this work is to study the dynamic current sharing performance and

its influence on the voltage regulation response under both low-frequency and high-

frequency transients, so that a better understanding and feedback designs can be achieved

to paralleling systems. To achieve this objective, the output impedance approach is

explored in detail, and extended to the high-frequency analysis.

In the next chapter, the general study of dynamic current sharing under low-

frequency perturbations will be presented based on the output impedance concept. Then

the three current sharing control structures are able to be compared regarding the system’s

dynamic performance.

In Chapter 3, the special current sharing issue under high-frequency dynamics is

studied thoroughly. An unconventional multi-frequency model is proposed to evaluate the

beat-frequency current sharing issue with extended describing functions. After that,

possible solution is proposed and tested. Furthermore, the dynamic current sharing issues

related to the higher-order beat-frequency oscillations are discussed in Chapter 4 with the

extended multi-frequency model.

With both low-frequency and high-frequency models ready, Chapter 5 then

summarizes the study from all previous chapters. The output impedance concept and its

extension in the form of extended describing function have been proven an effective

approach for the dynamic current sharing study. Conclusions are also given in Chapter 5.

44

Chapter 2. General Study about the Dynamic Current

Sharing Performance

2.1 Introductions

When a paralleling converter/phase system is subjected to transients that are caused

by single step changes (load or input line changes, or any other one step actions), or caused

by low-frequency perturbations (perturbation frequency is much lower than half of the

switching frequency), the dynamic current sharing response can be predicted by the

conventional modeling technique. A small-signal model of two paralleled converters has

been demonstrated in [24] based on the well-known average modeling technique, where

five different loop gains are defined to assess system stability and performance. However,

it is not stated clearly what are the physical meanings of those loop gains in this approach.

Moreover, when paralleling more than two modules, the number of feedback loops grows

dramatically, which makes the transfer function analysis suggested in [24] impractical. By

assuming identical modules, [26] is able to tackle the stability analyses of N-module

paralleling system. However, the dynamic current sharing performance is not predictable

with such an assumption.

A more promising way to address the current sharing study of paralleled systems was

proposed in [25][36], where the output impedance concept is utilized as a powerful tool to

evaluate dynamic current sharing performance. This output-impedance approach is adopted

in this dissertation because it brings better understanding of a real physical system and

overcomes the difficulty of studying paralleling systems with more than two modules.

45

Juanjuan Sun Chapter 2. General Study about the Dynamic Current Sharing Performance

2.1.1 Introduction of the Output-Impedance Approach

The output impedance represents a converter’s terminal characteristics between the

output voltage and current. Figure 2.1 shows the approach of using output impedances to

evaluate dynamic current sharing responses of a paralleling system.

Zo1+

-

Module #1

Module #2

oi

ov

2oi

1oi

Zo2

Load

Zo

oioo iI ˆ+

oI

o1I

Δioo1o1 iI ˆ+

o2I

o2o2 iI ˆ+

(a) Output impedances of paralleled modules. (b) Dynamic current sharing response.

Figure 2.1. Use output impedances to evaluate dynamic current sharing performance.

In Figure 2.1(a), the terminal characteristics of paralleled converters are represented

by their output impedances in the small-signal model. It is defined that

11 ˆ

ˆ

o

oo i

vZ −= , (2.1)

22 ˆ

ˆ

o

oo i

vZ −= . (2.2)

Since there is no active current sharing control applied to the system in Figure 2.1(a), the

two modules’ output impedances, Zo1 and Zo2, are individually determined by themselves.

Namely, they are not influenced by each other no matter whether they are connected

together or not. Thus, the total output impedance of the system is

46


2121

21

21

//ˆˆˆ

ˆˆ

oooo

oo

oo

o

o

oo ZZ

ZZZZ

iiv

iv

Z =+

=+

−=−= . (2.3)

Therefore, based on these definitions, output impedances can be utilized to evaluate

the dynamic current sharing performance because

21

12

21

2121 )11(/ˆ

/ˆ/ˆˆ

ˆˆ

oo

oo

ooo

oo

oooo

o

oo

ZZZZ

ZZZ

ZvZvZv

iii

+−

=−⋅=−

+−=

−. (2.4)

Here, the symbol ˆ means a small-signal perturbation or response. The left-hand side of

(2.4) represents the dynamic current sharing error as a response of load perturbation; the

right side shows that dynamic current sharing error is related to two aspects: the difference

between paralleling modules’ output impedances and the sum of them. It is the ratio of

these two terms determines the final dynamic current sharing error.

One special case of the impedance approach is predicting the steady-state current

sharing error. It is simplified from (2.4) that

21

1221

oo

oo

o

oo

RRRR

III

+−

=−

. (2.5)

Here, Ro1 and Ro2 are the DC output resistances of module #1 and #2, respectively.

Comparing with (1.1), the only difference is that the reference voltage error is assumed to

be zero. Therefore, if considering there is no voltage set-point error, the steady-state

current sharing performance is determined by the DC output resistances of the converters.

Once the tolerance of the output resistances is known, it is straightforward to calculate the

steady-state current sharing error. Extending the equation to the frequency domain, the

output impedance can be used as a criterion to evaluate the dynamic current sharing

performance during load transients. However, the assumption behind this approach is that

47


the load transient frequency must be much lower than half of the switching frequency of

the converters so that the output impedance derived from the average model is valid.

The output impedance of a converter not only can represent the dynamic responses of

output voltage under the load transients in a small-signal sense, but also is able to predict

the large-signal performances as long as the load changes do not shift the operating point

of the converter. Based on this, the approach of the low-frequency dynamic current sharing

study is obtained: first the output impedances for different current sharing methods needs

to be derived; then the influence of current sharing controls can be identified and

compared; at last, the design tradeoffs should be clarified.

2.1.2 An Example of Applying the Output-Impedance Approach

In this section, by using the output impedance concept, the process of low-frequency

dynamic current sharing analyses is demonstrated with a paralleling system of two

paralleled isolated boost converters. The transformer of each boost converter has 1:18 turns

ratio, so that 600-V output voltage can be obtained from 24~30V input voltage. The output

power of each converter is 5 kW. Figure 2.2 shows this system without the complexity

from transformers. Each boost converter has its own voltage feedback control loops, their

compensators, Hv1 and Hv2, are designed to be the same. However, since the input voltage

is extremely low comparing with the output voltage, a special issue of this application is

the huge input current. To handle a more than 200-A input current, a bulky input inductor

is needed. Therefore, for the purpose of high power density, the input cables are utilized as

the inductors, L1 and L2. On the other hand, the inductances of input cables have relatively

large variation due to different length and loop area, which is hard to control in practice.

48


This variation of inductances in paralleled converters becomes a severe concern in terms of

current sharing control design.

Zo1

Zo2

Tv1

Tv2

Zo

Figure 2.2. A paralleling system of two boost converters: without current sharing.

In Figure 2.2, assuming a ±50% variation of the inductances, the values of passive

components are shown in Table 2.1:

Table 2.1. Values of passive components in Figure 2.2.

L C

Module #1 2.5 uH 1 mF

Module #2 5 uH 1.2 mF

The small-signal characteristic of the boost converter #1 is shown in Figure 2.3. It is

well-known that there exists a moving right-half-plane zero related to the load resistance

and the inductor. Because of this right-half-plane zero, the feedback control loop has more

difficulties in increasing its bandwidth.

49


10 100 1 .103 1 .104 1 .10520

0

20

40

60

10 100 1 .103 1 .104 1 .105270

180

90

0

90

Frequency(Hz)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)fs/2

10 100 1 .103 1 .104 1 .10520

0

20

40

60

10 100 1 .103 1 .104 1 .105270

180

90

0

Frequency(Hz)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)

fs/2Tv1

Gvd1

ESR Zero

RHP Zero

fc=10kHz

Figure 2.3. Control-to-output transfer function of

boost converter #1.

Figure 2.4. Voltage feedback loop gain of boost

converter #1.

Figure 2.4 illustrates the design result of the voltage feedback loop, Tv1. Due to the

limitation from the right-half-plane zero, Tv1’s bandwidth can only be push to around 10

kHz. With this design, the output impedances, Zo1 and Zo2, are plotted in Figure 2.5(a). The

dynamic current sharing response of this system is simulated under a single-step load

change and shown in Figure 2.5(b).

The steady-state current sharing error in Figure 2.5(b), Δss, is contributed by the

different DC output resistances, Ro1 and Ro2. In this application, Ro1 and Ro2 are mostly

determined by parasitics of the circuit, such as ESR of inductor, Rdson of switch, and cable

resistances. With a high voltage-loop gain at low-frequency, the output impedance is

attenuated. However, in practice, the voltage loop cannot has an infinitely high DC gain;

50


hence, there are certain output resistances for the paralleled modules. In the simulation, the

following values are used: Ro1=4 mΩ, Ro2=12 mΩ. Therefore, with a 19-A total output

current, there is

AIRRRRII o

oo

ooooss 5.919

412412

21

1221 =×

+−

=×+−

=−=Δ . (2.6)

10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

Zo1

Zo2

Frequency (Hz)

Out

put I

mpe

danc

es (d

B) fs/2

ΔZo

ΔRo

(a) Output impedances without current sharing.

(A)


io1

io2

(b) Dynamic current sharing response under single-step load transient.

Figure 2.5. Dynamic performance of the paralleling system without current sharing control.

51


Meanwhile, because of the large discrepancy between Zo1 and Zo2 in higher-frequency

range (marked as ΔZo in Figure 2.5(a)), there exists a dynamic current sharing error. With

both the steady-state and transient current sharing error combined, the instantaneous

current of one module exceeds 18 A, which is about 2 times of its rated value.

To improve the steady-state current sharing accuracy, droop resistors can be added as

in Figure 2.6. As a result, the output impedances are modified to Zo1’ and Zo2’. Figure

2.7(a) illustrates the bode plots of Zo1’ and Zo2’. Clearly, at the frequency range where the

original output impedances are higher than the droop value, the original ones still dominate

the dynamic current sharing performance. At the rest of frequency region, especially at

DC, the droop resistances are able to help the current sharing.

Zo1’

Zo2’

Tv1

Tv2

Zo’

Figure 2.6. The paralleling boost system with passive droop current sharing.

52


10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

Zo1’Zo2’

Frequency (Hz)

Out

put I

mpe

danc

es (d

B) fs/2

ΔZo’

ΔRo’

(a) The output impedances of individual converters.

ΔssΔdyn+Δss

io1

io2

(A)

(b) Corresponding output currents waveforms under load transient.

Figure 2.7. Dynamic current sharing performance is not improved with the droop method.

The droop resistance value used is 40 mohm. Hence, the equivalent DC output

resistances of two paralleled modules are changed to: Ro1’=44 mΩ, and Ro2’=52 mΩ. The

steady-state current sharing error is then calculated as:

53


AIRRRRII o

oo

ooooss 6.119

44524452

''''

21

1221 =×

+−

=×+−

=−=Δ . (2.7)

Based on (2.5), it is not the absolute difference, but the relative difference between

the output resistances that determines the steady-state current sharing error. As shown in

Table 2.2, with the droop function, although the absolute difference remains the same as 8

mΩ, the relative difference is reduced from 50% to 8.3%. As a result, with a 19-A total

current, the steady-state current sharing error is reduced from 9.5 A to 1.6 A, i.e., from

50% to 8.3%.

Table 2.2. Resistances comparison: without and with droop method.

Without droop With droop

1oR 4 mΩ 44 mΩ

2oR 12 mΩ 52 mΩ

12 oo RR − 8 mΩ 8 mΩ

21

12

oo

oo

RRRR

+−

50.0 % 8.3 %

1oI 14.25 A 10.3 A

2oI 4.75 A 8.7 A

21 oo II − 9.5 A 1.6 A

21

21

oo

oo

IIII

+−

50.0% 8.3%

However, without changing the control structure of each converter, the passive droop

current sharing improves only the steady-state current sharing accuracy. According to

Figure 2.7(b), there is no improvement on the overshoot and the settling time with droop

54


current sharing when encounting load transients. The reason can be found from (2.4): when

there is no current sharing,

ooo

oooodyn i

ZZZZii ˆˆˆ

21

1221 ×

+−

=−=Δ . (2.8)

While after adding the droop resistors, the dynamic current sharing error is

odroopodroopo

droopodroopoo

oo

oooodyn i

RZRZRZRZ

iZZZZ

ii ˆ)()()()(ˆ

''''ˆˆ

21

12

21

1221 ×

+++

+−+=×

+−

=−=Δ . (2.9)

Since the magnitudes of Zo1 and Zo2 are much larger than Rdroop at the frequency range we

are interested, (2.9) is approximately equal to (2.8). Hence, passive droop methods have

the limitation of improving dynamic current sharing performance.

According to Figure 2.7, if the dynamic current sharing performance is desired to be

improved with the droop method, the droop resistance needs to overwhelm the original

output impedance of the converters in the entire frequency region. For example, in this

case, a droop resistance higher than 6.3 Ω is needed. Clearly, this is impractical because it

leads to huge power loss and output voltage regulation error [12]. Therefore, the passive

droop scheme is not capable of high-accuracy current sharing both from the steady-state

and the transient aspects. Active current sharing schemes, on the other hand, are better

candidates in terms of both aspects. According to different control structures, active current

sharing control methods are further classified into three categories: outer-loop, inner-loop

and dual-loop. All of them have the ability to modify undesired output impedances without

too much scarification.

55


2.2 Dynamic Current Sharing Analyses with Active Current Sharing

Controls

Because of the aforementioned voltage regulation and dynamic current sharing issues

of the droop methods, active current sharing techniques have been developed for systems

requiring precise regulations. The basic feature of active current sharing methods is the

existence of a current sharing bus communicating among the paralleled power modules. It

provides a common current reference. Each module then adjusts its own control to follow

this common reference, thus the load current will finally evenly distributed among these

modules. Nevertheless, the output impedance is still a valid and powerful approach for

dynamic current sharing study.

Zcs1+

-

Module #1

Module #2

Zcs2

oi

ov

2oi

1oi Zcso

LoadZo1

Δio

CS bus CS

control

Zo2

Figure 2.8. The output impedance approach for paralleling system with active current sharing control.

As shown in Figure 2.8, with active current sharing control, the output impedances

are modified from their original values of Zo1 and Zo2 to Zcs1 and Zcs2. Regarding terminal

56


characteristics, Zcs1 and Zcs2 should be used to represent the real performance of these

paralleled modules. Therefore, they are calculated by:

11 ˆ

ˆ

o

ocs i

vZ −= , (2.10)

22 ˆ

ˆ

o

ocs i

vZ −= . (2.11)

These two equations seem exactly the same as (2.1) and (2.2). However, since io1 and io2

have been changed due to current sharing control, the two impedances are also changed. In

another word, Zcs1 and Zcs2 already consider feedback control of output currents.

Meanwhile, the total output impedance of the paralleling system is calculated as

2121

//ˆˆˆ

ˆˆ

cscsoo

o

o

ocs ZZ

iiv

iv

Z =+

−=−= . (2.12)

And the system’s dynamic current sharing error is evaluated by:

21

12

21

21 )11(ˆˆˆ

cscs

cscs

cscscso

o

oo

ZZZZ

ZZZ

iii

+−

=−⋅=− . (2.13)

Due to the interconnection bus between two modules, Zcs1 and Zcs2 are now related to

each other, this is different with what has been discussed in section 2.1. Therefore, the

major task of this section is to find out Zcs1 and Zcs2 for different active current sharing

schemes and the consequences.

2.2.1 Outer-Loop Current Sharing Control

The outer-loop current sharing structure is illustrated in Figure 2.9. In this scheme,

the output currents of two paralleled converters, io1 and io2, are sensed and compared with

57


the average current signal, which is obtained from the current sharing bus that connects

two modules through resistors of the same value. The output of the current sharing

controller Hcs, vcso1 and vcso2, is added to the output voltage feedback signal to adjust the

reference voltage equivalently. In this way, the currents of paralleled modules are forced to

follow the bus value and the steady-state current sharing is achieved. The signal on the

current sharing bus does not necessarily to be the average value of output currents, it can

be the maximum value of all output currents, or any dedicated values.

io1vin

Tv1

+-

Hv

CS_BusVref1

+

+Hcs

-+

Hv

Vref2

+

+

io2

Tv2

vo

vo

+-

Hcs+

-

Power stage #1

2ii o2o1 +

Power stage #2

io

Vcso1

Vcso2

Zcs1 Zcso

Zcs2

Figure 2.9. Outer-loop current sharing control with two paralleled converters.

Since the current sharing control signal has to go through the inside voltage feedback

loop, this control scheme is named as the outer-loop regulation. In some applications, a

current feedback control loop could also be added inside Tv. Because of good modularity

and the ability to achieve real redundant operation, outer-loop current sharing is mostly

used for paralleled modules in distributed power systems, such as high reliability

58


applications in server, telecom, workstation, etc. There are many ICs available to realize

this kind of control structure, such as UC3907, UCC39002, LM5080, and L6615.

(a) Derivation of Output Impedances

Apparently, the introduction of the current sharing control makes the whole system

much more complicated. There exist more control loops; therefore, the interactions of the

paralleled modules must be taken into consideration when the dynamic performance is

concerned.

According to the Thevenin theory, any linear electric circuit can be reduced to a

combination of an ideal voltage source and an output-impedance. On the other hand, non-

linear switching regulators have been linearized based on the small signal assumption [44].

Therefore, assuming there is no perturbation in the input voltage, the power stages in

Figure 2.9 are substituted by controlled voltage sources and the open-loop output

impedances, ZOL. As shown in Figure 2.10, the small-signal model of power stage #1 is

represented by a controlled voltage source and its open-loop output impedance, ZOL1. Gvd is

the duty-to-output voltage transfer function of the power stage, Hv is the voltage feedback

compensator and Fm is the PWM gain.

In Figure 2.10, the closed-loop output impedance of an individual module is referred

as Zo1, which has already included the influence from the closed voltage feedback loop,

Tv1,

)1/( 111 vOLo TZZ += , (2.14)

mvvdv FHGT 11 = . (2.15)

Similarly,

59


)1/( 222 vOLo TZZ += , (2.16)

mvvdv FHGT 22 = . (2.17)

Tv1

-Hv

Power stage #1

vdGd ⋅1

CS_Bus

+

+ Hcs+-

Fm

ZOL1+-

1ˆcv

1d

1oi

1ˆcsov

Zo1 Zcs1

ov

Figure 2.10. The small-signal model of module #1.

However, the effect of the current sharing control is not shown in Zo1 and Zo2. To

understand the influence from the current sharing control mechanism, we should look at

the output impedance Zcs1 instead of Zo1 in Figure 2.10. To derive Zcs1, further

simplification by applying the Thevenin equivalent circuit theory leads to Figure 2.11.

Module #1 is represented by its closed-loop output impedance Zo1 and a voltage source that

is controlled by vcso1.

Same model is derived for module #2. Now, with two modules paralleled and the

outer-loop current sharing control added, the completed small-signal model of the

paralleling system is shown in Figure 2.12 by noticing

2

ˆˆˆˆ 21

21oo

cscsocsoii

Hvv−

⋅=−= . (2.18)

60


CS_BusHcs

+-

11

1 ˆ1 cso

v

v vT

T+

−

Zo1

+-

ov 1oi

1ˆcsov

Zcs1

Figure 2.11. Further simplified small-signal model of module #1.

According to (2.13), with the current sharing control, the dynamic current sharing

performance is represented by

21

12

21

21

ˆˆˆˆ

cscs

cscs

oo

oo

ZZZZ

iiii

+−

=+−

. (2.19)

Based on Figure 2.12, Zcs1 and Zcs2 are solved as

2211

21211 )1(

)1(

ocsocs

oocscscs ZTZT

ZZTTZ

⋅++⋅⋅⋅++

= , (2.20)

1122

21212 )1(

)1(

ocsocs

oocscscs ZTZT

ZZTTZ

⋅++⋅⋅⋅++

= , (2.21)

where,

11

11

112 ov

vCScs ZT

THT ⋅

+⋅= , (2.22)

61


22

22

112 ov

vCScs ZT

THT ⋅

+⋅= . (2.23)

Moreover, a current sharing control loop gain Tcs is defined based on the derivations:

)11

(2

2

1

1

21 v

v

v

v

oo

cscs T

TT

TZZ

HT

++

+⋅

+= . (2.24)

11

1 ˆ1 cso

v

v vT

T+

−

Zo1+- +-

ov

1oi

1ˆcsov

22

2 ˆ1 cso

v

v vT

T+

−

Zo2+- +-2oi

+-HCS/2

-1

2ˆcsov

A

Zcs1

Zcs2

B

Tcs=B/A

Figure 2.12. Simplified small-signal model of the paralleling system with outer-loop current sharing.

The physical meaning of Tcs is explained in Figure 2.12: if an AC perturbation source

is inserted as shown, the loop gain measured at the two ports of this AC source is Tcs.

However, it is worth noting that this point does not physically exist in a circuit. Even

though, Tcs gives us a convenient tool to investigate the design of the current sharing

controller, Hcs.

Tcs not only determines the stability of the paralleling system, but also changes its

dynamic response of current sharing by modifying the original closed-loop output

62


impedances of Zo1 and Zo2 to Zcs1 and Zcs2. Therefore, with the outer-loop current sharing

control, according to (2.20)~(2.24), the following very simple relationship can be obtained

that

csoo

oo

cscs

cscs

o

oo

TZZZZ

ZZZZ

iii

+×

+−

=+−

=−

11

ˆˆˆ

12

12

12

1221 . (2.25)

Equation (2.25) explains that the function of Tcs is to attenuate the dynamic current

sharing error inside its bandwidth. In another word, these two modules’ original closed-

loop output impedances Zo1 and Zo2 are modified by the current sharing control, so that

they are matched with each other inside Tcs’s bandwidth, to reduce the error. As the result,

the higher loop gain and the wider bandwidth of Tcs, the better match between Zcs1 and Zcs2

in a wider frequency range, and the better dynamic current sharing performance

consequently.

According to (2.20) and (2.21), higher DC gain of Hcs is preferred to assure smaller

steady-state current sharing error, which is the difference between Io1 and Io2. If Hcs has

high DC gain, the DC output resistances are modified to

221

1oo

csRRR +

≈ , (2.26)

221

2oo

csRRR +

≈ . (2.27)

So the steady-state current sharing error is minimized with Hcs’s high DC gain:

012

1221 ≈×

+−

=− ocscs

cscsoo I

RRRRII . (2.28)

63


On the other hand, higher DC gain of Hcs is also beneficial to reduce the steady-state

current sharing error caused by the difference between the reference voltages, Vref1 and

Vref2. Thus, the first requirement of Hcs is high DC gain.

Meanwhile, Hcs needs to be designed so that Tcs is stable. According to (2.24), it is

noticed that the integrator 1/s in Hv also appears in Tcs, which means that Tcs always has

infinite DC gain even when Hcs doesn’t. However, this infinite DC gain of Tcs caused by Hv

does not guarantee zero steady-state current sharing error according to (2.28). Instead, the

infinite DC gain of Tcs makes (2.25) equals to zero at steady state, namely the DC

resistances’ difference and the steady-state current sharing error caused by it are

eliminated.

As aforementioned, Tcs already has a 1/s factor embedded. Therefore, if Hcs has

infinite DC gain, the phase of the current sharing control loop becomes –180o degree at the

very low frequency region. This is an extreme case of conditional stable and is undesired

for the system although it can achieve zero steady-state current sharing error. This is why

in the outer-loop current sharing control scheme, the compensator with a finite DC gain is

recommended. Clearly, there exists a conflict between the requirements of steady-state

current sharing accuracy and stability of the current sharing loop. Therefore, according to

different applications, designers need to make a tradeoff between those two aspects.

(b) Example of Outer-Loop Current Sharing Control

The paralleling boost converter system in Figure 2.2 is again used as the example to

demonstrate the change of output impedances. Figure 2.13 illustrates the system structure.

One particular design of Tcs is shown in Figure 2.14, where its crossover frequency is

around 30 Hz. In order to illustrate Tcs’s influence, the output impedances before and after

64


applying current sharing control is compared: Zo1 and Zo2 are the original closed-loop

impedances; they are the same as Figure 2.5(a). Zcs1 and Zcs2 are the modified impedances

with current sharing control.

Tv1

Tv2

Zcs1

Zcs2

Zcs1

Zcs2Zo2Zo2

Zo1

Zcso

Figure 2.13. The paralleling boost system with outer-loop current sharing.

According to (2.25), which is rewritten here as:

csoo

oo

cscs

cscs

o

oo

TZZZZ

ZZZZ

iii

+×

+−

=+−

=−

11

ˆˆˆ

12

12

12

1221 , (2.29)

the dynamic current sharing error is attenuated inside Tcs’s bandwidth. Therefore, Zcs1 and

Zcs2 are pulled together below 30 Hz, as shown in Figure 2.14. Because of improved match

between the DC output resistances, the steady-state current sharing error is greatly reduced

with this active current sharing control. However, the major difference between

impedances around 3-kHz is not compensated due to limited Tcs bandwidth. As a result,

although the steady-state performance is greatly improved, the time domain dynamic

response is not improved, as shown in Figure 2.15.

65


1 10 100 1 .10 3 1 .10 4 1 .10 5100

80604020

020

401 10 100 1 .10 3 1 .10 4 1 .10 5

60

40

20

0

20

1 10 100 1 .10 3 1 .10 4 1 .10 560

40

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

fs/2

Zo1

ΔZo

Zo2

ΔRo

Loop

gai

n T c

s(d

B)

Out

put I

mpe

danc

es (d

B)

Tcs

fc=30Hz

Zcs2

Zcs1

ΔZcs

ΔRcs

Figure 2.14. Change of output impedances after applying outer-loop current sharing control: Zo1 and

Zo2 – without current sharing; Zcs1 and Zcs2 – with current sharing control (Tcs crossovers at 30 Hz).

(A)


ΔssΔdyn

io1

io2

(A)io1

io2

(a) without current sharing. (b) with outer-loop current sharing (Tcs@30Hz).

Figure 2.15. The dynamic current sharing responses comparison.

66


Apparently, to improve the dynamic current sharing response, Tcs has to be designed

with a bandwidth higher than the frequency where there is significant discrepancy between

the output impedances. For this purpose, the expression of Tcs needs to be carefully

examined. In (2.24), if assume Tv1≅Tv2 and Zo1≅Zo2, some insights can be obtained

regarding Hcs’s design:

11

vOL

cscs T

ZHT ⋅≈ . (2.30)

1 10 100 1 .10 3 1 .10 4 1 .10 5100

80604020

020406080

1 10 100 1 .10 3 1 .10 4 1 .10 5360

270

180

90

0

1 10 100 1 .10 3 1 . 10 4 1 .10 580

60

40

20

0

20

40

Frequency (Hz)

Mag

nitu

de (d

B)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)

Hcs fs/2

ZOL1

OL1

cs

ZH

-1-2

Tv1

V1OL1

cscs T

ZHT ⋅≈

-2-3

-1

-1

-2

0dB

-1-2

-3

Tcs

Tcs

Tv1

Tv1

ZOL1

Hcs

30Hz 10kHz

(a) Asymptotical sketch of Tcs design. (b) Low Tcs bandwidth with the simple Hcs.

Figure 2.16. Low Tcs bandwidth is resulted with a simple Hcs.

67


Therefore, if Hcs can be designed to follow the open-loop impedance’s shape, then Tcs

can have similar loop gain as Tv. Follow this design philosophy, it is possible to achieve

high Tcs bandwidth. Nevertheless, in the design of Figure 2.14, one commonly used Hcs is

applied: the compensator with low-frequency pole [22][40]. Figure 2.16 illustrates an

example of this kind of Hcs.

1 10 100 1 .10 3 1 .10 4 1 .10 520

10

0

10

20

30

40

1 10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

40

60

80

1 10 100 1 .10 3 1 .10 4 1 .10 5360

270

180

90

0

Frequency (Hz)

Mag

nitu

de (d

B)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)

fs/2

Hcs

Hcs

ZOL1

OL1

cs

ZH

Tv1

V1OL1

cscs T

ZHT ⋅≈

-2-3

Tcs

Tcs

Tv1

Tv1

ZOL1

-1

-10dB

10kHz6kHz

(a) Asymptotical sketch of Tcs design. (b) Much higher Tcs bandwidth is achieved.

Figure 2.17. High Tcs bandwidth is achieved with proposed Hcs.

68


With a voltage-mode control, according to Figure 2.16(a), the -1 slope in Hcs/ZOL1

results in -2 slope in Tcs. Hence, the bandwidth of Tcs is very low comparing with that of

Tv1 due to inadequate phase margin. Consequently, the dynamic current sharing

performance is not improved with this design, as demonstrated in Figure 2.15. As a

comparison, Figure 2.17 proposes a Hcs design which leads to much higher bandwidth of

Tcs.

1 10 100 1 .10 3 1 .10 4 1 .10 560

40

20

0

201 10 100 1 .10 3 1 .10 4 1 .10 5

40

20

0

20

40

60

801 10 100 1 .10 3 1 .10 4 1 .10 5

60

40

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

fs/2Zo1 ΔZoZo2

ΔRo

Loop

gai

n T c

s(d

B)

Out

put I

mpe

danc

es (d

B)

Tcs

fc=6kHz

Zcs2

Zcs1

ΔZcs

ΔRcs

Figure 2.18. Change of output impedances after applying outer-loop current sharing control: Zo1 and

Zo2 – without current sharing; Zcs1 and Zcs2 – with current sharing control (Tcs crossovers at 6 kHz).

69


Since the phase delay in Tv1 will also appear in Tcs, it is not practical to design Tcs’s

bandwidth higher than that of Tv1 for the discussed outer-loop current sharing structure.

Therefore, in Figure 2.17(b), Tcs’s crossover frequency is a little lower than Tv1 to

guarantee adequate phase margin. With a much higher current sharing loop gain and

bandwidth, the discrepancy between output impedances below 6 kHz can be reduced,

which leads to improved dynamic current sharing performance, as shown in Figure 2.18

and Figure 2.19. However, due to a quickly dropping phase margin, there is no room to

increase Tcs’s bandwidth further more. Therefore, the gain of Tcs around 6 kHz is limited.

As the result, the impedance cannot be pulled to match each other perfectly. Nevertheless,

the reduction of the impedances’ difference is good enough to reduce the over current

during the load transient.

(A)


ΔssΔdynio2

io1(A)io1

io2

(a) without current sharing. (b) with outer-loop current sharing: faster Tcs.

Figure 2.19. The dynamic current sharing responses comparison.

From these two design example, it can be seen that the desired bandwidth of Tcs is

greatly related to specific applications. In another word, the frequency range where original

output impedances have the largest discrepancy determines the effective point of Tcs’s

function. Only when Tcs have a higher bandwidth than that, it is useful in improving

dynamic current sharing response of a paralleling system.

70


In Figure 2.19(b), the current oscillations are within the specified over-current limit

of 120%. In this particular paralleling system, the over-current issue is solved with a faster

current sharing loop, while the benefit from a slower current sharing control is very limited

in terms of dynamic current sharing performance.

In this application, since the difference between original output impedances, Zo1 and

Zo2, is mostly contributed by the large tolerance of boost inductances, their mismatch is

focused on a relatively low frequency range. Hence, it is possible for the outer-loop current

sharing to reduce this difference. However, if Zo1 and Zo2 have large difference in high

frequency range, which cannot be reached by Tcs’s bandwidth with outer loop structure,

then outer-loop schemes may not be the solution for this application.

On the other hand, with the design in Figure 2.17, all the delays in the voltage loop

appear in the current sharing loop. In practice, the first priority of a design is to ensure

voltage regulation. Hence, the voltage loop has been compensated with sufficient high

bandwidth. Therefore, it is impossible for Tcs to compensate the existing delays in Tv. As a

result, there is more phase delay in the current sharing loop gain. And the current sharing

loop bandwidth is practically limited by the voltage loop.

(c) Current Sharing Loop’s Impact on the Voltage Regulation Performance

For the purpose of better dynamic current sharing performance, higher gain and

wider bandwidth of Tcs is desired. However, even if we are able to do that, it is still

questionable that whether this is the best choice. When paralleled modules’ output

impedances are matched inside the bandwidth, the total output impedance of the system,

Zcso, is modified from the original Zo at the same time:

71


],4

)(1

1[

14

1

21

221

21

oo

oo

cs

cso

cs

o

oocs

ocso

ZZZZ

TT

Z

TZZZ

TZZ

⋅−

⋅+

+⋅=

+⋅+

⋅+⋅=

(2.31)

and,

ocso ZZ ≥ . (2.32)

Therefore, the system’s overall output impedance is becoming larger insider Tcs’s

bandwidth. Meanwhile, it is told from (2.31) that with a larger discrepancy between the

impedances, the current sharing control will increase the output impedances more. Hence,

the output voltage regulation is compromised with a high current sharing loop gain.

A more straightforward explanation is shown in Figure 2.20 and Figure 2.21. In

Figure 2.20, Zcs1 is compared with Zo1, and Zcs2 is compared with Zo2. Because of the

function of current sharing control, Zcs1 is increased from the smaller impedance, Zo1, while

Zcs2 is decreased from the originally larger Zo2. The final result is Zcs1 and Zcs2 are more

close to each other than Zo1 and Zo2. However, when the dynamic voltage regulation is

concerned, the overall output impedances, Zo and Zcso, need to be compared:

21 // ooo ZZZ = , (2.33)

21 // cscscso ZZZ = . (2.34)

Therefore, it is the lower impedance that is more dominant in determining the overall

impedances. In this case, the first module always has lower impedances. However, this

impedance is increased due to the current sharing control. Hence, the overall output

impedance, Zcso is always larger than Zo, as shown in Figure 2.21.

72


10 100 1 . 103 1 . 104 1 . 10540

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B) fs/2

10 100 1 . 103 1 . 104 1 . 10540

20

0

20

Zcs1

Zo1

Frequency (Hz)

Out

put I

mpe

danc

es (d

B) fs/2

Zcs2

Zo2

(a) Zo1 – without CS; Zcs1 – with CS. (b) Zo2 – without CS; Zcs2 – with CS.

Figure 2.20. Output impedances’ change with outer-loop current sharing (faster Tcs design).

10 100 1 . 103 1 . 104 1 . 10540

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

Zcso

Zo

w/ CS fs/2

w/o CS

Figure 2.21. Total output impedance comparison: Zo – without CS, Zcso – with CS (faster Tcs design).

As the result of higher Zcso, the system’s dynamic voltage regulation is compromised.

Figure 2.22 compares the simulation waveform of vo. With a fast current sharing loop, vo

has more undershoot than the case without active current sharing control. Therefore, the

design of Tcs should consider both dynamic current sharing and voltage regulation

performance of the whole paralleling system. Tradeoff has to be made according to

specifications. If no acceptable solution can be found based on the outer-loop structure,

73


other active current sharing control schemes such as dual or inner-loop structures may be

selected as alternatives.


5 5.5 6 6.5 7

V

560

570

580

590

600

610vo (V)

w/o current sharingw/ outer-loop, faster Tcs

5 5.5 6 6.5 (ms)560

580

600


5 5.5 6 6.5 7

610

V

560

570

580

590

600

vo (V)

w/o current sharingw/ outer-loop, faster Tcs

560

580

600

5 5.5 6 6.5 (ms)

Figure 2.22. Output voltage response with outer-loop current sharing.

(d) Summary

Table 2.3 summarizes the basic characteristics of the outer-loop current sharing

control. With limited current sharing loop bandwidth, the dynamic current sharing

performance is limited. However, it has superior modularity. Therefore, for the

applications where the dynamic current sharing performance is not strictly required while

good system flexibility is needed, such as most of the paralleled front-end converters or

some load converters, the outer-loop current sharing scheme is a good choice.

Table 2.3. Summary for outer-loop current sharing control.

Current sharing loop bandwidth Relatively low

ΔZ vs. Tcs ΔZ is attenuated by Tcs

Zcso vs. Tcs Zcso is increased inside Tcs

Applications Paralleled modules with limited dynamic requirement

74


2.2.2 Dual-Loop Current Sharing Control

The dual-loop current sharing structure is shown in Figure 2.23: both of the current

sharing controller, Hi, and the voltage regulation controller, Hv, influence the generation of

duty-cycle signal. While, there is no direct interaction between the two control loops. The

major field that employs the dual-loop regulation is the multiphase voltage regulators, such

as the control ICs of IR3086, IR3093, L6919, L6710, ISL6561, and LM27262, etc. In

addition, it has been reported that this control structure is also used in distributed power

systems [35]. Other examples of dual-loop current sharing can be found in [30].

vc1

io1vin

Tv1

+-

Hv

CS_Bus

Vref1

+-

Hcs

-+

Hvvc2Vref2

+-

io2

Tv2

vo

vcso2

vcso1 +-

Hcs+

-

Power stage #1

2ii o2o1 +

Power stage #2

VR_Bus

io

Zcs1 Zcso

Zcs2

Figure 2.23. Dual-loop current sharing control structure.

To solve the voltage regulation conflicting problem caused by different Vref1 and Vref2,

a voltage regulation bus is also needed as shown. Of course, it is also possible to use just

75


one voltage feedback loop to save the cost. Comparing with the outer-loop structure in

Figure 2.9, the only difference is that the current sharing error signal, vcso1 and vcso2, do not

go through the voltage compensator Hv anymore. Thus, dual-loop structure is a decoupled

version of the outer-loop structure.

(a) Output Impedances Derivation

The output impedances of dual-loop structure, Zcs1 and Zcs2, can be derived with the

same process as the outer-loop case. It is obtained

2211

21211 )1(

)1(

ocsocs

oocscscs ZTZT

ZZTTZ

⋅++⋅⋅⋅++

= , (2.35)

1122

21212 )1(

)1(

ocsocs

oocscscs ZTZT

ZZTTZ

⋅++⋅⋅⋅++

= . (2.36)

where,

11

11

112 ov

vdmCScs ZT

GFHT ⋅

+⋅= , (2.37)

22

22

112 ov

vdmCScs ZT

GFHT ⋅

+⋅= . (2.38)

Substituting (2.35)~(2.38) into (2.13), it is obtained that the dynamic current sharing

error is

csoo

oo

cscs

cscs

o

oo

TZZZZ

ZZZZ

iii

+×

+−

=+−

=−

11

ˆˆˆ

12

12

12

1221 , (2.39)

where the current sharing control loop gain, Tcs, is defined as

76


)11

(2

2

1

1

21 v

vd

v

vd

oo

mcscs T

GT

GZZFH

T+

++

⋅+⋅

= . (2.40)

Similar to outer-loop case, Tcs represents the dynamic current sharing performance.

The function of the current sharing loop gain still is to match the output impedances inside

its bandwidth. Therefore, a higher current sharing loop bandwidth is also desired for the

dual-loop control schemes.

Comparing (2.24) with (2.40), it is observed that different from the outer-loop

structure, there is no voltage loop information included in Tcs for dual-loop schemes. This

is because the current sharing loop is in parallel with the voltage loop. Without Hv or Tv

included in the current sharing loop gain, there is no integrator 1/s from Hv appearing in

Tcs. Therefore, an infinite-DC-gain Hcs does not impact the stability of Tcs. There is no

conditional stability issue due to the infinite DC gain of Hcs. This means a zero steady-state

current sharing error is achievable with the dual-loop current sharing.

(b) Design Example

Applying the dual-loop structure to the paralleling boost converter system in Figure

2.2 leads to the implementation in Figure 2.24. The elimination of Hv or Tv in Tcs removes

the low-pass filters of the voltage loop.

Apparently, to improve the dynamic current sharing response, Tcs has to be designed

with a bandwidth higher than the frequency where there is significant discrepancy between

the output impedances. For this purpose, the expression of Tcs needs to be carefully

examined. Similar as the process in the outer-loop case, if assume Tv1≅Tv2 and Zo1≅Zo2,

some insights can be obtained regarding Hcs’s design:

77


1

1

1

1

1 1 OL

vdcsm

v

vd

o

mcscs Z

GHFT

GZ

FHT ⋅=+

⋅⋅

≈ . (2.41)

Zcso

Zo1 Zcs1Zcs1Zo1Tv1Tv1

Zo2Zo2 Zcs2Zcs2Tv2Tv2

Figure 2.24. Applying dual-loop current sharing to the paralleling boost system.

Figure 2.25(a) illustrates the asymptotical sketch of the transfer functions used in the

design. With the aforementioned assumptions, there is perfect cancellation of the poles and

zero in Gvd1/ZOL1, which is the plane to be compensated. There is only one pole in the

plane; therefore, with a simple Hcs as shown in Figure 2.25(a), it is possible to achieve high

Tcs bandwidth. Using this design method, Figure 2.25(b) demonstrates an example with the

parameters above. A current sharing faster than the voltage loop is realized.

78


1 10 100 1 . 103 1 . 104 1 . 10540

20

0

20

40

60

80

1 10 100 1 . 103 1 . 104 1 . 105360

270

180

90

0

1 10 100 1 . 103 1 . 104 1 . 10520

0

20

4060

80

100

120

Frequency (Hz)

Mag

nitu

de (d

B)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)

fs/2Gvd1

Hcs

OL1

vd1

ZG

ZOL1

OL1

vd1cscs Z

GHT ≈

Tcs

Tcs

Tv1

Tv1

Gvd1/ZOL1

Hcs

10kHz 18kHz

(a) Asymptotical sketch of Tcs design. (b) Tcs design for dual loop CS.

Figure 2.25. Tcs design for dual loop current sharing control.

As a result, the output impedances of the two converters are matched in a wider

frequency range in Figure 2.26 than the outer-loop case. The transient response waveforms

of output currents are demonstrated in Figure 2.27, where the output current overshoots are

minimized because of the well-matched output impedances with higher current sharing

loop bandwidths.

79


1 10 100 1 . 103 1 . 104 1 . 10540

20

0

20

40

60

80

1 10 100 1 . 103 1 . 104 1 . 10560

40

20

0

20

1 10 100 1 .10 3 1 .10 4 1 .10 560

40

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

fs/2Zo1 ΔZoZo2

ΔRo

Loop

gai

n T c

s(d

B)

Out

put I

mpe

danc

es (d

B)

Tcs

fc=18kHz

Zcs2

Zcs1

ΔZcs

ΔRcs

Figure 2.26. Change of output impedances after applying dual-loop current sharing control: Zo1 and

Zo2 – without CS; Zcs1 and Zcs2 – with dual loop CS.

ΔssΔdynio2 ΔssΔdyn

io2

io1(A) io1(A)

(a) Transient response with outer-loop. (b) Transient response with dual-loop.

Figure 2.27. Dynamic current sharing performance comparison.

80


(c) Voltage Regulation Performance

For the purpose of better dynamic current sharing performance, higher gain and

wider bandwidth of Tcs is also desired for dual-loop scheme. Therefore, it is also necessary

to exam the voltage regulation performance based on the total output impedance of the

system, Zcso. Similarly as the outer-loop scheme, it is derived that

].4

)(1

1[

14

1

21

221

21

oo

oo

cs

cso

cs

o

oocs

ocso

ZZZZ

TT

Z

TZZZ

TZZ

⋅−

⋅+

+⋅=

+⋅+

⋅+⋅=

(2.42)

Therefore, there is,

ocso ZZ ≥ . (2.43)

Clearly, if outside the current sharing bandwidth, there is no influence from Tcs; hence,

under this condition, Zcso remains the same as Zo. While, inside Tcs, the output impedance is

increased, and the larger difference the paralleled modules, there is larger impedance of the

entire system.

Compared with the outer-loop current sharing, the equations are similar for Zcso.

However, as aforementioned, a higher current sharing bandwidth is achieved with the dual-

loop scheme. Since the total output impedance becomes larger as Tcs becomes faster for

both the outer-loop and dual-loop structures in a similar way described in (2.31), the dual-

loop design improves current sharing but suffers voltage regulation during dynamics.

There is always a tradeoff between dynamic current sharing and voltage regulation. The

fundamental conflicting comes from the fact that one control variable (duty cycle) has to

81


take care of two requirements. Comparing with outer-loop case (with a 30-Hz Tcs

bandwidth), Figure 2.28 shows the increase of the overall output impedance, Zcso. As the

result, Figure 2.29 shows the degraded output voltage’s response of dual-loop current

sharing control.

10 100 1 . 103 1 . 104 1 . 10540

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

Zcso

w/ DLR fs/2

w/ OLR

Figure 2.28. Comparison of the total output impedances with dual-loop and outer-loop controls: OLR

case– Tcs crossover at 30 Hz; OLR case– Tcs crossover at 18 kHz;.

5 5.5 6 6.5 7

V

560

570

580

590

600

610vo (V)

w/ dual-loop

w/ outer-loop

560

580

600

5 5.5 6 6.5 (ms)

Figure 2.29. Output voltage responses comparison between dual-loop and outer-loop controls.

(d) Possibility of Interaction Between Tcs and Tv

Because of its configurations, the dual-loop structure is able to achieve fast current

sharing during transient than the outer-loop case. However, we need to be very careful

82


about one potential problem: with the current sharing loop and the voltage regulation loop

in parallel, there is the possibility of the interference between the two loops.

In the previous design guideline, it is assumed that the paralleled modules are similar

to each other so that the design is simplified. However, if there is significant difference

between the modules, there are potential issues because the zeroes and poles cannot be

perfectly cancelled.

For example, in the current sharing loop gain is

)11

(2

2

1

1

21 v

vd

v

vd

oo

mcscs T

GT

GZZFH

T+

++

⋅+⋅

= . (2.44)

Under the condition of

12 oo ZZ > , (2.45)

2

2

1

1

11 v

vd

v

vd

TG

TG

+>

+, (2.46)

there is

1

2

2

1

1

1

2 11

1 v

v

OL

vdmcs

v

vd

o

mcscs T

TZGFH

TG

ZFHT

++

⋅⋅=+

⋅⋅

≈ . (2.47)

Figure 2.30~Figure 2.32, explains the generation of the additional poles and zeroes,

and thus more delays in Tcs around the voltage loop bandwidth. Figure 2.33 illustrates the

design. Ideally, with the given circuit parameter tolerances, an 18-kHz bandwidth is

obtained with sufficient phase margin. However, if there is more tolerance, the phase drop

in Tcs is significant between the two modules voltage loop gain. Therefore, if Tcs bandwidth

is designed higher than that, potential conditional stable might happen. If it has similar

83


bandwidth around Tv, the insufficient phase margin results in undesired spikes in the

impedances, as shown in Figure 2.33(b).

Gvd1

ZOL1

Gvd1

ZOL2

OL1

vd1

ZG

OL2

vd1

ZG

(a) Without significant difference in modules. (b) With significant difference in modules.

Figure 2.30. Mismatching of the modules leads to more poles and zeroes in Gvd1/ZOL2.

1+Tv21+Tv2

1+Tv1

fc_Tv1

1+Tv1

fc_Tv1

V1

V2

T1T1

++

V1

V2

T1T1

++

fc_Tv2fc_Tv2 (a) Without significant difference in modules. (b) With significant difference in modules.

Figure 2.31. Mismatching of the modules leads to more poles and zeroes from Tv1 and Tv2.

84


V1

V2

OL2

vd1

T1T1

ZG

++

⋅

-2-1V1

V2

OL2

vd1cscs T1

T1ZGHT

++

⋅≈

csH

V1

V2

OL2

vd1

T1T1

ZG

++

⋅

V1

V2

OL2

vd1cscs T1

T1ZGHT

++

⋅≈

csH

fc_Tv1

fc_Tv2 fc_Tv1 fc_Tv2 (a) Without significant difference in modules. (b) With significant difference in modules.

Figure 2.32. Mismatching of the modules leads to delays in Tcs around the voltage loop bandwidth.

Figure 2.34 shows the resulted time domain output currents and voltage responses.

The current is over the limitations with long settling time, while the voltage undershoot is

much bigger. Moreover, the oscillations in the output currents are reflected in the output

voltage waveform due to interaction of two feedback control loops.

Therefore, one should be careful to avoid the interference between the current

sharing loop and voltage regulation loop. This is especially important when using dual-

loop structures, because it gives designer the possibility to do so. Meanwhile, another

disadvantage of dual-loop schemes should be mentioned here: there are two buses needed

as interconnection among paralleled modules, which makes it less reliable and more

sensitive to noises.

85


1 10 100 1 . 103 1 . 104 1 . 105360

270

180

90

01 10 100 1 . 103 1 . 104 1 . 105

40

20

0

20

40

60

80

1 10 100 1 . 103 1 . 104 1 . 10560

40

20

0

20

Frequency (Hz)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)M

agni

tude

(dB

)

18kHz

fs/2

1 10 100 1 . 103 1 . 104 1 . 105360

270

180

90

01 10 100 1 . 103 1 . 104 1 . 105

40

20

0

20

40

60

80

1 10 100 1 . 103 1 . 104 1 . 10560

40

20

0

20

Frequency (Hz)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)M

agni

tude

(dB

)

10kHz

fs/2

Zcs1Zcs2

Tcs

Tv2

Tv1

Tv2

TcsTv1

Zcs1Zcs2

Tcs

Tv2

Tv1

Tv2

TcsTv1

(a) Without significant difference in modules. (b) With significant difference in modules.

Figure 2.33. Possible issue for Tcs design with dual-loop current sharing.

time/mSecs 1mSecs/div

5 6 7 8 9 10

V

0

2

4

6

8

10

12

14

16

5 5.5 6 6.5 7 (ms)0

4

8

12

16Io1, Io2 (A)

Over current limit: 120%Io


5 6 7 8 9 10

vout

/ V

550

560

570

580

590

600

610

620

5 5.5 6 6.5 7 (ms)

Vo (V)

560

580

600

620

(a) Output currents responses. (b) Output voltage response.

Figure 2.34. Output currents and voltage responses with dual-loop current sharing in Figure 2.33(b).

86


On the other hand, Tcs for outer-loop control’s current sharing was defined as:

)11

(2

2

1

1

21 v

v

v

v

oo

cscs T

TT

TZZ

HT

++

+⋅

+= . (2.48)

With the similar assumption as that of dual loop:

12 oo ZZ > , (2.49)

(2.48) is simplified as:

)11

(2

2

1

1

2 v

v

v

v

o

cscs T

TT

TZHT

++

+⋅≈ . (2.50)

Because Tcs has much lower bandwidth than the voltage loop gain, at the crossover

frequency of Tcs, it can be assumed that

11 1

1 ≈+ v

v

TT , (2.51)

11 2

2 ≈+ v

v

TT . (2.52)

Therefore, it is obtained:

)1(222

22v

OL

cs

o

cscs T

ZH

ZHT +=≈ . (2.53)

Therefore, even the two modules’ voltage loops are of large difference, (2.53) does not

lead to the extra phase delay due to interaction. Hence, with the voltage loop and current

sharing loop well separated for the outer-loop current sharing structure, there is no concern

of interaction between these two loops. Namely, it is a special issue for dual loop current

sharing, since it offers the flexibility of Tcs bandwidth design.

87


(e) Noise Sensitivity

Another potential issue for the dual-loop design is the noise sensitivity. Because the

current sharing bus connects paralleled modules, it is easy to catch the noise inside a

system, such as the AC line frequency and its harmonics, the beat-frequency when the

modules are not synchronized, etc. As shown in Figure 2.35, the perturbation on the

current sharing bus modifies the reference for the current sharing compensator. It is

derived that

)(2112 21

2

2

1

1oo

cs

v

vd

v

vdcsm

noise

o ZZT

TG

TGHF

vv

+⋅=⎟⎟⎠

⎞⎜⎜⎝

⎛+

++

⋅= . (2.54)

Therefore, even the two modules are identical, the output voltage responses to the current

sharing bus noise. Meanwhile, with a higher Tcs gain, there is stronger response, which

means the system is more noise sensitive. This is because the current sharing loop can only

attenuate the difference between the output currents.

Tv1Tv1

Tv2Tv2

Zo2

Zo1

Zo2

Zo1

TcsTcs

Figure 2.35. Dual loop with noise perturbation on the current sharing bus.

88



0 2 4 6 8 10-12-8-4048

12

Vno

ise

(mV

)


0 2 4 6 8 10580

590

600

610

620V

o(V

)

Time (ms)

Figure 2.36. Output voltage’s response to noise perturbation on the current sharing bus for dual loop

current sharing structure.

Figure 2.36 illustrates the time-domain response with the design in Figure 2.26. With

a 5-mV 360-Hz perturbation on the current sharing bus, there is 18-V output voltage

response. Therefore, it is necessary in the design to ensure the bus is high noise immunity.

The similar issue also exists for the outer-loop case. It can be derived that for outer-

loop case in side the voltage loop bandwidth,

)(2 21 oocs

csmnoise

o ZZT

HFvv

+⋅=≈ . (2.55)

However, because the Tcs gain is much lower, the noise issue is not as severe as that of the

dual-loop case. As a comparison, Figure 2.37 shows the response of the output voltage for

the outer-loop case with 6-kHz bandwidth. With the same noise perturbation, there is only

5-V response at the output.

89



0 2 4 6 8 10-12-8-4048

12


0 2 4 6 8 10580

590

600

610

620

Time (ms)

V noi

se(m

V)V

o(V

)

Figure 2.37. Output voltage’s response to noise perturbation on the current sharing bus for outer loop

current sharing structure..

(f) Summary

Table 2.4 summarizes the basic characteristics of the dual-loop current sharing

control. The current sharing loop bandwidth design is flexible and could be higher than the

voltage loop. Hence, comparing with outer-loop, better dynamic current sharing

performance is achievable for dual loop current sharing schemes. On the other hand, higher

current sharing loop gain and bandwidth leads to worse noise immunity for dual loop than

outer loop. Plus, one needs to pay attention to the potential interaction between the two

loops. Besides, its modularity is not as good as outer-loop. In summary, for the

applications where the dynamic current sharing is required and requires good system

flexibility, the dual-loop structure shows its advantages.

90


Table 2.4. Summary for dual-loop current sharing control.

Current sharing loop bandwidth Flexible, could be high. But it is recommended to

separate Tcs and Tv’s bandwidth.

Applications Paralleled phases or modules with stringent dynamic

requirement


Zcso vs. Tcs Zcso is increased inside Tcs

Interaction between Tcs and Tv Possible

Noise immunity Poor

2.2.3 Inner-Loop Current Sharing Control

Figure 2.38 shows the control scheme for the inner-loop current sharing control.

Inner-loop structure mostly is used based on the current-mode control. It utilizes the output

of voltage compensator, Hv, to serve as the current sharing bus. Since every module forces

its current to follow the same reference on the bus, current balance can be obtained.

There are several major differences between the inner-loop scheme and the outer-

loop method in Figure 2.9. First, in most of the practices, the current feedback loop is also

used as the current sharing loop, and it is inside the voltage feedback loop. Second,

considering the purpose of current-mode control, the inductor current is sensed and fed

back instead of the output currents. Third, the current sharing function is realized by

91


forcing each phase’s current to follow the control voltage, vc, instead of the average

currents, and there is no direct current information used as the reference bus.

iL1

vin

T2

+-

CS_BusVref

Hv

-+

iL2

vo

+-

Power stage #2

Power stage #1io

Hi

Hi

io1

io2

Zcs1 Zcso

Zcs2

Vc

Figure 2.38. Inner-loop current sharing control structure.

There are two very common implementations in this category: the average-current-

mode control and the peak-current-mode control. In both schemes, the current sharing

control can be combined with the current feedback control. Among them, the peak-current-

mode control is widely used in the application of multi-phase buck voltage regulators to

guarantee the current sharing among paralleling phases. Lots of IC venders have

manufactured dedicated controllers that adopt the peak-current-mode control, such as

LTC3738, MAX8525, SC2643, NCP5318, TPS40090, ADP3188, and FAN5019B.

Similar studies based on the output impedance concept can be conducted for inner-

loop control structure. The dynamic current sharing performance can still be evaluated

based on how well each module current shares under load transients. Because the bus

92


signal may not directly represent the total output current for different control schemes

and/or bus implementations, sometimes it is necessary to study dynamic current sharing

error under perturbations from both the output current and the current sharing bus.

(a) Output Impedances Derivation

In the inner-loop current sharing structure, the current sharing loop is directly added

upon the power stage. Therefore, the influence of current sharing loop is revealed based on

the open-loop impedances. In the paralleling boost system of Figure 2.39, ZOL1 and ZOL2

are the open-loop output impedances of two power stages.

Tcs1Tcs1

Tcs2Tcs2

Zcc1Zcc1ZOL1

Zcc2Zcc2ZOL2

Figure 2.39. Inner-loop current sharing control with voltage loop open.

Clearly, the voltage loop has no function of reducing the difference between the

modules. Therefore, as the first step, the output impedances with only the current loops

closed, as shown in Figure 2.39, are calculated [45][46]:

93


cs

OLccsOLcc T

ZZTZZ+

+⋅=

1/1 11

11 , (2.56)

cs

OLccsOLcc T

ZZTZZ+

+⋅=

1/1 22

22 . (2.57)

Zc1 and Zc2 are the impedances of the output capacitors, and the current sharing loop gain is

defined as

esidmcs HRGFT 11 = . (2.58)

Where Fm is the modulator gain, Gid1 is the duty-cycle-to-inductor-current transfer function

of the first module, Rs is the current sensing gain, and He represents the sample-hold effect

[47].

Based on (2.58), because the current loop is inside, there is no voltage loop’s

influence. Meanwhile, the current loop is normally much higher than the voltage loop.

Hence, there is no interaction between the two loops.

A higher current loop gain makes the inductor current behaviors like a controlled

current source. Therefore, inside Tcs’s bandwidth, it is simplified

11 ccc ZZ ≈ , (2.59)

22 ccc ZZ ≈ . (2.60)

Hence, with a sufficient high bandwidth, the inductor becomes a perfect current

source due to the current feedback loop, so that the impedance difference from the

inductors is attenuated. The only component observable from output terminal is the output

capacitor. Next, if the voltage loop is closed, as shown in Figure 2.40, the output

impedances are modified to

94


cs

OLccsOLcccs T

ZZTT

ZT

ZZ+

+⋅

+=

+=

1/1

1111

2

1

2

11 , (2.61)

cs

OLccsOLcccs T

ZZTT

ZT

ZZ+

+⋅

+=

+=

1/1

1122

2

2

2

22 . (2.62)

Where,

esidemcs HRGFT = . (2.63)

cs

v

TTT+

=12 , (2.64)

vvdemv HGFT = . (2.65)

Gide and Gvde are the equivalent control-to-total-inductor-current and control-to-output-

voltage transfer function of the system. T2 is the effective voltage feedback loop gain.

Tcs1Tcs1

Tcs2Tcs2

Zcs1Zcs1 Zcso

T2

Zcs2Zcs2

Figure 2.40. Inner-loop current sharing control with voltage loop closed.

95


Clearly, the voltage loop gain does not change the relative difference between the

output impedances. And the dynamic current sharing response is calculated as

OLccsOLOL

OLOL

cccc

cccc

cscs

cscs

o

oo

ZZTZZZZ

ZZZZ

ZZZZ

iii

/11

ˆˆˆ

12

12

12

12

12

1221

+×

+−

=+−

=+−

=− . (2.66)

Where Zc is the total output capacitor’s impedance, ZOL is the total open-loop impedance of

the paralleling system. According to (2.66), the function of current sharing loops is similar

to that of outer-loop structure: attenuate dynamic current sharing error inside its bandwidth

by reducing ΔZcs. Of course, because of different control structures, these two have

different ability of pushing Tcs’s bandwidth.

(b) Design Example

A design example is shown in Figure 2.41. Because the inner-loop structure is

fundamentally the current-mode control, a high bandwidth is achieved for the current

sharing loop. Therefore, with only the current loops closed, the output impedances, Zcc1

and Zcc2 matches very well inside the current sharing loop bandwidth. Meanwhile, because

two paralleled modules shares the same voltage feedback loop, the final output

impedances, Zcs1 and Zcs2, also have reduced difference.

According to (2.61), Zcs1 is attenuated from Zcc1 by T2 inside its bandwidth. Figure

2.42 shows the comparison between Zcc and Zcs. Compared with the outer-loop current

sharing control, a better match between Zcs1 and Zcs2 is obtained with a higher current

sharing loop bandwidth. As a result, there is almost no overshoot during the load transient

in the output currents, as demonstrated in Figure 2.43.

96


10 100 1 .10 3 1 .10 4 1 .10 520

0

20

40

60

10 100 1 .10 3 1 .10 4 1 .10 520

0

20

40

10 100 1 .103 1 .104 1 .10520

0

20

40

60

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

fs/2

10 100 1 .10 3 1 .10 4 1 .10 5

20

0

20

4010 100 1 .10 3 1 .10 4 1 .10 5

20

0

20

40

6010 100 1 .10 3 1 .10 4 1 .10 5

20

0

20

40

60

Frequency (Hz)

fs/2

Out

put I

mpe

danc

es (d

B)

ΔZcc

Zcc2ZOL1

ΔZo

ZOL2

Tcs

Loop

gai

n T c

s(d

B)

Out

put I

mpe

danc

es (d

B)

ΔZcc

fc=35kHz

Zcc2

Zcc1

Zcc1

T2

Loop

gai

n T 2

(dB

)O

utpu

t Im

peda

nces

(dB

)

ΔZcs

fc=10kHz

Zcs2

Zcs1

Figure 2.41. Change of output impedances after

applying inner-loop current sharing control: ZOL1

and ZOL2 – open-loop impedances; Zcc1 and Zcc2 –

with current loop closed while voltage loop open.

Figure 2.42. Change of output impedances after

applying inner-loop current sharing control: Zcc1

and Zcc2 – with current loop closed while voltage

loop open; Zcs1 and Zcs2 – with both current and

voltage loop both closed;

There is a very importance difference between outer-loop/dual-loop and inner-loop

structures. For outer-loop and dual-loop schemes, there exists communication between two

modules’ output currents, thus the output impedance of one module are modified by other

97


paralleled modules. Inner-loop structure, on the other hand, achieves current sharing by

forcing all modules to function like controlled current sources. The reduction of impedance

difference is accomplished by increasing inductor’s impedance through current feedback

loops. Therefore, inner-loop structure is not capable of compensating the difference among

output capacitors when inductor currents are sensed and fed back.

5 6 7 8 9 100

2

4

6

8

10

12

5 5.5 6 6.5 7

4

8

12

(ms)0

io1, io2 (A)

Figure 2.43. Dynamic current sharing for two paralleled converters with inner-loop current sharing.

(c) Current Sharing Control’s Impact on Voltage Regulation

Since the current feedback loop changes the output impedances of paralleled

modules, it also has impact on the overall output impedance of a paralleling system. It can

be obtained that the system’s overall output impedance, Zcso, is

cs

OLcccsOLcso T

ZZZTT

ZZ+

⋅+×

+=

1/)//(1

121

2

. (2.67)

Where ZOL is the overall open-loop output impedance of the paralleling system, it is

determined by the open-loop output impedances of two individual modules:

21

21

OLOL

OLOLOL ZZ

ZZZ+

= . (2.68)

98


The second term of (2.67) has a gain larger or equal to 1, which means the current

feedback loop increases the overall output impedance. On the other hand, the attenuation

from T2 loop gain reduces magnitude of Zcso inside its bandwidth. The final result of Zcso is

a combination of these two effects.

As a comparison, the Zcso for outer-loop current sharing control can be written as

cs

OL

OLOLcs

v

OLcso T

ZZZT

TZZ

+⋅+

⋅+×

+=

14

1

1

21

, (2.69)

where ZOL is also the overall open-loop output impedance of the paralleling system. It can

be seen that the second term of (2.67) has bigger influence in the low-frequency range than

that of (2.69), since (Zc1//Zc2)/ZOL is normally pretty large in that range. On the other hand,

the magnitude of (2.69)’s second term is determined by the difference between ZOL1 and

ZOL2, which is usually smaller.

In most of the inner-loop applications, the voltage loop compensator is redesigned

considering the existence of the current loop. Figure 2.44 compares Zcso for outer-loop and

inner-loop current sharing controls with similar voltage regulation loop bandwidth. The

current sharing loop gain design for the outer-loop case in this comparison adopts the

higher-bandwidth design in Figure 2.18. Since the current feedback loop increases output

impedances in the low-frequency range, it is expected that inner-loop structure resulting in

longer settling time of vo. But the peak value of Zcso is similar. Therefore, inner-loop

current sharing structure is able to achieve similar voltage undershoot with improved

dynamic current sharing performances.

99


10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

10 100 1 .10 3 1 .10 4 1 .10 540

20

0

20

Frequency (Hz)

Out

put I

mpe

danc

es (d

B)

fs/2

Outer-loop

Inner-loop

Zcso

(a) The overall output impedance of the paralleling system with inner-loop current sharing.

5 5.5 6 6.5 7 7.5 8

V

560

570

580

590

600

610

vo (V)

w/ inner-loop

w/ outer-loop

5 5.5 6 6.5 (ms560

580

600

7 7.5 )

(b) The corresponding time domain dynamic responses of output voltage under load step change.

Figure 2.44. Overall impedance comparison between inner-loop and outer-loop structures.

(d) Noise sensitivity

Due to well separated Tcs and Tv bandwidth, it usually not a concern of the interaction

problem for the inner-loop current sharing schemes. However, the noise sensitivity aspect

needs to be studied. To investigate the noise sensitivity for the inner-loop case, a noise

source is inserted in the control voltage, as shown in Figure 2.45. It is then derived that

100


1

1

1 csv

vdm

noise

o

TTGF

vv

++≈ . (2.70)

Tcs1Tv

Tcs2

Figure 2.45. Inner loop current sharing scheme with noise perturbation on the current sharing bus.


0 2 4 6 8 10-12-8-4048

12


0 2 4 6 8 10580

590

600

610

620

Time (ms)

Vno

ise

(mV

)V

o(V

)

Figure 2.46. Output voltage’s response to noise perturbation on the current sharing bus with inner-

loop current sharing scheme.

101


Different from the outer-loop and dual-loop cases, because the current sharing loop is

combined with the current loop in inner-loop structure, it attenuates the noise in addition to

the voltage loop. Consequently, as shown in Figure 2.46, with similar amount of bus noise,

the inner-loop control’s output voltage has much better immunity than dual-loop current

sharing.

(e) Summary

Table 2.5 summarizes the basic characteristics of the inner-loop current sharing

control. With a high current sharing loop bandwidth, the dynamic current sharing

performance is improved compared with outer-loop current sharing. Moreover, inner-loop

is superior to dual-loop structure in terms of less chance of loop interaction and better

noise immunity. However, its modularity is limited compared with outer-loop case.

Therefore, for the applications where the dynamic current sharing is stringent but requires

only fair system flexibility, such as for the paralleled phases in a converter, the inner-loop

current sharing scheme is a good choice.

Table 2.5. Summary for inner-loop current sharing control.

Current sharing loop bandwidth High


Zcso vs. Tcs Zcso is increased beneath resonant frequency

Noise immunity Good

Applications Where stringent dynamic performance is required

102


2.2.4 Summary

In the analysis above, the output impedance concept is generalized to investigate the

behaviors of dynamic current sharing and the output voltage regulation. It is demonstrated

that this concept is a generic approach for the current sharing schemes. With this method,

it is concluded that the active current sharing control is superior to the passive droop

scheme not only in the steady-state accuracy, but also in the dynamic aspect. Therefore, if

a high performance is required for the current sharing during transient, active current

sharing control schemes are of their advantages.

Regarding the three active current sharing control schemes, a current sharing loop

gain, Tcs, can be defined for all of them. The function of this loop gain is to match the

output impedances inside its bandwidth, such that dynamic current sharing error can be

attenuated. Hence, it is preferred to have wide bandwidth of Tcs from the dynamic current

sharing point of view.

Therefore, it can be concluded that the current sharing loops have the same function

for all three active control schemes. Namely, impedances’ difference is reduced inside

current sharing loop’s bandwidth. However, these three control structures have different

ability of pushing Tcs’s bandwidth. Among them, outer-loop control has the strongest

limitation, while inner-loop and dual-loop structures provide the possibility of increasing

Tcs’s bandwidth beyond that of the voltage feedback loop.

In summary, different aspects of three active current sharing control schemes are

compared in Table 2.6.

103


Table 2.6. Comparison of three active current sharing structures

Outer-loop Dual-loop Inner-loop

Δz and Tcs Δz is attenuated by Tcs

Current sharing loop bandwidth Slow Flexible Fast

Interference between loops Minor Possible Minor

Noise immunity Moderate Poor Good

Applications Limited transients With stringent

transients

With stringent

transients

By comparing these methods, it is concluded that the inner loop shows its advantages

because

• The dynamic current sharing performance is improved inside the current

sharing loop bandwidth for all three control structures;

• The inner-loop and dual-loop schemes can achieve higher Tcs gain and

bandwidths than outer-loop structure;

• For dual-loop scheme, there is possibility of interaction between the voltage

regulation loop and the current sharing loop; therefore, it is recommended

to not design the current sharing loop to have similar bandwidth as that of

the voltage loop’s;

104


• The dynamic voltage regulation is impacted because of the current sharing

control for all three structures; however, with combination of the current

control loop, the inner-loop scheme has more flexibility to design a desired

voltage feedback loop and total output impedance of the system;

• With faster current sharing loop design, the dual loop’s noise immunity is

poor. However, combined with the current loop, the inner-loop control has

very good noise immunity because the current loop also has the function of

attenuating the noise;

• Therefore, inner-loop is a better choice considering both dynamic current

sharing and voltage regulation performance.

2.3 Experimental Implementations

The analyses in the previous section provide the basis of addressing the dynamic

current sharing issue, namely by looking at the output impedances one can determine what

bandwidth of Tcs is necessary to make required improvements. Next, the current sharing

control is implemented in the distributed power supply system shown in Figure 2.47 for

three paralleled front-end converters. In this distributed power system, three 200-kHz 5-

kW active-clamp isolated full-bridge boost converters (AFBCs) [48] are paralleled to

transfer 24~30V DC input voltage to 600-V DC output voltage [49]. The converter’s

operation modes have been documented in [49][50]. The picture of the hardware is shown

in Figure 2.48, where three front-end converters and five load converters [51] are all

included. The three front-end DC/DC converters are packaged in a metal box in the front,

and the five load converters on the back.

105


Front-endConverter

Front-endConverter

24V

HVCharger

600V

Front-endConverter

Front-endConverter

10kV5kW

5kW

5kW

Front-endConverter

Front-endConverter HV

ChargerHV

ChargerHV

ChargerHV

Charger

Front-endConverter

Front-endConverter

24V

HVCharger

600V

Front-endConverter

Front-endConverter

10kV5kW

5kW

5kW

Front-endConverter

Front-endConverter HV

ChargerHV

ChargerHV

ChargerHV

ChargerCS busCS bus

Figure 2.47. The DPS system for a high-voltage, pulsed-power charging application.

It is demonstrated that the dual-loop current sharing control shows more advantages

considering both the dynamic current sharing and the voltage regulation responses,

although all three approaches provide acceptable performance. However, in practice, it is

not always the higher Tcs bandwidth the better. With a faster current sharing loop, there are

high-frequency signals in the current sharing bus. Therefore, from the dynamic aspect,

low-pass filters are not preferred on the bus. On the other hand, this makes the current

sharing control more sensitive to noises, especially for a high-frequency high-current

system. The dual bus approach with dual-loop scheme can cause more troubles than a

single-wire connection.

Considering this practical issue, the outer-loop is selected for the design to minimize

the noise issue. Since the major function of Tcs is to minimize the difference among output

impedances, its bandwidth should be designed according to applications. For example, if it

is already clear that Zo1 and Zo2 are different only in the low frequency range, then Tcs does

not need a bandwidth higher than the mismatching region. In Figure 2.18, there is not too

much benefit to increase Tcs’s bandwidth beyond 10-kHz. Moreover, there could be some

compromise on the dynamic voltage regulation performance with fast Tcs. Of course, the

106


bandwidth of Tcs is also limited by its phase margin; sometimes it is not possible to design

very fast Tcs due to converter’s characteristics.

Figure 2.48. The hardware implementation of the whole charging system.

Vo

iin1iin2

2s/div

(100v/div)

(50A/div)iin3

Vo

iin1iin2

2s/div

(100v/div)

(50A/div)iin3

Figure 2.49. The experimental waveforms of the charging system.

107


Figure 2.49 shows the experimental waveforms of current sharing performance for

both steady-state and during load transients, where the input currents are measured for each

module. The design illustrated in Figure 2.18 is adopted here. The output voltage ripple

during light load in Figure 2.49 is due to the burst mode operation of the paralleling

system. Once power is required by the load side, the front-end converters exits the burst

mode operation and the feedback control can function properly. During this process, a

small spike may be seen because of operation mode transition. Nevertheless, this spike is

small enough to be ignored since it happens at light load. After that, the system behaves as

expected. It is observed that with proposed current sharing control loop design, the

dynamic current sharing is well achieved without overshoots.

2.4 Summary

In this chapter, detailed analyses are presented for the dynamic current sharing with

the output impedance approach. Different current sharing schemes are studied using this

method. It has been demonstrated that the essential role of the current sharing control is to

match the output impedances of paralleled modules.

Although the passive droop current sharing scheme is able to reduce certain

difference between the paralleled modules, the improvement is limited at the DC and low-

frequency region. Once the converter’s impedance is higher than the droop resistance at

certain frequency range, the performance is determined by the converter itself and the

droop method has no ability to attenuate the current sharing error at these frequencies.

Therefore, the droop current sharing approach’s performance is limited not only because of

the steady-state accuracy but also for during the transient.

108


The active current sharing control schemes greatly improve the matching of the

output impedances. It has been shown that for all three structures, the current sharing

loops, Tcs, are defined and their functions are similar: reduce mismatches among the

equivalent impedances of paralleled modules. With the voltage feedback loop, Tv, inside

the current sharing loop, the bandwidth of outer-loop structure’s Tcs is limited by Tv. While

the current sharing loop is located inside or parallel with the voltage loop for inner-loop

and dual-loop schemes, the limitation is eliminated. Moreover, inner-loop is better than

dual-loop in terms of possible loop interaction and noise immunity. Therefore, it is a better

choice considering both dynamic current sharing and voltage regulation performances.

All these analyses are based on the conventional output impedance concept, which is

the result of traditional average modeling technique. Therefore, the conclusions made in

this chapter are only applicable when the perturbation frequency is lower than half of the

switching frequency. However, there are some applications where transient’s frequency

can go much higher than half of the switching frequency. For those situations, models with

better high-frequency accuracy should be used to find out output impedances in the high-

frequency range. If so, the output impedance concept should still be useful in predicting

dynamic current sharing errors under high-frequency load transients. Chapter 3 will tackle

the high-frequency model, which can be accurate up to the switching frequency.

109

Chapter 3. Current Sharing Issue under

High-Frequency Dynamics

In Chapter 2, the conventional small-signal model based on the average technique

has been utilized to analyze the dynamic current sharing performance of paralleling

systems. However, these studies are only valid when the perturbation is low-frequency. In

another word, if the perturbation frequency is close or higher than half of the switching

frequency, then new research tool should be developed.

If we look at the VR applications, it is specified that the load transient frequency

varies in a very wide range from several kHz to several MHz, depending on the running

software. It is very likely that with certain kind of software, the load frequency is randomly

fixed at one value for a period of time. Therefore, it is required by Intel that VR vendors

should test their products for repetitive load transients up to 1MHz [41]. Figure 3.1 shows

one example of load profile for a multiphase VR system, which is determined by the power

required from the microprocessor.

Time

CPU Power

Time

CPU Power

Figure 3.1. Load profile for multiphase VR systems.

The equation of predicting the dynamic current sharing performance should not be

limited to whether the load is a single step or repetitive if the average model is valid,

110

Juanjuan Sun Chapter 3. Current Sharing Issue under High-Frequency Dynamics

21

12

21

21 )11(ˆˆˆ

cscs

cscs

cscscso

o

oo

ZZZZ

ZZZ

iii

+−

=−⋅=− . (3.1)

Therefore, it is valid to continue using the output impedance concept to study the dynamic

current sharing performance under repetitive load transients.

Zcs1 Zcso

Zcs2Zcs2

Figure 3.2. Output impedances for a 2-phase interleaved buck VR.

1 .103 1 .104 1 .105 1 .10665

60

55

50

1 .103 1 .104 1 .105 1 .10665

60

55

50Zcs1

Frequency fp(Hz)

Impe

danc

es (d

B)

Zcs210kHz

fs/2

?

Figure 3.3. Use output impedance to predict dynamic current sharing performance when the

perturbation frequency, fp, is lower than fs/2.

111


For a 1-MHz 2-phase interleaved buck VR in Figure 3.2, the output capacitor is

equally distributed in two paralleled phases. By doing so, the difference between inductor

currents is the same as that between output currents. To evaluate dynamic current sharing,

the output impedances for each phase, Zcs1 and Zcs2, are shown in Figure 3.3. The flat shape

of Zcs1 and Zcs2 is due to the adaptive voltage position (AVP) control [18]. Because of the

limitation of average model, Zcs1 and Zcs2 are only modeled up to half of the switching

frequency. Nevertheless, Figure 3.3 is still useful when the perturbation frequency is lower

than fs/2, for example, when fp=10kHz. With a 10-kHz repetitive load transient, the

corresponding time domain waveforms are illustrated in Figure 3.4.

cso

/ V

-15

-10

-5

0

5

10

15

io2

/ A

-5

0

5

10

15

20

io1

/ A

-5

0

5

10

15

20

ip /

A

-505

1015202530


2.65 2.7 2.75 2.8 2.85 2.9 2.95 3

Vo /

V

1.2

1.24

1.28

1.32

1.36

i o1 (A

)i o

(A)

i o2 (A

)i o1

–i o2

(A)

fp=10kHzio(10k)

io1(10k)

io2(10k)

io1(10k)-io2(10k)

v o(A

)

vo(10k)

10kHz

10kHz

10kHz

50us/div (ms)

10kHz

Figure 3.4. Time domain waveforms with 10-kHz repetitive load transient.

112


In Figure 3.4, the dynamic current sharing error at the perturbation frequency, fp, is

predicted by:

)()()()(

)()()(

21

1221

pcspcs

pcspcs

po

popo

fZfZfZfZ

fififi

+−

=−

. (3.2)

However, there is a phenomenon that cannot be explained when fp=990kHz, as

shown in Figure 3.5. According to the simulation waveforms in Figure 3.5(b), when fp is

close to the switching frequency, there are significant low-frequency oscillations in the

output currents. The oscillation frequency is determined by the beat-frequency, fbeat, which

is the difference between the per-phase switching frequency, fs, and the load transient

frequency, fp. It can also be observed that the beat-frequency oscillations in io1 and io2 are

out-of-phase, which leads to the cancellation of this frequency component in the output

voltage. Therefore, the beat-frequency oscillation can hardly be seen in the output voltage

waveform. Nevertheless, the large-amplitude low-frequency oscillations in the output

currents (also in the inductor currents) are already a severe issue which endangers the

reliability of the whole VR system. Therefore, this phenomenon needs to be studied and

understood clearly.

However, in the average model and the impedance concept, only the fp components

are included. In another word, there is no way to obtain information about the beat-

frequency components with conventional approach. Therefore, the output impedance

concept needs to be extended to include the beat-frequency components in order to study

dynamic current sharing performance in the whole frequency range. Meanwhile, since the

beat-frequency component could be unobservable in the output voltage, there are more

challenges to study the beat-frequency issue.

113


1 .103 1 .104 1 .105 1 .10665

60

55

50

1 .103 1 .104 1 .105 1 .10665

60

55

50Zcs1

Frequency fp(Hz)

Impe

danc

es (d

B)Zcs2

fs/2

?990kHz990kHz

(a) Output impedance is unknown when fp is close to fs.

cso

/ V

-40-30-20-10

010203040

io2

/ A

-10

0

10

20

30

io1

/ A

-10

0

10

20

30

ip /

A

-505

1015202530


2.65 2.7 2.75 2.8 2.85 2.9 2.95 3

Vo /

V

1.2

1.24

1.28

1.32

1.36

i o1 (A

)i o

(A)

i o2 (A

)i o1

–i o2

(A)

fp=990kHzio(990k)

io1(10k)

io2(10k)

io1(10k)-io2(10k)

v o(A

)

10kHz

10kHz

10kHz

vo(10k)≅0

50us/div (ms)

(b) Simulation waveforms when fp=990kHz.

Figure 3.5. Unexplainable phenomenon when fp is close to fs.

114


This issue can be classified as the high-frequency dynamic current sharing issue. It

has been found in most of the state-of-art industry products. One example has been given

in Figure 1.32. Figure 3.6 gives another example of test waveforms based on a 4-phase VR

board available in the market. The waveforms of two phases’ inductor currents, the output

voltage and load current are recorded. When there is a load transient at the repetitive

frequency, fp, of 10 kHz, the inductor currents are well shared in Figure 3.6(a). The square

waveform in the output voltage is caused by the adaptive voltage position (AVP) function

required by Intel. However, when fp is increased to 260 kHz, there is huge oscillation in the

inductor currents of 13 kHz, which is the beat frequency. With a load current amplitude of

2.5 A per phase, there exists a beat-frequency oscillation of 30 A in each phase, which is

more than ten times over the expected value. Meanwhile, the beat-frequency oscillation is

unobservable at the output voltage.

iL1

iL3

iL1

iL3

vovo

ioio

(a) fp=10kHz, 40us/div; from top to bottom: iL1:

10A/div, iL3: 10A/div, vo: 50mV/div, io: 50A/div.

(b) fp=260kHz. 40us/div; from top to bottom: iL1:

25A/div, iL3: 25A/div, vo: 50mV/div, io: 10A/div.

Figure 3.6. High-frequency dynamic current sharing issue for an industry demon-board,

tested on a 4-phase interleaving buck VR with fs=273kHz.

115


The undesired huge oscillations of the inductor currents impact the system reliability

due to extra losses on devices and the unexpected high flux densities in the magnetics. It

has been reported of fatal failure of the VRs due to this issue. Nevertheless, this

phenomenon is not well recognized and understood yet. Therefore, it is very important to

do a thorough study about it.

On the other hand, the major function of a VR system still is to keep the tight voltage

regulation under fast load transients [41][52]. Because of the cost related considerations, as

well as the limited space for VRs in the computer system, fewer output capacitors are

desired, which makes the design of the feedback control a very challenging task. Because

of that, as well as the benefit from ripple cancellation, the multi-phase interleaved

synchronous buck converter is widely adopted in VR applications [53][54][55]. It has been

shown that the feedback control loop’s bandwidth plays a very important role in the

transient response performances. With a higher bandwidth, fewer output capacitors are

needed to meet the specifications [18][56][57].

To understand the beat-frequency oscillation issue and its impact to system’s voltage

regulation performance, this chapter utilizes an untraditional high-frequency model. Based

on this model, the output impedance concept is expanded to extended describing functions

for dynamic current sharing study. Analyses based on this approach reveal design tradeoffs,

so that possible solutions can be proposed. The inner-loop and dual-loop structures are the

most popular current sharing solutions nowadays for multiphase VRs. Therefore, the high-

frequency dynamic current sharing analyses use peak-current mode control, which belongs

to the inner-loop category, as the study case.

116


3.1 Generation and Attenuation of the Beat-Frequency Oscillations

The fundamental reason of the beat-frequency oscillation’s generation is the

sampling characteristic of the PWM modulator [42][43]. As illustrated in Figure 3.7 with a

single-phase open-loop buck converter, supposing there is a perturbation source at

frequency fp in its control signal, vc. vc is then sampled by the ramp when going through the

PWM modulator. Due to the time-varying nature of a sampler, sideband components such

as fs+fp, fs-fp, 2fs+fp, 2fs-fp are generated at the output of the modulator, i.e., the duty cycle.

After being fed into the power stage and attenuated by its low-pass filter, the sideband

component fs-fp leads to beat-frequency oscillations in the output voltage and current.

Figure 3.7. A single-phase, 1MHz open-loop buck converter.

Nevertheless, the sidebands are usually ignored in the past. The reason is that for fp

lower than half of the switching frequency, the sidebands’ frequencies are relatively high,

so that they can be effectively attenuated by the low-pass filters in the power stage. Figure

3.8 illustrates an example of this situation: for a 1-MHz converter, when fp is 10 kHz, the

10-kHz component is the dominate one in vo’s waveform. Therefore, when fp<<fs/2, it is

safe to rely on the conventional average model, where the sidebands are neglected, to

predict the response of the output voltage.

117


pf− pf

cv~

pf− pf

cv~


4.6 4.7 4.8 4.9 5

VO /

V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4


4.6 4.7 4.8 4.9 5

Vc /

mV

890892894896898900902904906908910

100us/div

V o(V

)V c

(mV)

100us/div

fp=10kHz

fp=10kHz


dv~sfsf−


dv~sfsf−

ps ff −− ps ff +ps ff −ps ff +−

LPF

pf− pf

v o~

sfsf−

(a) Spectra of cv~ , dv~ , and ov~ . (b) Time domain waveforms.

Figure 3.8. The beat-frequency component can be ignored when fp<<fs.

However, if fp keeps increasing beyond fs/2, some of the sidebands such as fs-fp can

move into very low frequency range. As the result, the low-pass filter in the power stage

filters the fp component instead of the sideband component, fs-fp. Therefore, a large beat-

frequency oscillation can be observed on the output voltage waveform; while fp component

is nearly invisible in vo. Figure 3.9 shows the spectra and waveforms of one example when

fp is very high.

In summary, the nonlinear behavior of the pulse-width modulator generates a series

of sideband components with a single-frequency-component input. Meanwhile, all other

parts of the power stage can be treated as linear functions: they only react to a frequency

component at their inputs and then output the same frequency component with modified

magnitude and/or phase. By considering the nonlinear behavior of the PWM, it is then

possible to develop a high-frequency model with improved accuracy. This is exactly what

118


has been done in [43] when the multi-frequency model is proposed. Figure 3.10 shows the

concept of the multi-frequency model; where fs-fp component is generated from PWM and

LC filter only process different signals.

pf− pf

cv~

pf− pf

cv~


4.6 4.7 4.8 4.9 5

VO /

V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

V c(m

V)V o

(V)

100us/div

fp=990kHz


dv~sfsf−


LPF5us/div

fs-fp=10kHz

pf− pf

v o~

sfsf−

(a) Spectra of cv~ , dv~ , and ov~ . (b) Time domain waveforms.

Figure 3.9. The beat-frequency component becomes dominant when fp is close to fs.

Figure 3.10. The signal flow paths of different frequency components in Figure 3.7.

Besides the approach suggested in [43], there have been other researches about

extending the validity of small-signal model up to the switching frequency, such as the

119


sample-data model, harmonic balance model, etc [58][59]. The key issue of these works is

to found out the relationship between inputs and outputs of the PWM, which will be

discussed later in detail.

Tv

Figure 3.11. A single-phase, 1MHz closed-loop buck converter.

Tv

Figure 3.12. Feedback loops of Figure 3.11 considering the beat-frequency components.

For the single-phase open-loop buck VR being considered above, the attenuation for

high-frequency components mostly comes from the LC low-pass filter in the power stage.

However, for a closed-loop converter shown in Figure 3.11, there is additional attenuation

from the feedback loop gain, Tv. Following the multi-frequency model concept, a block

diagram incorporates both fp and fs-fp components are drawn in Figure 3.12. Since vo

120


includes fp and fs-fp components, they are both feedback through the controller Hv. Hv is

also a linear function, it reacts to fp and fs-fp components separately.


v o~

sfsf−(open-loop)

sfsf−vT1

1+

cfcf-


v o~

sfsf−(closed-loop)

1


4.6 4.7 4.8 4.9 5

VO /

V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

fp=990kHz

v c(m

V)

5us/div


Open-loop Vo

v o(V

)

4.6 4.7 4.8 4.9 5

VO /

V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

fs-fp=10kHz

fs-fp=10kHz 100us/div

Closed-loop Vo

v o(V

)

100us/div

(a) Spectra of with closed-loop. (b) Time domain waveforms. ov~

Figure 3.13. The beat-frequency component is effectively attenuated by feedback loop gain in a single-

phase, closed-loop buck converter when fp>fs/2.

Since the vo(fs-fp) component is also fed back, there exists the attenuation from the

voltage feedback loop for it. When fp>fs/2 and the fs-fp component in vo is not effectively

reduced by LC filter, the high gain of voltage feedback loop at low-frequency range helps

to attenuate the beat-frequency oscillation’s amplitude. Therefore, comparing with Figure

3.9 of the open-loop case, the vo waveform in Figure 3.13 has much smaller beat-frequency

121


oscillation magnitude. In the drawing of vo’s spectrum, the influence from the feedback

control loop gain is shown inside its bandwidth, fc.

Hence, with the voltage feedback loop’s attenuation, the beat-frequency oscillation is

not a big issue for a single-phase closed-loop buck VR. However, the situation is totally

different when multi-phase interleaved VR is concerned. Figure 3.14 shows a 2-phase

interleaved buck VR subjecting to high-frequency perturbations. Since the two paralleled

phases share the same control voltage, vc, their duty cycles both response to this

perturbation.

Figure 3.14. A 2-phase interleaved, 1MHz open-loop buck VR.

Based on Figure 3.14, Figure 3.15 illustrates the signal flow paths of fp and fs-fp

components. Apparently, both phases’ PWM generate sideband components and contribute

to the total output voltage. However, due to phase-shifting operation, the sampling

moments are different for two phases. This fact leads to very different outputs of two

PWMs although their input is the same.

122


Figure 3.15. Signal flow paths of Figure 3.14 considering the beat-frequency components.

pf− pf

cv~

pf− pf

cv~


d1v~sfsf−

ps f2f +− ps f2f −ps ff −ps ff +− time/mSecs 20? ecs/div

4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

vos

/ V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

fp=990kHz

5us/div

v c(m

V)v o

(V)

20us/div pf− pf

v o~

sfsf−


pf− pf

d2v~sfsf−

LPF1

LPF2

(a) Spectra of , cv~ 1~

dv , 2~

dv and . (b) Time domain waveforms. ov~

Figure 3.16. The fs-fp component is cancelled at vo in a 2-phase interleaved, open-loop buck VR.

123


Figure 3.16 illustrates the related spectra and simulation waveforms for this 2-phase

interleaved, open-loop buck VR. It can be found that although each phase observes fs-fp

components in their duty cycle, the output voltage doesn’t contain any beat-frequency

component at all. The reason can be explained from Figure 3.16(a): vd1(fs-fp) and vd2(fs-fp)

are out-of-phase by 180o with same magnitudes (assume perfect interleave and identical

phases), leading to cancellation of beat-frequency component in the summing point.

However, the fact that the beat-frequency oscillation is not observable at output

voltage doesn’t mean the system is not impacted by the beat-frequency components. Figure

3.17 illustrates the signal flow path of the first phase’s output current, io1. io1 contains both

fp and fs-fp components. Meanwhile, there is no cancellation effect for each phase’s current

since there is no summing effect for individual phases.

Figure 3.17. Signal flow path of io1.

Figure 3.18 shows a very severe beat-frequency oscillation in io1 when fp is close to fs.

Since there is no cancellation of fs-fp component in each phase’s output current, the only

factor that can reduce io1(fs-fp) is the low-pass filter of the power stage. Therefore, when fs-

124


fp is located at low-frequency range, the beat-frequency oscillation in io1 is huge comparing

with its DC values. Similar phenomenon also happens for io2. Thus, as shown in Figure

3.19, with a high-frequency perturbation in vc, the beat-frequency oscillation in output

currents could be a severe issue although it is unobservable at vo and io.

pf− pf

cv~


d1v~sfsf−


i o1

~

sfsf−

LPF1


4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

il1 /

A

-80

-60

-40

-20

0

20

40

60

80


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

fp=990kHz

v c(m

V)5us/div

(A)

i o1

10kHz

20us/div

(a) Spectra of cv~ , 1~

dv and 1~oi . (b) Time domain waveforms.

Figure 3.18. The fs-fp oscillations are severe at io1 in a 2-phase interleaved, open-loop buck VR.

Apparently, the beat-frequency oscillation issue raised in Figure 3.19 needs to be

addressed. Recalling that closed feedback loop helps to attenuate beat-frequency

components for single-phase converters, same attempt is made for 2-phase case. Figure

3.20 shows a 2-phase interleaved buck VR with average current mode control, while a

high-frequency perturbation source is inserted in the control voltage, vc. By sharing the

same control voltage, current mode control is able to realize current balance of inductor

currents. Figure 3.21 illustrates a simplified model with both fp and fs-fp components.

125



4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

vos

/ V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4


4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

A

-80

-60

-40

-20

0

20

40

60

80


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

fp=990kHz

5us/divv c

(mV)

v o(V

)

20us/div

vo(10kHz)=0

& i o

2(A

)i o1

10kHz 20us/div

Figure 3.19. The fs-fp oscillations are severe at io1 and io2 but unobservable in vo for a 2-phase

interleaved, open-loop buck VR.

Because of interleaving operation, there still exists cancellation effect of the fs-fp

component in vo, just as explained in Figure 3.16. Consequently, the feedback control of

vo(fs-fp) is not really effective. In another word, the Tv loop is only useful in attenuating fp

components. Meanwhile, the gain of Tv is negligible when fp is close to fs. Therefore, it

turns out for 2-phase interleaved buck VR, closed voltage feedback loop does not help to

reduce beat-frequency oscillations in output currents.

126


Ti1

Ti2

Tv

Figure 3.20. A 2-phase interleaved, 1MHz average-current-mode-controlled buck VR.

Ti1

Ti2

Tv

Figure 3.21. The simplified model for Figure 3.20.

127


Since there is no cancellation effect in io1(fs-fp) and io2(fs-fp), their magnitudes are

determined by the LC low-pass filter in the power stage, as well as any possible

attenuation from feedback loops. Since fs-fp is in the low-frequency range, the low-pass

filter can hardly reduce io1(fs-fp) and io2(fs-fp). On the other hand, because the current

feedback loops, Ti1 and Ti2, are separated in two phases, their gain should be helpful to

reduce io1(fs-fp) and io2(fs-fp). Figure 3.22 illustrates a simplified model for io1 and io2, where

the voltage feedback is not useful in reducing io1(fs-fp) and io2(fs-fp). Figure 3.23 uses

spectra and simulations to demonstrate dramatically reduced beat-frequency oscillations in

io1 with average-current-mode control. In Figure 3.23(a), the high gain of Ti1 in low-

frequency range significantly attenuates low-frequency fs-fp component. Therefore,

individual current feedback loops are helpful for the beat-frequency oscillation issue.

Ti1

Ti2

Tv

Figure 3.22. Simplified signal flow path of io1 and io2 in Figure 3.20 when fp fs.

128



4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

A

-80

-60

-40

-20

0

20

40

60

80


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

fp=990kHz

5us/div

20us/div

v c(m

V)


i o1

~

sfsf−

sfsf−i1T1

1+

cfcf-


sfsf−(closed-loop)i o1

~

(open-loop)

1

10kHzi o1&

i o2(A

)


4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

80

60

40

20

A

-80

0

-20

-40

-60

10kHz

i o1

20us/div

& i o

2(A)

Open loop

Average current mode control

(a) Spectra of 1~oi with average current mode control. (b) Simulation waveforms.

Figure 3.23. Attenuation of beat-frequency for multiphase, average-current-mode-controlled VR.

Nevertheless, peak-current mode control, as shown Figure 3.24, is more often used

for multiphase VRs due to easier implementation. However, peak-current-mode control

does not have high gain as average current mode control, which means that it may not be

able to provide enough attenuation for io1(fs-fp) and io2(fs-fp). An example is shown in

Figure 3.25, with limited gain of Ti1, the reduction of io1(fs-fp) is not as significant as that of

average current mode control. Therefore, the beat-frequency oscillation issue could still be

severe with peak-current mode control without proper design.

129


Ti1

Ti2

Tv

Figure 3.24. A 2-phase interleaved, 1MHz peak-current-mode-controlled buck VR with perturbations.


4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

A

-80

-60

-40

-20

0

20

40

60

80


4.975 4.98 4.985 4.99 4.995 5

Vc /

mV

890892894896898900902904906908910

fp=990kHz

5us/div

20us/div


i o1

~

sfsf−

v c(m

V)

sfsf−i1T1

1+

cfcf-



~

(open-loop)

1

10kHzi o1&

i o2(

A)


4.82 4.84 4.86 4.88 4.9 4.92 4.94 4.96 4.98 5

80

60

40

20

A

-80

0

-20

-40

-60

10kHz

i o1

20us/div

& i o

2(A)

Open loop

Peak current mode control

(a) Spectra 1~oi with peak current mode control. (b) Simulation waveforms.

130


Figure 3.25. Attenuation of beat-frequency for multiphase, peak-current-mode-controlled VR.

As aforementioned, although the beat-frequency oscillations with peak-current mode

control are reduced, their amplitudes are still too large to be accepted. Therefore, it is

essential to understand the reason behind this phenomenon and identify when the worse

case would happen. For this purpose, several spectra of io1 are drawn in Figure 3.26 as fp

moves from low frequency to switching frequency. In the drawings of Figure 3.26, it is

assumed that perturbations are added at the control voltage, vc, like what has been shown in

Figure 3.24. In a real circuit, however, perturbations are normally caused by load

transients. Nevertheless, it is still valid to represent the load perturbations by the control

voltage’s perturbation equivalently.

sfsf−i1T1

1+

cfcf-


~

cv~

i1T11

+


cv~

p1s ff −− p1s ff +p1s ff −p1s ff +− p1f− p1f

d1v~sfsf−

sfsf−

LPF1

(open-loop)

cfcf-

i1T1LPF1

+

sfsf−

p1f− p1f

p1f− p1f

p1f− p1f

i o1

~p2s ff −− p2s ff +p2s ff −p2s ff +− p2f− p2f

d1v~sfsf−

sfsf−

LPF1

(open-loop)

cfcf-

sfsf−

i o1

~

i o1

~

p2f− p2f

p2f− p2f

p2f− p2f

p2s ff −− p2s ff +p2s ff −p2s ff +−


1



i1T1LPF1

+

sfsf−cfcf-

1

(a) fp1<<fs/2. (b) fp2<fs/2.

131


i1T11

+


cv~

i1T11

+


cv~

p3s ff +−2 p3s f2f −p3s ff −p3s ff +−p3f− p3f

d1v~sfsf−

sfsf−

LPF1

(open-loop)

cfcf-

sfsf−

i1T1LPF1

+

i o1

~

i o1

~

p3f− p3f

p4s ff +−2 p4s f2f −p4s ff −p4s ff +−p4f− p4f

d1v~sfsf−

sfsf−

LPF1

(open-loop)

cfcf-

sfsf−

p3s ff +−2 p3s f2f −p3s ff −p3s ff +−


p3f− p3f

p3f− p3f

sfsf−cfcf-

1

i1T1LPF1

+

i o1

~

i o1

~

p4f− p4f

p4f− p4f

p4f− p4f



sfsf−cfcf-

1

(c) fp3>fs/2. (d) fp4 fs.

Figure 3.26. Response of io1 as fp changes from low to high frequency with peak-current mode control.

In Figure 3.26(a), fp1 locates at low frequency so that the fs-fp1 component in io1 gets

adequate attenuation from power stage’s low pass filter. Thus, the beat-frequency

oscillation in io1 can be ignored when fp=fp1. As fp moves to fp2, the fs-fp2 component is not

negligible although it is still small compared with fp2 component. If we further increases fp

to fp3, the fs-fp3 component becomes bigger than fp3 component. Finally, as fp approaches fs

as in Figure 3.26(d), the beat-frequency oscillation reaches its maximum value. Here, due

to the limited gain of Ti1 with peak-current mode control, there is a flat area of io1(fs-fp)’s

magnitude. Namely, after fp reaches a certain value, the magnitude of io1(fs-fp) does not

keep increasing as fp increases. It needs to be mentioned that Figure 3.26 is only a

132


conceptual drawing for the purpose of estimating the magnitude of beat-frequency

oscillation in io1; it is can not be used for fp component, because the fp component in io1 is

influenced by both current and voltage feedback loops while only the current loop has been

considered in Figure 3.26.

Moreover, circuit simulations have been used to collect data. When a sinusoidal

current whose frequency is denoted as fp is applied at the load of Figure 3.27, the time

domain responses of a 2-phase interleaved buck VR are recorded to extract the fs-fp

component of io1. The magnitude of output currents change is 0~20A, and the switching

frequencies are 1 MHz per phase.

1/fp

0A

20A

Figure 3.27. Simulation circuit for a 2-phase interleaving peak-current-mode controlled buck VR.

It is observed from simulation results that the amplitude of the beat-frequency

oscillation is changing with different load transient frequency, fp. As fp increases, the beat-

frequency decreases, and the oscillation magnitude keeps increase until it reaches certain

level. The trends of 2-phase interleaved VRs with peak-current mode control are obtained

133


in Figure 3.28 by repeating the simulation for a series fp (shown in the dots). The gain of an

extended describing function, io1(fs-fp)/io(fp), is then plotted by connecting these points.

This extended describing function indicates how much beat-frequency current sharing error

in the output current is caused by the perturbation at fp on the load current.

-40

-20

0

20

1000 10000 100000 1000000fbeat

iL1*

/io|i o

1(f s

-f p)/i

o(f p

)| (d

B)

fs-fp (Hz)

fp (Hz) 900k 0700k

1k 10k 100k 1M300k30k3k

970k990k997k999k

fc_Ti1 fp1

fp2

fp3fp4

Figure 3.28. The simulated response of io1(fs-fp)/io(fp) for a 2-phase interleaved, peak-current-mode-

controlled buck VR.

The simulation result in Figure 3.28 can be related to Figure 3.26 by denoting some

of the data points to fp1 to fp4. The bandwidth of Ti1 is also marked in Figure 3.28. In order

to study the dynamic current sharing performance under high-frequency perturbations, the

traditional output impedance method needs to be extended so that beat-frequency dynamic

current sharing issue can also be addressed. Meanwhile, it is necessary to develop a tool

which is able to do high-frequency modeling. For this purpose, the multi-frequency model

for voltage-mode-controlled VRs proposed in [43] is utilized in this work. However, only

134


the multi-frequency model for voltage mode control has been developed in [43]. Therefore,

this modeling technique needs to be extended to current-mode-controlled VRs. In the next

section, the multi-frequency model for peak-current mode controlled single phase VR will

be derived. And the section following that deals with multiphase VRs.

3.2 Multi-Frequency Model for Current Mode Controlled Converters

There have been researches about extending the validity of small-signal model up to

the switching frequency, such as the sample-data model, harmonic balance model, etc

[43][58][59]. By taking into consideration of the sideband components’ effect through the

feedback control loops, the concept of the multi-frequency model was proposed in [43].

After doing so, the accuracy of high-frequency modeling for the single-loop voltage-mode

control is improved, so that additional phase delay can be explained [43].

The basic idea of the multi-frequency model can be described in this way: in a buck

converter with constant input voltage, the only nonlinear function is the PWM comparator.

Through the frequency modulation, new frequency components are generated from the

PWM and propagated inside the network. If extended describing functions considering the

sideband components can be derived for the PWM, then the high-frequency performance

can be modeled by combining them with the transfer functions of the linear parts for the

rest of the converter.

Therefore, it is essential to get the describing functions from the PWM’s inputs to its

outputs. In the PWM comparator of a buck converter with voltage mode control, its input

of the control voltage, vc, and output of the duty cycle, d, both include multiple frequency

components. The describing function of the PWM comparator for the same frequency

135


input and output has been derived using Fourier analysis [60]. On the other hand, [43] has

derived the relationship between different frequencies and plug the resulted PWM model

into the multi-frequency model. It has been found that through the feedback path of Hv, the

perturbation frequency, fp, is closely coupled with the beat-frequency, fs-fp. Therefore, it is

impossible to only consider one of them for an accurate high-frequency model [43].

This multi-frequency modeling concept can be adopted and expanded to current-

mode-controlled converters. However, the special sample-and-hold feature of current mode

control makes its PWM function much more difficult to be modeled. Another difference of

this work and [43] is that this research is more focused on the sideband components

themselves instead of their impact on the loop gains. Figure 3.29 shows a single-phase,

peak-current-mode-controlled buck VR with a perturbation source added in the control

voltage. Figure 3.30 shows the multi-frequency model of this converter. The major

difficulty comes from the modeling of the PWM.

Figure 3.29. A single-phase, peak-current-mode-controlled buck VR.

When a perturbation signal vp(fp) is inserted to the control voltage vc, the PWM

modulator generates duty cycle signal with two frequency components: fp and fs-fp. Both of

them are fed back through the current loop and voltage loop and injected into the PWM

modulator again. Thus, through the feed back mechanism, the fp components and fs-fp

136


components are cross-coupled. Therefore, to obtain the multi-frequency model and then

find out the beat-frequency component in iL and io, the unknown PWM box in Figure 3.30

need to be solved.

Figure 3.30. Multi-frequency model for a single-phase peak-current-mode controlled buck converter.

It should be noted that the fp-fs and fs-fp components are actually different

representations of the same time-domain waveform. Hence, they are equivalent in

representing the magnitude of beat-frequency oscillations. Because of this, it is not

necessary to distinguish them when magnitude is the major concern.

As shown in Figure 3.31, the duty cycle signal is generated by comparing vc to the

combination of sensed inductor current and the external ramp. With a small perturbation of

angular frequency ωp on vc,

)sin()(ˆ)( θωε +⋅+=+= tVtvVtv pcccc , (3.3)

137


the small-signal perturbation on the duty cycle, , is a series of narrow pulses. This

function is approximated very well by a string of delta functions whose areas is identical

with that of the pulse functions

)(ˆ td

[42],

])([ˆ)(ˆss

kk TDktTdtd +−⋅≈ ∑

∞

−∞=

δ . (3.4)

where is the width of the small-signal response of the duty cycle in the k-th switching

cycle, and D is the steady-state duty cycle. T

kd

s is the switching period, Ts=1/fs.

In order to solve , the discrete-time approach in kd [47] is utilized here. The small-

signal restriction is implied when discrete values are extracted from a continuous signal,

because it is assumed that the sampling action always happens at a fixed moment, namely

(k+D)Ts. It is then obtained that

''ˆ'ˆ)1(ˆ)(ˆˆkkLsmcmk ddkiRFkvFd −=−−= . (3.5)

In (3.5), is the discrete value of control voltage’s perturbation at the k-th

switching cycle, represents the discrete value of inductor current perturbation in

the (k-1)-th cycle, R

)(ˆ kvc

)1(ˆ −kiL

s is the current sensing gain, and Fm is the modulator gain:

senm TSS

F)(

1+

= . (3.6)

where, Sn and Se are the on-time slopes of the current-sensing waveform and the external

ramp, respectively. Therefore, combination of equation (3.4) and (3.5) yields:

138


)(''ˆ)('ˆ

])([''ˆ])(['ˆ)(ˆ

tdtd

TDktTdTDktTdtd ssk

kssk

k

−=

+−⋅⋅−+−⋅⋅≈ ∑∑∞

−∞=

∞

−∞=

δδ. (3.7)

PWM

vc

iL

Se

+

_

_

d

Sn

(a) Pulse-width modulator of peak-current mode control.

V

1.41.6

3.43.2

1.82

2.22.42.62.8

3

time/mSecs 1� ecs/div

5.018 5.019 5.02 5.021 5.022 5.023 5.024 5.025 5.026 5.02

d_ha

t / V

-6

-4

-2

0

2

4

)(tvc

eLs stiR +)(

)(ˆ tdkd

kTs

(b) Generation of the duty cycle perturbation.

Figure 3.31. PWM function of the peak-current mode control.

The first term of (3.7) shows the relationship between the duty and control voltage,

which is relatively straightforward. On the other hand, since the current feedback loop has

to be closed to allow the modulator to work appropriately, the second term requires more

effort to be correctly modeled.

139


For the first part in (3.7), Figure 3.32 gives a simple representation of the influence

from on . is the corresponding part of in . In )(ˆ tvc )('ˆ td )('ˆ td 'kd )(ˆ td Figure 3.32,

is the sampled waveform of , )(*ˆ tvc )(ˆ tvc

])([)(ˆ)(*ˆ sk

cc TDktkvtv +−⋅≈ ∑∞

−∞=

δ . (3.8)

])([)(ˆ)'*(ˆs

kcm TDktkvFtd +−⋅≈ ∑

∞

−∞=

δ , (3.9)

])([)(ˆ)('ˆss

kcm TDktTkvFtd +−⋅⋅≈ ∑

∞

−∞=

δ . (3.10)

Where,

])(sin[)(ˆ θωε ++⋅≈ spc TDkkv . (3.11)

'*(t)d(t)*vcˆ(t)vcˆ (t)'dFm Ts

sampling

Figure 3.32. The PWM function: from the control voltage to duty cycle.

The Fourier analysis is then performed on (3.10), which leads to the following results

if ωp≠N*πfs:

...}]2)sin[(

]2)sin[(){sin()('ˆ

+−+++

++−++≈

πθωω

πθωωθωε

Dt

DttFtd

sp

sppm . (3.12)

Therefore, considering only ωp and ωp-ωs components, the frequency domain

relationship between and ' is obtained as show in cv d Figure 3.33. This result is same as

that for voltage mode control in [43].

140


FmejD2π

Fm)(ωv pc )(ωd' p

)ω-(ωd' sp

Figure 3.33. Frequency domain relationship between the control voltage and the duty cycle.

Now the second term in (3.7) needs to be solved. Recall from [47], a z-domain

equation was utilized to derive the s-domain model:

αα

++==

zz

RzvziH

sc

L )1(1)(ˆ)(ˆ

. (3.13)

where, α=(Sf-Se)/(Sn+Se), and Sf is the off-time slope of the sensed inductor current. The

frequency-domain description of (3.13) is obtained by replacing z with . Including the

sample-and-hold effects,

sTje ω

Figure 3.34 illustrates the process of reacting to perturbations

on v

Li

c in the frequency domain. Where, the function Gh(jω) is a zero-order holder:

)1(1)( sTjh e

jjG ω

ωω −−= . (3.14)

)H(e spTjω)(v pc ω )(*i pL ω )(i pL ω

sampling)(jωG ph

]H[e ssp )Tω-j(ω)-(*i spL ωω )-(i spL ωω

)]ω-[j(ωG sph

Figure 3.34. Frequency-domain relationship between and . Li cv

Thus, the ωp and ωp-ωs components of can both be calculated from )(ˆ tiL Figure 3.34

[61]. On the other hand, after applying the methodology in [47] and the result in (3.12),

141


Figure 3.35 needs to be equivalent to Figure 3.34. The Fi(jω) function in Figure 3.35 is the

duty-cycle-to-inductor-current transfer function. He(jω) and He’(jω) are the unknowns in

the frequency domain model, whose appearance is the consequence of the sample-and-hold

effect in the current feedback loop.

FmejD2π

)(ωv pc )(i pL ω)d( pω

)-(i spL ωω)-d( sp ωω

Figure 3.35. Frequency-domain model for peak-current-mode control with the outer voltage loop open.

Then by equating two expressions derived separately from Figure 3.34 and Figure

3.35, the unknowns can be solved. For example, for the ωp component, the equation is:

( )( )

( ) ( ) ( )( ) ( )pespim

pim

s

phTjω

pc

pL

jωHRjωFFjωFF

TjωGeH

ωvωi sp

+=

×=

1ˆ

ˆ. (3.15)

The outcome of (3.15) is:

1)(

−= Tj

sppe pe

TjjH ω

ωω . (3.16)

This, with no surprise, is exactly the same result as reported in [47]. As for the ωp-ωs

components, a similar derivation yields:

142


( )[ ] ( )( ) 1

'−

⋅−=− − ssp Tj

sspspe e

TjjH ωω

ωωωω . (3.17)

Comparison between (3.16) and (3.17) leads to the conclusion that He and He’ are

actually the same function: He’(jω)=He(jω). Therefore, the modulation function of a single-

phase peak-current mode controlled converter is expressed by the following describing

functions under the input perturbation of )(ˆ pcv ω :

)(ˆ)()(ˆˆpLspempcmp iRjHFvFd ωωωω −=)( , (3.18)

)(ˆ)]([)(ˆˆ 2spLsspempc

jDmsp iRjHFveFd ωωωωωωω π −−−=− )( . (3.19)

Following the same process, the duty cycle output with input perturbation

)(ˆ spcv ωω − is derived as:

)(ˆ)()(ˆˆ 2pLspemspc

jDmp iRjHFveFd ωωωωω π −−= −)( , (3.20)

)(ˆ)]([)(ˆˆspLsspemspcmsp iRjHFvFd ωωωωωωωω −−−−=− )( . (3.21)

Thus the complete model for PWM comparator is obtained by combining (3.18),

(3.19), (3.20) and (3.21), which leads to:

)(ˆ)()(ˆ)(ˆˆ 2pLspemspc

jDmpcmp iRjHFveFvFd ωωωωωω π −−+= −)( , (3.22)

)(ˆ)]([

)(ˆ)(ˆˆ 2

spLsspem

pcjD

mspcmsp

iRjHF

veFvFd

ωωωω

ωωωωω π

−−−

+−=− )(. (3.23)

Finally, including ωp and ωp-ωs components, the small-signal model of the PWM

function in a peak-current mode controlled converter is obtained in Figure 3.36.

143


In the past, only the model for ωp component has been developed, that is the first two

blocks in Figure 3.36. However, one of the sideband components and its cross-coupling

effect with ωp component are also included in this work. This improvement not only

enables the prediction of beat-frequency oscillation on inductor current and output voltage,

but also increases the high-frequency accuracy of conventional model. The reason, as

mentioned before, is that for a closed-loop system, the sidebands have influences on ωp

components through the feedback mechanism.

)( pLsiR ω

)( pcv ω )( pd ω

)( spLsiR ωω −

)( spcv ωω −

)( spd ωω −

Figure 3.36. The small-signal model of peak-current mode controlled PWM comparator.

Given that the small-signal model of the modulator has already been developed in

Figure 3.36, Figure 3.37 illustrates the completed small-signal model for a single-phase,

peak-current-mode controlled buck VR, supposing there is a perturbation of ωp on load

current. Since the ωs-ωp component and the ωp-ωs component are only different

expressions for the same sinusoidal waveform, they have the same magnitude but different

phases. Because the magnitude is our major concern for the beat-frequency analysis, it is

144


not necessary to differentiate them. It is assumed here that the feed-forward loops in the

peak-current mode control have insignificant influence, and the AVP loop is not included

for simplicity.

(a) The circuit needs to be modeled.

)( pcv ω

)( ppi ω

)( pov ω

)( pLi ω

)( pd ω

)( spcv ωω −

)( spov ωω −

)( spLi ωω −

)( spd ωω −

vovc

(b) The proposed multi-frequency model.

Figure 3.37. Complete small-signal model of a single-phase, peak-current-mode controlled buck

converter, with high-frequency load current perturbation.

145


Gvd(ω) and Gid(ω) are the control-to-output-voltage and the control-to-inductor-

current transfer functions of the power stage, respectively. Gii(ω) and ZOL(ω) represent the

power-stage load-to-inductor-current and open-loop output-impedance function. The cross

coupling between ωp and ωs-ωp components can be clearly observed from Figure 3.37.

Moreover, there are two feedback loops, Tv(ωp-ωs) and Ti(ωp-ωs), to attenuate the beat-

frequency component in the inductor current, iL(ωp-ωs). These two feedback loops are

defined as:

)()()( spvspvdmspv HGFT ωωωωωω −−=− , (3.24)

)()()( spespidsmspi HGRFT ωωωωωω −−=− . (3.25)

With the proposed multi-frequency model in Figure 3.37, two advantages can be

achieved over the conventional average model. First, the output impedance which is

accurate up to the switching frequency can be obtained. This gives us the opportunity to

evaluate the system’s voltage and current response under perturbations faster than half of

the switching frequency. Second, since the beat-frequency components are visible in this

model, it is then possible to predict the beat-frequency oscillation’s magnitude in the

inductor current as the response of load transients. In the next section, these two aspects

will be elaborated.

Based on this model, beat-frequency components are predictable. For example, the

beat-frequency component in inductor current as the response of load current perturbation

can also be measured by an extended describing function. It can be derived that the

describing function between )( spLi ωω − and )( poi ω is:

146


( )( )

( ) ( )( ) ( ) ( )pCL

spvspi

spidjD

mpv

po

spL ZTT

GeFHi

iω

ωωωωωωω

ωωω π

×−+−+−

=−

1

2

. (3.26)

Where, ZCL(ωp) is the closed-loop output impedance:

( )( ) ( )

( )( ) ( )

( )( )

( )ps

p

pid

piipvd

pi

pipOL

pCL

TT

GGG

TT

ZZ

ωωω

ωωω

ωω

ωω

−++

⋅+

+=

2

2

11

1, (3.27)

)()()( pepidsmpi HGRFT ωωω = , (3.28)

)()()( pvpvdmpv HGFT ωωω = , (3.29)

)(1)(

)(2pi

pvp T

TT

ωω

ω+

= . (3.30)

If we denote:

( ) ( ) ( ) ( )pCLspidjD

mpvpsp ZGeFHG ωωωωωωω π −=− 2, , (3.31)

then,

)(),(

)()(

sp

psp

po

spL

TωG

ωii

ωωωωωω

−+−

=−

11. (3.32)

The loop gain T1(ωp-ωs) is defined as

)()()( spispvsp TTT ωωωωωω −+−=−1 . (3.33)

Then it can be found that as ωp approaches ωs, the gain of T1(ωp-ωs) increases and the

magnitude of iL(ωp-ωs) would decrease. Therefore, same trend is predicted from the model

as we have plotted in Figure 3.13, where the beat-frequency is denoted as

147


psbeat ωωω -= , (3.34)

Figure 3.38 plots the gain curves of (3.26) and (3.33). It can be seen that while inside

the bandwidth of T1, which is denoted as fc_T1 in the picture, iL(fbeat) is greatly reduced from

G(fbeat, fp). Thus, the effective attenuation from T1(fbeat) makes the beat-frequency issue of

the single-phase case not that severe. Meanwhile, if we compare this model prediction with

the simulation results, which is redrawn here in brown dots, it can be observed that the

calculation matches with simulation very well, which verifies the proposed model in

Figure 3.37.

1 .103 1 .104 1 .105 1 .10620

0

20

40

60

80

1 .103 1 .104 1 .105 1 .10660

40

20

0

20

40

Gai

n (d

B)

Mag

nitu

de (d

B)

Frequency fbeat=fs-fp (Hz)

T1(fbeat) fsfs

fc_T1fc_T1

),( pbeat ffG

)(fi)(fi

po

beatL

Dots: Simulation results

Figure 3.38. Prediction and attenuation of the beat-frequency component in a 1MHz single-phase

peak-current-mode-controlled buck VR.

148


This section developed the multi-frequency model for a single-phase peak-current

mode controlled buck VR, and use it to predict the beat-frequency component in the phase

current. Simulation was used to verify the analyses. It is also revealed that the feedback

loop gain T1(fbeat) plays a very important role in attenuating the beat-frequency oscillations

inside the system. In the next section, the study is extended to multi-phase interleaved

VRs.

3.3 Multi-Frequency Model for Multiphase Interleaved Buck VRs

With the PWM model for single-phase, peak-current mode control derived, it is then

not difficult to extend it to the multiphase converters. As an example, a 2-phase interleaved

buck VR with peak-current mode control is shown in Figure 3.39. The two paralleled

phases are sharing the same voltage feedback control loop, therefore same vc.

The first step is still to find the PWM function for different phases. One of the major

differences in the multiphase VR is the existence of the phase-shifting operation.

Therefore, for the second phase, the sampling instant is no longer happening at (K+D)Ts.

Instead, it is happening at (K+D+1/2)Ts, since there is 180o degree phase shift between two

paralleled channels. Hence, the duty cycle of the second phase is determined by:

])21([ˆ)(ˆ

22 ssk

k TDktTdtd ++−⋅≈ ∑∞

−∞=

δ . (3.35)

On the other hand, is also different from , since different vkd2ˆ

kd1ˆ c value will be seen

by different phases at different moments. Considering these possibilities, the PWM

function is derived with the same approach described in section 3.2 for both phases, as

shown in Figure 3.40.

149


Figure 3.39. A 2-phase interleaved buck VR with peak-current mode control.

)(1 pLsiR ω

)( pcv ω

)(2 pLsiR ω

)( pcv ω )(2 pd ω)(1 pd ω

)(1 spLsiR ωω −

)( spcv ωω −

)(1 spd ωω −

)(2 spLsiR ωω −

)( spcv ωω −)(2 spd ωω −

(a) PWM function for the first phase. (b) PWM function for the second phase.

Figure 3.40. The small-signal models of PWM comparators for a 2-phase interleaved buck VR using

peak-current mode control.

After applying the PWM models in Figure 3.40, the completed multi-frequency

model for the 2-phase interleaved buck VR with peak-current-mode control is obtained in

Figure 3.41. Perturbation is added at the load side as ip(fp). There exist several feedback

150


loops for both fp and fbeat components. Nevertheless, this complicated model is capable of

solving any term that is of our interest, such as iL1(fbeat) or io1(fbeat).

Figure 3.41. The multi-frequency model of Figure 3.39.

151


As aforementioned, there exist 180o phase-shift between PWM of the first and the

second phases. Because of this, it is possible to make some simplification on the multi-

frequency model of the whole system. The ωbeat components of Figure 3.41 are extracted

and shown in Figure 3.42, where the detailed block diagrams of each phase are simplified

by a block. Both phases contribute to the output voltage, therefore,

)()()( 21 beatobeatobeato vvv ωωω += . (3.36)

-Hv( beat)

)( beatov ω

)(1 beatov ω

)(2 beatov ω

)(1 beatoi ωPWM

)( pcv ω

)(2 beatoi ω)( beatcv ω

Figure 3.42. ωbeat component part of a 2-phase interleaved buck VR.

If the two paralleled phases are perfectly symmetric, namely they have identical

components and exactly 180o phase difference, then it can be concluded that vo1(ωbeat)=-

vo2(ωbeat). Although this perfect condition cannot be easily achieved in reality, it is still safe

to consider

)()( 21 beatobeato vv ωω −≈ , (3.37)

)()( 21 beatobeato ii ωω −≈ , (3.38)

152


since the asymmetry is normally minor. Therefore,

0)( ≈beatov ω , (3.39)

0)( ≈beatcv ω , (3.40)

0)( ≈beatoi ω . (3.41)


2.65 2.7 2.75 2.8 2.85 2.9 2.95 30.9

1

1.1

1.2

1.3

1.4

1.5

v o1(

v)

ωbeatωbeat

Time (ms) time/mSecs 50� ecs/div

2.65 2.7 2.75 2.8 2.85 2.9 2.95 3VO

/ V

0.9

1

1.1

1.2

1.3

1.4

1.5

v o2(

v)

ωbeatωbeat

Time (ms)

(a) vo1 waveform. (b) vo2 waveform.


2.65 2.7 2.75 2.8 2.85 2.9 2.95 3

VO /

V

0.9

1

1.1

1.2

1.3

1.4

1.5

v o(v

)

Time (ms)

(c) vo waveform.

Figure 3.43. Waveforms of )(1 beatov ω , )(2 beatov ω and )( beatov ω with symmetric phases.

Figure 3.43 shows the waveform of vo1(ωbeat), vo2(ωbeat) and vo(ωbeat) if the paralleling

phases are considered to be perfectly symmetric. Due to different PWM functions of two

phases, the ωbeat component in is gone since vov o1(ωbeat) and vo2(ωbeat) have same

magnitude and they are out-of-phase. Apparently, this means there is no )( beatcv ω either,

and the feedback loop Tv(ωbeat) is disabled. However, for each phase’s inductor and output

153


currents, there are no such cancellations of ωbeat components, since the current loops of two

phases are totally separated.

Therefore, compared with the single-phase case, two-phase buck converter has no

attenuation from Tv(ωbeat) for beat-frequency components in the output currents, and hence

much severer beat-frequency oscillation problem. Furthermore, a more general conclusion

can be made that the multiphase case is worse than single-phase from the beat-frequency

oscillation point of view, since the cancellation of vo(ωbeat) is always true no matter how

many phases there are.

Usually perfect symmetric phases are not possible in reality, resulting in some

amount of ωbeat component in vo. However, this component is very small since the

mismatch among phases is designed to be insignificant and the interleaving operation

implemented inside control ICs is almost perfect. Therefore, it is safe to ignore vo(ωbeat) in

the model, which greatly simplifies the analyses.

Under the condition that 0)( ≈beatcv ω , the PWM function of two phases can be

significantly simplified as:

)()()( 11 pLspempcmp iRHFvFd ωωωω −=)( , (3.42)

)()()( 12

1 beatLsbeatempcjD

mbeat iRHFveFd ωωωω π −=)( . (3.43)

)()()( 22 pLspempcmp iRHFvFd ωωωω −=)( , (3.44)

)()()( 22

2 beatLsbeatempcjD

mbeat iRHFveFd ωωωω π −−=)( . (3.45)

154


Figure 3.44. Simplified multi-frequency model for 2-phase buck VR with peak-current mode control.

Figure 3.44 shows a simplified model of a 2-phase interleaved buck VR. Since

vo(ωbeat)≅0, the output capacitor does not influence the beat-frequency components of

output and inductor currents. Therefore, the control-to-inductor-current transfer functions

at ωbeat are changed to:

155


)(/)(' 11 beatLinbeatid ωZVωG = , (3.46)

)(/)(' 22 beatLinbeatid ωZVωG = . (3.47)

Where ZL1(ω) and ZL2(ω) are the inductors’ impedances of two phases.

Nevertheless, to calculate the beat-frequency current information directly based on

Figure 3.44 is complicated and not straightforward. It is desired to utilize the terminal

characteristics such as the output impedances. However, the traditional output impedances

contain only the information of fp components. Therefore, it is necessary to extend the

concept to include fbeat information.

Figure 3.45 illustrates the terminal characteristics for a 2-phase buck considering the

beat-frequency information. When a load transient at fp is applied to the system, there exist

both fp and fbeat components in vo, io1 and io2. Therefore, to represent the complete

performance of one phase, four different “impedances” can be defined for the first phase.

They are:

)()(

po

popcs i

vZ

ωω

ω1

1 )( −= , (3.48)

)()(

beato

po

iv

Xωω

11 −= , (3.49)

)()(

po

beato

ivY

ωω

11 −= , (3.50)

)()(

beato

beatobeatcs i

vZωωω

11 )( −=

, (3.51)

156


Among them, Zcs1 is the conventional output impedance, which expresses the relationship

between output voltage and current in the same frequency. While, X1 and Y1 are in the form

of extended describing functions; they are used to show the relationship between voltage

and current in different frequencies. Figure 3.45(b) illustrates those four impedances.

io2(fbeat)

io2(fp)

io1(fbeat)

io1(fp)

(a) Two-phase buck with output perturbation.

Zcs1(fp) Zcs2(fp)

Y1

io1(fp)

io1(fp)

Y2

io2(fp)

io2(fp)

Zcs1(fbeat)

X1

io1(fbeat)

io1(fbeat)

Zcs2(fbeat)

X2

io2(fbeat)

io2(fbeat)

(b) Terminal characteristics of phase #1. (c) Terminal characteristics of phase #2.

Figure 3.45. Terminal characteristics for a 2-phase buck considering beat-frequency components.

157


Similarly, a set of impedances are defined for the second phase as in Figure 3.45(c):

)()(

po

popcs i

vZ

ωω

ω2

2 )( −= , (3.52)

)()(

beato

po

iv

Xωω

22 −= , (3.53)

)()(

po

beato

ivY

ωω

22 −= , (3.54)

)()(

beato

beatobeatcs i

vZωωω

22 )( −= , (3.55)

The final objective is to find out the dynamic current sharing performance of this

system. Namely, it is desired to obtain io1(ωp)-io2(ωp) and io1(ωbeat)-io2(ωbeat). In order to get

io1(ωp)-io2(ωp), we can either use Zcs1(ωp) and Zcs2(ωp), or Y1 and Y2. It is not necessary to

use all of them. Same situation can be found when io1(ωbeat)-io2(ωbeat) is the concern: either

X1 and X2, or Zcs1(ωp) and Zcs2(ωp) would be enough for our purpose. Recall from Figure

3.43, the ωbeat component in vo is zero with symmetric phases. Therefore, it is more

reasonable to use impedances that do not contain vo(ωbeat). Therefore, it is obtained that for

ωp component:

)()()()(

)(1

)(1)(

)()(

)()(

)()(

)()()(

12

12

21

2121

pcspcs

pcspcs

pcspcspcso

po

po

po

po

po

po

po

popo

ZZZZ

ZZZ

vi

vi

iv

iii

ωωωω

ωωω

ωω

ωω

ωω

ωωω

+−

=

⎥⎥⎦

⎤

⎢⎢⎣

⎡−⋅=

⎥⎥⎦

⎤

⎢⎢⎣

⎡−⋅=

−

. (3.56)

And the dynamic current sharing error at the beat-frequency, ωbeat, is:

158


⎟⎟⎠

⎞⎜⎜⎝

⎛−×=

⎥⎥⎦

⎤

⎢⎢⎣

⎡−⋅=

−

21

2121

11)(

)()(

)()(

)()(

)()()(

XXZ

vi

vi

iv

iii

pcso

po

beato

po

beato

po

po

po

beatobeato

ω

ωω

ωω

ωω

ωωω

. (3.57)

Where Zcso(ωp) is:

)(//)()( 2111

pcspcspopo

po

po

popcso ZZ

iiv

iv

Z ωωωω

ωωω

ω =+

−=−=)()(

)()()(

, (3.58)

Figure 3.46 shows the simplified terminal characteristics for the paralleling VR

system, where only four useful impedances are drawn. According to (3.56) and (3.57), this

simplified model is adequate to address dynamic current sharing analyses.

io1

X1

X2

io1(fp)

io2(fp)

io2

io1(fbeat)

io2(fbeat)

Zcs1(fp)

Zcs2(fp)

Figure 3.46. Simplified terminal characteristics for a 2-phase interleaved buck VR.

Therefore, the dynamic current sharing study through impedance approach proposed

in Chapter 2 is still applicable by extending the conventional impedance concept.

Moreover, it is now possible to predict the dynamic current sharing error at ωbeat with the

help from the multi-frequency model. It can be observed that equation (3.56) and (3.57)

159


have very similar forms. Namely, the dynamic current sharing error is always evaluated by

the difference of output impedances or their extended forms. In the next section, this

unified impedance approach for dynamic current sharing study will be explained in detail

with examples.

-1/X1

Phase #1

-1/X2

Phase #2

Figure 3.47. Multifrequency model to calculate X1 and X2.

The multi-frequency model to calculate X1 and X2 is illustrated in Figure 3.47 by

simplifying Figure 3.44. Here, because the beat-frequency is generated as a result of the

fedback vo(fp) signal, the phase current fbeat responses are

)()( pobeato vX

i ωω ⋅−=1

11 , (3.59)

)()( pobeato vX

i ωω ⋅−=2

21 . (3.60)

Therefore, it is the admittance that determines the current responses at ωbeat. However, to

make the mathematics an analogy of the traditional definition, the equations of (3.49) and

(3.53) are used.

160


3.4 Prediction of Dynamic Current Sharing Error for Both

Perturbation and Beat Frequency Components

As discussed in the previous section, with the multi-frequency model available for

multi-phase interleaved VRs, output impedances and extended describing functions can be

derived to evaluate system’s voltage regulation and current sharing performance up to the

switching frequency. Without fbeat component at the output voltage, the capacitors do no

carry fbeat-component currents. Hence, the dynamic current sharing error between phase

currents is same as that of the output currents:

2121 ooLL iiii −=− . (3.61)

This means we don’t need to change output impedances’ definition to analyze phase

currents difference. Therefore, the task left is to obtain the expressions of Zcs1, Zcs2, Zcso, X1

and X2. Figure 3.47 illustrates X1 and X2 in the model, which is further simplified from

Figure 3.44. Then it is not difficult to find out X1 and X2 as:

)(')()()('

1

11

beatidpvjD2π

m

beatebeatidsm

GHeFHGRF1X

ωωωω+

= , (3.62)

)(')()()('

2

22

beatidpvjD2π

m

beatebeatidsm

GHeFHGRF1X

ωωωω+

−= . (3.63)

Because vo(ωbeat)≅0, the ωbeat component of iL1 and io1 should be the same. Hence,

Gid1’(ωbeat) is used when calculating X1. As deriving Zcs1, Zcs2 and Zcso, Figure 3.44 needs to

be utilized. A careful look of Figure 3.44 reveals that the sideband components do not

influence the transfer functions of the perturbation frequency. Therefore, it can be easily

obtained that the output impedances are:

161


( )( ) ( )

( )( ) ( )

( )( )p

pid

piipvd

pi

pipOL

pcs TG

GGT

TZ

Zω

ωωω

ωω

ωω

21

1

11

1

11

1 11

+

⋅+

+= , (3.64)

( )( ) ( )

( )( ) ( )

( )( )p

pid

piipvd

pi

pipOL

pcs TG

GGT

TZ

Zω

ωωω

ωω

ωω

22

2

22

2

22

2 11

+

⋅+

+= . (3.65)

Where, for phase #x,

( ) ( ) ( ) LoadpceqpLxpOLx RZZZ 2//// ωωω = , (3.66)

( ) ( )( ) ( ) LoadpceqpLx

Loadpceqinpvdx RZZ

RZVG

2//2//

ωωω

ω+

= , (3.67)

( ) ( ) ( ) LoadpceqpLxinpidx RZZ

VG2//

1ωω

ω+

= , (3.68)

( ) ( )( ) ( ) LoadpceqpLx

Loadpceqpiix RZZ

RZG

2//2//

ωωω

ω+

= , (3.69)

)()()( pepidxsmpix HGRFT ωωω = , (3.70)

)()()( pvpvdxmpvx HGFT ωωω = , (3.71)

)(1)(

)(2pix

pvxpx T

TT

ωω

ω+

= . (3.72)

The bode plots of Zcs1 and Zcs2 are then drawn in Figure 3.48 for a 1-MHz, 2-phase

interleaved buck VR with peak current mode control. The flat portions of Zcs1 and Zcs2 are

contributed by adaptive voltage position (AVP) control requirement. The AVP feedback

loop is not included in Figure 3.44 for simplicity; nevertheless, it does influence Zcs1 and

162


Zcs2. Due to cancellation effect, AVP feedback loop does not influence the beat-frequency

components directly, which means the X1 and X2 will keep the same expressions with or

without AVP control.

1 .103 1 .104 1 .105 1 .10665

60

55

50

1 .103 1 .104 1 .105 1 .10690

45

0

45

90

Zcs1 fsfs

fp (Hz)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)

Zcs2

Figure 3.48. The bode plot of Zcs1 and Zcs2.

Based on Figure 3.48, the dynamic current sharing error at fp, which is predicted by

(3.56), is drawn in Figure 3.49. The magnitude of this curve is determined by the

difference between Zcs1 and Zcs2. Namely, it is the component tolerance decides the

dynamic current sharing error at the perturbation frequency. Usually, the circuit parameters

163


of paralleled phases are designed to be closely matched, leading to a relatively low

magnitude of this curve.

1 .103 1 .104 1 .105 1 .10660

40

20

0

20

fp (Hz)

Mag

nitu

de (d

B)

⎥⎥⎦

⎤

⎢⎢⎣

⎡−⋅=

−)(

1)(

1)()(

)()(

21

21

pcspcspcso

po

popo

fZfZfZ

fififi

Figure 3.49. Dynamic current sharing error at fp.

Meanwhile, based on (3.62) and (3.63), the bode plot of X1 and X2 can also be

obtained, as shown in Figure 3.50. The horizontal axis of Figure 3.50 is still the

perturbation frequency. It can be observed that X1 and X2 are out-of-phase. This means

even with exactly same components in both phases, the current sharing error could still be

large because

1

21 2)()(

)()(X

Zi

iipcso

po

beatobeato ×≈− ωω

ωω . (3.73)

Hence, the current sharing error at the beat-frequency is no longer determined by the

difference in magnitudes of impedances. Instead, it is decided by the sum of them. This is

one reason why the beat-frequency oscillations can get so large even with some attenuation

from the current feedback loops. The other dominant reason for huge beat-frequency

164


oscillations in the output/phase currents is due to the lack of attenuation from the voltage

feedback loop.

1 .103 1 .104 1 .105 1 .10680

60

40

20

1 .103 1 .104 1 .105 1 .106270

180

90

0

90

180

fsfs

fp (Hz)

Mag

nitu

de (d

B)

Phas

e (d

egre

e)X1

Out of phase due to interleaving

X2

Figure 3.50. Bode plot of X1 and X2.

The magnitude of (3.57) is also plotted to evaluate the dynamic current sharing error

at beat-frequency based on X1 and X2. Figure 3.51 shows the result of beat-frequency

dynamic current sharing error prediction. The curve in Figure 3.51 actually has the same

shape as the simulation result in Figure 3.28 if making their horizontal axes the same.

According to Figure 3.51, as fp increase, the beat-frequency decreases, and the amplitudes

165


of beat-frequency oscillations in output currents increases. This is what we have observed

in simulations and experiments.

1 .103 1 .104 1 .105 1 .10660

40

20

0

20

fp (Hz)

Mag

nitu

de (d

B)

⎟⎟⎠

⎞⎜⎜⎝

⎛−×=

−

21

21 11)()(

)()(XX

fZfi

fifipcso

po

beatobeato

Figure 3.51. Dynamic current sharing error at beat-frequency.

With Figure 3.49 and Figure 3.51, it is then possible to study the system’s behavior

completely. If we combine them together into one picture, it will be more convenient. In

this way, the system’s current sharing error as the function of fp is shown in Figure 3.52.

According to Figure 3.52, in this particular design case, the dynamic current sharing

error is dominated by fp component when fp is below 100kHz. If fp keeps increase beyond

100kHz, the dynamic current sharing error is dominated by the beat-frequency component.

When fp approaches fs at 1MHz, the beat-frequency oscillations become very large. The

reason, as shown in (3.73), is because beat-frequency oscillations are determined by the

sum of X1 and X2, instead of their difference. Therefore, reducing parameters’ difference

can only help dynamic current sharing at fp, but not at fbeat. Of course, if components’

166


tolerances increase, the frequency range where fp component dominates dynamic current

sharing error could become wider.

1 .103 1 .104 1 .105 1 .10660

40

20

0

20

)(fi)(fi)(fi

po

beato2beato1 −

)(fi)(fi)(fi

po

po2po1 −

fp (Hz)

Mag

nitu

de (d

B)

Figure 3.52. Evaluate dynamic current sharing performance for both fp and fbeat components.

Figure 3.53 shows a series of simulation waveforms of the dynamic current sharing

error under different fp. When fp=10kHz, io1-io2 is dominated by 10-kHz component, which

has a relatively small magnitude. When fp=100kHz, io1-io2 has both 100-kHz and 900-kHz

components, and they have similar magnitudes. After increase fp to 300-kHz, the beat-

frequency component of 700-kHz become dominant in io1-io2. If further increase fp to 700-

kHz, the 300-kHz beat-frequency component is much larger. The situation becomes even

worse when fp=990kHz and 990kHz. The simulation waveforms are summarized in Table

3.1, where the most important components are highlighted. All these simulation results in

Figure 3.53 are consistent with the prediction in Figure 3.52, which verifies the

derivations. Therefore, it can be seen that the approach of combining output impedances

and their extension of describing functions is very useful in evaluate dynamic current

sharing performance in the frequency range up to switching frequency. Because this

167


approach includes the beat-frequency information, it is especially useful with high-

frequency perturbations.

ip /

A

-10

-5

0

5

10

15

20

25

30


2.65 2.7 2.75 2.8 2.85 2.9 2.95 3

cso

/ V

-40

-30

-20

-10

0

10

20

30

fp=10kHz

i o(A

)i o1

-i o2

(A) 10kHz

50us/div

ip /

A

-10

-5

0

5

10

15

20

25

30


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

cso

/ V

-30

-20

-10

0

10

20

30

i o(A

)i o1

-i o2 (A

)

fp=100kHz

100kHz

900kHz

20us/div

ip /

A

-10

-5

0

5

10

15

20

25

30


2.92 2.94 2.96 2.98 3

cso

/ V

-40

-30

-20

-10

0

10

20

30

i o(A

)i o1

-i o2

(A)

20us/div

fp=300kHz

300kHz

700kHz

(a) fp=10KHz. (b) fp=100KHz. (c) fp=300KHz.

ip /

A

-10

-5

0

5

10

15

20

25

30


2.92 2.94 2.96 2.98 3

cso

/ V

-40

-30

-20

-10

0

10

20

30

20us/div

i o(A

)i o1

-i o2 (A

)

fp=700kHz

300kHz

ip /

A

-10

-5

0

5

10

15

20

25

30


2.92 2.94 2.96 2.98 3

cso

/ V

-40

-30

-20

-10

0

10

20

30

i o(A

)i o1

-i o2 (A

)

20us/div

fp=900kHz

100kHz

ip /

A

-10

-5

0

5

10

15

20

25

30


2.65 2.7 2.75 2.8 2.85 2.9 2.95 3

cso

/ V

-40

-30

-20

-10

0

10

20

30

i o(A

)i o1

-i o2

(A)

50us/div

fp=990kHz

10kHz

(d) fp=700KHz. (e) fp=900KHz. (f) fp=990KHz.

Figure 3.53. Simulation waveforms of dynamic current sharing error with different fp.

Table 3.1. Summary of the simulation results in Figure 3.53: |io(fp)|=10A.

fp 10k 100k 300k 700k 900k 990k

io1(fp)-io2(fp) 1.2A 1.4A 1.7A 0.44A 0.25A 0.26A

168


io1(fbeat)-io2(fbeat) 0.13A 1.04A 3.5A 10.13A 22.5A 30A

Now the current sharing error at both fp and fbeat are solved based on the multi-

frequency model. However, this is not the only concern in terms of dynamic current

sharing. One of the major concerns regarding the beat-frequency oscillation phenomenon is

the high oscillation magnitude in each phase’s current, which endangers the safety of

devices and magnetics. Therefore, it is also necessary to analyze the beat-frequency

oscillation magnitude for each phase, namely the describing function between and

should also be found. Since

)( beatLx fi

)( po fi 0)( ≈beato fv , it can be obtained:

)()(1)(1)()(11

11 popcsopobeatobeatL fifZX

fvX

fifi ×⋅=⋅−== , (3.74)

)()(1)(1)()(22

22 popcsopobeatobeatL fifZX

fvX

fifi ×⋅=⋅−== . (3.75)

Let:

( ) )()(')(, 11 pcsobeatidpvjD2π

mbeatp fZfGfHeFffG = . (3.76)

Then,

( ))('1

,)()(

1

11

beati

beatp

po

beatL

fTffG

fifi

+= . (3.77)

Where,

)()(')(' 11 beatebeatidsmbeati fHfGRFfT = . (3.78)

169


It should be mentioned that Ti1’ is not the same as conventional current loop gain, Ti1.

The reason is because that Gid1’ is not the conventional control-to-inductor-current transfer

function. Nevertheless, those two loop gains are related: their bandwidths are both

determined by the external ramp of the PWM modulator.

The loop gain of Ti1’ is shown in Figure 3.54. Apparently, there is only one loop

gain, Ti1’, can reduce the magnitude of beat-frequency component in iL1. While in the

single-phase case, there is more attenuation from Tv. This is a fundamental difference

between a single-phase VR and a multiphase interleaved VR. Nevertheless, in most VR

applications for the microprocessors and the graphic cards, multiphase topology is much

often used. Hence, it is very important for us to look at the design aspect of Ti1’.

Phase #1

Phase #2

Figure 3.54. The model from ip(fp) to iL1(fbeat).

To design the bandwidth of the loop gain Ti1’, the only parameter can be adjusted is

the external ramp Se. Larger Se means lower bandwidth of Ti1’. Figure 3.55 shows an

example of how Ti1’(fbeat) attenuates G1(fp, fbeat) inside its bandwidth, where the bandwidth

of Ti1’ is denoted as fc_Ti1’. The red curve is the prediction result from (3.77) and the blue

170


dots are the simulation results from Figure 3.28, the perfect match between them verified

the proposed model. In order to emphasis the area where beat-frequency oscillations have

the largest magnitudes, the x-axis of Figure 3.55 is fbeat.

1 .103 1 .104 1 .105 1 .10640

20

0

20

4040

20

0

20

40G

ain

(dB

)M

agni

tude

(dB

)

Frequency fbeat=fs-fp(Hz)

fsfsTi1’(fbeat)

)(i)(i

po

beatL1

ff

fc_Ti1’

)f,(fG beatp1

Dots: Simulation results

Figure 3.55. |iL1(fbeat)/io(fp)| for 2-phase interleaved buck VR.

Moreover, Figure 3.55 clearly shows that the worst scenario of beat-frequency

oscillations in the phase currents happens when fs-fp is lower than the bandwidth of Ti1’.

Under this condition, (3.77) is further reduced to:

171


spvpcso

po

beatL

RfHfZ

fifi 1)()(

)()(1 ××≈ . (3.79)

According to (3.79), it seems that increasing Rs helps to reduce |iL1(fbeat)|. Namely,

increasing the bandwidth of Ti1’ is beneficial for high-frequency dynamic current sharing

performance. In another word, the external ramp Se is preferred to be small in terms of

reducing beat-frequency oscillations. In Figure 3.56, two different designs of Se are

compared to demonstrate this point.

40

20

0

20

40

1 .103 1 .104 1 .105 1 .10640

20

0

20

Gai

n (d

B)

Mag

nitu

de (d

B)

Frequency fbeat=fs-fp(Hz)1 .103 1 .104 1 .105 1 .10640

20

0

20

40

20

0

20

40

Gai

n (d

B)M

agni

tude

(dB

)


fsfsTi1’(fbeat)

)(i)(i

po

beatL1

ff

fsfs Ti1’(fbeat)

fc_Ti1’=160kHzfc_Ti1’=26kHz

)(i)(i

po

beatL1

ff

(a) w/ large Se: Se/Sn=5. (b) w/o Se.

Figure 3.56. Smaller Se is preferred to reduce fbeat oscillations.

With smaller external ramp, Ti1’ has a much wider bandwidth, which results in better

attenuation of the beat-frequency component in inductor currents. In Figure 3.56(b), the

curve is below 0 dB, thus the f)(/)(1 pobeatL fifi beat oscillation is not a problem anymore.

172


However, in practical VR designs, for the purpose of increasing the outer voltage

regulation loop — T2’s bandwidth, Se is normally designed to be relatively large to reduce

the sample-and-hold delay associated with the peak-current mode control [62]. Therefore,

tradeoff exists between fast voltage regulation and dynamic current sharing.

The symmetrical assumption has been used in the section to derive a simple form of

the multi-frequency model for multiphase interleaved buck VRs. This assumption is

normally very close to the reality. Even there must be some asymmetry among paralleled

phases, the effect is still negligible in the analyses of beat-frequency oscillation

phenomenon. The reason is that the current sharing error caused by the beat-frequency

oscillation is usually much larger than that caused by the parameter mismatches under

high-frequency dynamics.

It is worth mention that the adaptive-voltage-position (AVP) function is normally

required for VR applications. This function can be implemented with an additional

feedback control loop, Tavp. Although we did not include Tavp in the previous modeling and

analyses, it can be easily added into the whole picture. Actually Tavp has a very similar role

as Tv or Tve: it adds more attenuation for iL(fbeat) in the single-phase case, while it is

disabled for the multiphase case. Because Tavp controls the total current, it does not have

the beat-frequency component. Therefore, Ti1’ is still the only effective loop in a multi-

phase interleaved VR system to reduce iL1(fbeat).

3.5 Reduce the Beat-Frequency Oscillations in Phase Currents

Since there is conflict between dynamic voltage regulation and beat-frequency

oscillation amplitude, it is desired to have some means to solve this problem. Therefore, in

173


this section, several different methods are proposed for multi-phase VRs to reduce the

beat-frequency oscillations while not impacting the bandwidth of the voltage regulation

loop. Their features and drawbacks are also discussed.

(a) Notch Filter Solution

There are two very important aspects related to the beat-frequency oscillations of

inductor currents: the generation and the attenuation of sideband components. As discussed

earlier, the beat-frequency component is generated when )( pcv ω is sampled by the PWM

comparator. If )( pcv ω itself can be reduced, )(1 beatLi ω would be reduced. However,

)( pcv ω cannot be attenuated effectively because the compensator network, Hv, must be

designed to have sufficient gain at the high-frequency range to achieve a high bandwidth of

the outer voltage-regulation loop.

in out

R

L

C

Impedance of C+L

R=50Ω

fs

(a) A simple R-L-C implementation. (b) Measured characteristics.

Figure 3.57. An example of the notch filter design.

174


In order to solve this issue, one possibility is inserting a notch filter in the feedback

path, whose stop frequency located at fs. It can be implemented either by discrete

components, as in Figure 3.57(a), or inside an IC. The quality factor of the notch filter

should be designed to have sufficient attenuation around fs and very small phase delay at

the desired control loop bandwidth. Meanwhile, it is better to ensure that the whole curve

of is below 0 dB after inserting the notch filter, like in )(/)(1 pobeatL fifi Figure 3.58.

1 .103 1 .104 1 .105 1 .10640

20

0

20

Mag

nitu

de (d

B)

fs)()(1

po

beatL

fifi

w/o notch filter


w/ notch filter

Figure 3.58. Design the notch filter to make |iL1(fbeat)/io(fp)| below 0 dB.

Figure 3.59 compares the experimental waveform before and after applying the notch

filter solution. It can be seen there is a big improvement from the beat-frequency

oscillation point of view, while the loop bandwidth design is not changed.

The notch filter solution is proven very effective in reducing the beat-frequency

oscillations. With the knowledge of what is the original curve, it is then

not difficult to design the notch filter to fulfill certain specification. However, one concern

)(/)(1 pobeatL fifi

175


of this approach is that the switching frequency must been known, which makes it not so

convenient to be implemented inside a control IC chip.

iload (15A/div)


iload (15A/div)


4A*4φ

17A17A

(a) Before adding the notch filter, fs=300kHz, fp=280kHz.

iload (15A/div)


iload (15A/div)

4A*4φ


(b) After adding the notch filter, fs=300kHz, fp=280kHz.

Figure 3.59. Improvement of the beat-frequency oscillations with notch filter solution.

(b) Average Current Mode Control

If we can increase the attenuation from Ti’ while not impact the outer loop’s

bandwidth, then it is expected that the beat-frequency oscillation problem would be

176


relieved. One way to do this is using average-current mode control instead of the peak-

current mode control. As illustrated in Figure 3.60, average-current mode control needs

one more opamp, Hi, to compensate the current feedback loop gain. Meanwhile, the

sample-and-hold effect is reduced. Therefore, the loop gain, Ti1’, becomes:

)()(')( 11 beatisbeatidmbeati ωHRωGFω'T = . (3.80)

Since Hi can be designed with a much higher low-frequency gain, it is then possible for Ti’

to do more attenuations of the beat-frequency oscillations when fp approaches fs, which is

exactly the worst case.

Figure 3.60. The average-current mode control.

Figure 3.61 compares the loop gain Ti’ and the describing function

for both average and peak-current mode controls with the same voltage loop bandwidth

design. It can be seen that due to higher T

)(/)(1 pobeatL fifi

i’ gain of average-current mode control (shown in

the shaded area), it has smaller beat-frequency oscillation magnitude especially in the low

frequency range. However, if fbeat increase, those two are not very different. The time-

domain simulation waveforms in Figure 3.62 demonstrate the larger benefit of average-

current mode control in the lower frequency range.

177


1 .103 1 .104 1 .105 1 .10640

20

0

20

40

60

ACCACC

1 .103 1 .104 1 .105 1 .10640

20

0

20

Loop gain Ti1’G

ain

(dB

)

fsfs

PCCM

agni

tude

(dB

)

PCC

)(/)(1 pobeatL fifi

ACC


Figure 3.61. The average-current mode control leads to smaller beat-frequency oscillations.

10A

32A

-20

-10

0

10

20

30


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

-10

0

10

20

iL1 & iL2(A)

PC

CA

CC

20A

27A

-20

-10

0

10

20

30


2.92 2.94 2.96 2.98 3-20

-10

0

10

20

40kHz40kHz

40kHz40kHz

iL1 & iL2(A)

PC

CA

CC

10kHz10kHz

10kHz10kHz

(a) fp=990kHz, fs=1MHz, 0~20A load. a) fp=960kHz, fs=1MHz, 0~20A load.

Figure 3.62. Simulation comparison of average and peak current mode control.

178


The downsides of this solution include: additional opamp is needed for the current

feedback loop; the instantaneous protection from peak-current mode control is no longer

available.

(c) Nonlinear Approaches

Nonlinear control methods can also be adopted for reducing beat-frequency

oscillation purpose. The most straightforward method is to vary the switching frequency,

so that fbeat moves to a higher frequency region and gets more attenuation. For example,

Figure 3.63 shows the improvement by changing fs from 1-MHz to 1.2-MHz when

fp=990kHz.

fload=990kHz, fs=1.2MHzfload=990kHz, fs=1.2MHzfload=990kHz, fs=1MHzfload=990kHz, fs=1MHz


2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7

A

-20

-10

0

10

20

30

10kHz10kHz210kHz210kHz

& i L

2(A

)i L1

Figure 3.63. Change the switching frequency to reduce beat-frequency oscillations.

w/o phase shiftw/o phase shiftw/ phase shiftw/ phase shift

i L1&

i L2(

A)


2.35 2.4 2.45 2.5 2.55 2.6 2.65 2.7

30

20

10

A

-20

0

-10

Figure 3.64. Change the interleaving operation to reduce fbeat oscillations: fp=990kHz, fs=1MHz.

179


Another implementation of nonlinear control that can reduce fbeat oscillation is to

change the interleaving operation. As been pointed out in section 3.3, cancellation of the

Tv(ωbeat) loop is due to the phase-shift operation. If there is no interleaving among phases,

then the VR system is equivalent to a single-phase buck, so that the beat-frequency

oscillations in the phase currents can be significantly reduced. Figure 3.64 demonstrates

the benefit of disabling the phase-shift operation among phases. Today, in some VR

controllers, nonlinear control schemes such as adaptive transient response have been

realized already, which can turn on all phases simultaneously when fast transients occur.

For this kind of control IC, the additional benefit of decreased beat-frequency oscillations

may be obtained with proper design.

One practical concern of these nonlinear solutions is how to trigger and when to quit

from the abnormal operation mode. For example, in normal operation, interleaving is still

preferred; once the huge beat-frequency oscillations are detected or predicted, the IC

should enter the non-interleaving mode; when the load transient frequency becomes

slower, the controller should be able to return to normal operation with interleave.

Therefore, some kind of detecting mechanisms are needed for the controller to react

correspondingly.

(d) Reduce Beat-Frequency Oscillations With Coupled Inductors

Recently there has been a lot of study about the benefit of using coupled inductor in

the multiphase VR system. This idea was proposed by Pit-Leong Wong in [63]. Figure

3.65 illustrates the concept and waveforms of inversely coupled inductors used in VR

applications. L1 and L2 are the self inductances of each phase, M is the mutual inductance

between them, 0<M<1. Hence,

180


dtdiM

dtdiLv LL

L21

11 −= , (3.81)

dtdiM

dtdiLv LL

L12

22 −= . (3.82)

M

vin

+ vL1 -

+ vL2 -

(a) A 2-phase buck with inversely coupled inductor.

(b) Waveforms with coupled inductors.

Figure 3.65. Using inversely coupled inductor in multiphase VRs.

181


It is found that the power stage shows different inductances during different time

periods of one switching cycle. Assuming the self inductances are the same: L=L1=L2, the

equivalent inductances in Figure 3.65(b) are calculated when D<0.5 as:

MDDL

MLLeq

⋅′

−

−=

22

1 , (3.83)

MLLeq −=2 , (3.84)

MDDL

MLLeq

⋅′

−

−=

22

3 . (3.85)

Leq1 determines the steady-state ripple of the inductor current; Leq2 determines the

speed of transient response. Since Leq1 is always larger than L, and Leq2 is always smaller

than L, the nonlinear behavior of the coupled-inductor reduces the steady-state current

ripple and accelerates VR’s transient response. This is one of the major advantages to

adopt coupled inductors for VRs. Moreover, it has been found that the sample-and-hold

delay associated with peak-current mode control is reduced with coupled inductors [62],

making it possible to bypass the tradeoff between current loop and voltage loop’s

bandwidth.

In terms of the beat-frequency current sharing problem, the coupled inductor could

have advantages in two aspects. First, the nonlinear inductance changes the power stage

transfer functions. And second, possible higher current feedback loop gain can increase the

attenuations for the beat-frequency components. The first aspect is carefully discussed in

the following part of this section. The second benefit has been elaborated in [62].

182


+ vL1 -

+ vL2 -vin

Figure 3.66. Equivalent circuit of Figure 3.65(a).

Let’s first look at the benefit brought by the nonlinear inductance. According to

(3.81) and (3.82), Figure 3.65(a) is equivalent to Figure 3.66. For different frequency

components, fp and fbeat, Figure 3.66 can be further simplified to two different circuits in

the small-signal sense. For example, considering , the small-signal model

for ω

)(ˆ)(ˆ21 pp dd ωω ≈

p component is shown in Figure 3.67.

)(2 pLi ω

)(1 pindv ω

)(2 pindv ω

)(1 pLi ω

)( pov ω

)(2 beatLi ω

)(1 beatindv ω

)(2 beatindv ω

)(1 beatLi ω

0)( ≈beatov ω

Figure 3.67. Small-signal model of Figure 3.66

for ωp components.

Figure 3.68. Small-signal model of Figure 3.66 for

ωbeat components.

183


So the equivalent per phase inductance for ωload component is L-M, namely the

transient inductance, Leq2. However, for the ωbeat component, the relationship among duty

cycles becomes )()( 22 beatbeat dd ωω −≈ . Based on this, the small-signal model of the ωbeat

component is derived in Figure 3.68, where the equivalent per phase inductance is changed

to L+M. Comparing with Figure 3.66, the ωbeat components doesn’t see the –M inductance

and the capacitor on the interconnection point. This is because 0)()( 21 ≈+ beatLbeatL ii ωω , so

that those two are not change anything.

Based on Figure 3.68, the power stage transfer function of Gid’ should be:

)()('

MLjωVωG

beat

inbeatid +

= . (3.86)

Compare with (3.46) for the non-coupled case, we can see that the attenuation from the

power stage is larger with coupled inductor. Table 3.2 summaries the different inductance

for non-coupled and coupled inductors under different frequencies. Where Lnc denote the

inductance for the non-coupled case, it is always the same no matter what frequency is

concerned.

Table 3.2. Inductance comparison for ωp and ωbeat with 2-phase coupling.

Non-coupled inductor Coupled-inductor

Equivalent per phase

inductance for ωp: Lnc L-M


inductance for ωbeat: Lnc L+M

184


To make a comparison with non-coupled case, it is convenient to let Lnc=L-M. By

doing so, these two cases keep the same transient inductance, thus there is no need to

redesign the feedback control loops. Now if we define the coupling coefficient α as:

LM

=α , (3.87)

then we have:

)1( α−= LLnc . (3.88)

And the attenuation from the power stage to iL1(ωbeat) is determined by Lnc for non-coupled

case and L+M for the coupled case. Therefore, the ratio of beat-frequency oscillations in

inductor currents between coupled and non-coupled case can be obtained as:

αα

ωω

+−

=+−

=+

∝11

/1)/(1

)()(

_1

_1

MLML

LML

ii

ncncbeatL

cpbeatL . (3.89)

0 0.2 0.4 0.6 0.8 10

0.25

0.5

0.75

1

Coupling coefficient α

αα

+−

11

ncbeatL

cpbeatL

ii

_1

_1

)()(

ωω

Figure 3.69. The ratio of fbeat oscillations between non-coupled and 2-phase coupled inductor case.

185


Figure 3.69 plots the gain of equation (3.89). It can be observed that with larger α,

the beat-frequency oscillation becomes smaller. If perfect coupling can be achieved so that

α=1, then there is no beat-frequency oscillation anymore. This is because each phase can

only see 2fs ripple on their inductor current under this condition.

If N phases are coupled together instead of 2, and the mutual inductance between any

2 phases is M, then the coupling coefficient can be written as:

LMN )1( −

=α . (3.90)

Then the per phase transient inductance is calculated by:

MNLLeq )1(2 −−= . (3.91)

Table 3.3. Inductance comparison for ωp and ωbeat with N-phase coupling.

Non-coupled inductor Coupled-inductor


inductance for ωp: Lnc L-(N-1)M


inductance for ωbeat: Lnc L+M

Table 3.3 shows the comparison for N-phase coupled inductor. The per phase

equivalent inductance for ωbeat component is still L+M with coupling. If we still keep

Lnc=Leq2, then (3.88) still holds by the definition of α. And the ratio of beat-frequency

oscillations in inductor currents between N-phase coupled and non-coupled case is:

186


11

1/1

)/(1)()(

_1

_1

−+

−=

+∝

NL

MLii

ncncbeatL

cpbeatL

αα

ωω

. (3.92)

Apparently, (3.89) is only a special case of (3.92). With different N, Figure 3.70

shows the gain of (3.92), from which the phenomenon of diminishing return can be

observed when N increases.

0 0.2 0.4 0.6 0.8 10

0.25

0.5

0.75

1

Coupling coefficient α

n=3

n=4

n=2

ncbeatL

cpbeatL

ii

_1

_1

)()(

ωω

Figure 3.70. The ratio of fbeat oscillations between non-coupled and N-phase coupled inductor case.

To verify these derivations, an experiment has been done on a 4-phase, 273-kHz

industry’s VR demo-board. This board adopted the dual-loop current sharing structure with

a very slow and weak current sharing loop. Therefore, it can be treated as voltage-mode-

controlled, and the attenuation of beat-frequency oscillation is merely depending on the

power stage’s Gidx’. Because of this, it is an ideal test-bed for us to verify the conclusion in

(3.92). In this test, the per-phase transient inductance is kept the same for the setups of

non-coupled and 4-phase coupled tests.

187


30A

13kHz

iL1

iL3

vo

io

(a) With non-coupled inductors.

7.5A13kHz

iL1

iL3

vo

io

(b) With 4-phase coupled inductors, α=0.67.

Figure 3.71. The experimental waveforms of the fbeat oscillations: fs=273kHz, fp=260kHz, transient

inductance=120nH, load current jumps from 5 to 15A. Channel 1: iL1 (25A/div); Channel 2: iL3

(25A/div); Channel 3: vo (50mv/div); Channel 4: io (10A/div).

The test waveforms are shown in Figure 3.71. Without coupled inductor, the inductor

currents have about 30-A oscillations at 13-kHz. After changing the original inductors to

188


4-phase coupled inductor without modifying the control designs, the oscillation magnitude

reduced to 7.5-A. This about 4-times improvement is exactly what has been predicted by

(3.92), since α in this particular coupled inductor design equals 0.67. Therefore, these test

results prove the analyses about how much benefit is introduced by the coupling concept.

The reduction of beat-frequency oscillation’s magnitude by coupled inductor

certainly is beneficial in terms of decreased stress on the devices. However, it is

questionable whether the flux density has also been improved. In Figure 3.68, the volt-

second across the inductor is only determined by )(1 beatindv ω and )(2 beatindv ω . Therefore,

no matter we uses coupled inductor or not, the flux density in the core is identical with

same )(1 beatd ω and )(2 beatd ω . So actually, if we only use the coupled inductor in the way

presented in Figure 3.71, the magnetic core is still under the risk of high flux density when

there is high-frequency load transients. To solve this issue and further improve the

coupled-inductor solution, current-mode control with high current-loop bandwidth can be

utilized.

As mentioned before, there are a lot of benefits with the coupled inductor solution

besides the high-frequency dynamic current sharing performance. For example, coupled

inductors make it possible to design a much higher current feedback loop bandwidth

without compromise the voltage regulation performance [62]. This adds additional benefit

in terms of reducing beat-frequency oscillations since current loop gain is increased to give

more attenuation. Therefore, the coupled inductor is a very promising solution. However,

there is one drawback about coupling, namely the sub-harmonic instability is easier to

happen with more phase coupling. Since the inductor currents have N*fs information, the

maximum duty cycle for the sub-harmonic oscillations to occur becomes proximately N

189


times smaller when the coupling is strong. Therefore, one must be aware of this situation

when designing. Sometimes it becomes necessary to add external ramp to avoid this

problem, although it is not required from the high-bandwidth design aspect.

3.6 Summary

In summary, this chapter addresses the issue of high-frequency dynamic current

sharing for multiphase interleaved buck VRs. It is observed in experiments that when a

multiphase VR is subjected to high-frequency repetitive load transients, there exist huge

beat-frequency oscillations in the phase currents. The oscillations decreases reliability of

the whole system, therefore they need to be carefully studied and understood. The reason

for this phenomenon is the sampling characteristic of the PWM modulator. In order to

study this phenomenon, the conventional output impedance concept has been expanded to

describing function approaches. Moreover, to obtain related describing functions, an

unconventional small-signal model including the beat-frequency information is developed.

This model is effective up to the switching frequency with one of the sidebands included.

It precisely predicts the magnitude of ωbeat component in phase currents for single-phase

and multi-phase VRs. Based on this model, analyses indicate that only the current feedback

loop is capable of attenuating the beat-frequency oscillations in the multiphase interleaving

buck VRs. The tradeoff between high-bandwidth design and small beat-frequency

oscillations is then revealed.

To resolve this conflict, several solutions are proposed. The source of the beat-

frequency components can be diminished with a notch filter, namely to minimize fp-

component in the control voltage caused by the load perturbations. By using the average-

190


current mode control, it is possible to boost the current loop gain in the low-frequency

range and hence improve attenuations for the beat-frequency components. Nonlinear

controls such as changing switching frequency or interleaving operation could also benefit

the high-frequency dynamic current sharing issue. At last, the coupled inductor solution is

found to be a very promising way with many benefits, including significantly reduced

beat-frequency oscillations and flux densities. Simulation and experimental results have

proven the analyses and solutions.

It is worth to mention that although this beat-frequency study is based on the inner-

loop current sharing structure, the similar problem can be seen in the dual-loop controlled

test-beds. Should more study about dual-loop structure needed, the concept of multi-

frequency model is also applicable. Furthermore, the beat-frequency phenomenon has been

observed in many other applications whenever two similar frequencies are interacted in a

PWM modulator. Different from the multiphase VR system discussed here, the beat-

frequency oscillations on the input and/or output bus could be the major concern.

191

Chapter 4. Current Sharing Study under

Ultra-High-Frequency Dynamics

4.1 Observations

In the studies of Chapter 3, we have assumed the perturbation frequency is below the

switching frequency. However, as aforementioned, the load frequency can be higher than

the switching frequency. To investigate the dynamic current sharing performance,

simulations have been done based on the same VR system in Figure 4.1 with sinusoidal

perturbations on the load current. The power delivery path including parasitics and

different kinds of capacitors is also drawn in Figure 4.1, these parameters greatly influence

the total output impedances of the VR system, Zcso [64]. It will be shown later that Zcso

has a significant impact on the magnitudes of beat-frequency oscillations.

Zcso

Figure 4.1. A 2-phase VR system subjected to load transients, fs=1MHz.

192

Juanjuan Sun Chapter 4. Current Sharing Study under Ultra-High-Frequency Dynamics

For a 1-MHz 2-phase buck converter, Figure 4.2 shows the comparison between a

990 kHz and a 2.99 MHz perturbation. Clearly, both of them have the 10-kHz beat-

frequency oscillation, while the one with 2.99 MHz perturbation is much severe.


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30

fs-fload=10kHz

8A

Time (ms)

&

(A)

i L2i L1

(a) fp=990 kHz


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30

Time (ms)3fs-fload=10kHz

39.4A

&

(A)

i L2i L1

(b) fp=2.99 MHz

Figure 4.2. Simulation waveforms of the phase currents in a 1-MHz 2-phase interleaved buck VR with

5A sinusoidal perturbation in load currents.

To understand the phenomenon in Figure 4.2, the multi-frequency model described in

Chapter 3 is extended. First, we need to identify the reason for the beat-frequency

oscillation when the perturbation frequency, fp, is higher than the switching frequency. As

shown in Figure 4.3, many sidebands are generated from PWM. However, not all of them

have significant influence in the phase current. Because of the low-pass filter in the

converter, it is the one with the lowest frequency that has the largest magnitude.

193


ii ooˆˆ

21−

i oˆ

ii ooˆˆ

21−

i oˆ

(a) fp<<fs.

ii ooˆˆ

21−

i oˆ

ii ooˆˆ

21−

i oˆ

(b) fp≅fs.

ii ooˆˆ

21−

i oˆ

ii ooˆˆ

21−

i oˆ

(c) fp≅2fs.

194


ii ooˆˆ

21−

i oˆ

ii ooˆˆ

21−

i oˆ

(d) fp≅3fs.

Figure 4.3. Spectra with different perturbation frequencies.

To study the higher order beat-frequency issue, the same approach using the terminal

characteristics as in Chapter 3 can be adopted. However, in order to obtain the information

of more frequency components, more extended describing functions needed to be

incorporated, as shown in Figure 4.4. With a series of X1 to represent the terminal

characteristics of the first phase, we now have the freedom to study any frequency

component in io1. Nevertheless, it is usually not necessary to include all of them.

Depending on where is fp, the sideband component appears in low-frequency range should

be the most important one.

In this chapter, the dynamic current sharing issue for multiphase buck VRs under

ultra-high-frequency perturbations is studied. Since the perturbation comes from the load

transients, thus

loadp ff = . (4.1)

Therefore, in the following studies, fload is used to represent the perturbation frequency.

195


i o1(f l

oad)

)(

)(

)(

fload

o

fload

oflo

adcs

oiv

Z−

=

Figure 4.4. Using terminal characteristics for higher order beat frequency study.

i o1(f s

-f loa

d)

i o1(k

f s-f l

oad)

))

(1()

(1flo

ado

fload

oflo

adcs

ivZ

−=

)(1

)(

)(1

fload

fso

fload

oflo

adfs

ivX

−−

−=

)(2

)(

)(2

fload

o

fload

oflo

adcs

ivZ

−=

)(2

)(

)(2

fload

fso

fload

oflo

adfs

ivX

−−

−=

)(1

)(

)(1

fload

kfs

o

fload

oflo

adkf

siv

X−

−−

=

i o2(f s

-f loa

d)

i o2(k

f s-f l

oad)

)(2

)(

)(2

fload

kfs

o

fload

oflo

adkf

siv

X−

−−

=

i o2(f l

oad)

196


4.2 The Extended Multi-Frequency Model for 2-phase VR

The key of extending the multi-frequency model is still the PWM function. Figure

4.5 illustrates the simplified model for the kfs-fload component with a 2-phase interleaved

buck VR. Figure 4.5 looks pretty similar to Figure 3.42, except that kωs-ωload substitutes

ωbeat, and PWM function is influenced by k.

PWM

∑∑

)( loadcv ω)( loadoi ω )(1 loadsL ki ωω −

)(2 loadsL ki ωω −

)( loadso kv ωω −

)(1 loadso kv ωω −

)(2 loadso kv ωω −

-Hv(kωs-ωload)

)( loadsc kv ωω −

)()(

loado

loadc

iv

ωω

Figure 4.5. Simplified kωs-ωload frequency component model for 2-phase buck.

If k equals an odd number, then ejkπ=-1. Therefore, similar to the first-order beat-

frequency components, the PWM function of phase #1 and #2 is negative to each other.

This means the cancellation of )( loadso kv ωω − and Tv(kωs-ωload), and io1(ωbeat)=iL1(ωbeat)

with equally distributed output capacitance. Under this condition, Figure 4.5 can be

reduced to Figure 4.6 for peak-current-mode control. It is derived that:

)(/)(' 11 loadsLinloadsid ωkZVωkG −=− ωω , (4.2)

)()(')( 11 loadsesloadsidmloadsi ωkHRωkGFωk'T −−=− ωωω , (4.3)

197


)()('1

)(')(

)()(

)()(

1

12

11

loadcsoloadsi

loadsidloadvmjkD

loado

loadsL

loado

loadso

ZkT

kGHFe

iki

iki

ωωω

ωωω

ωωω

ωωω

π

×−+

−=

−=

−

. (4.4)

Where Zcso(ωload) is the total output impedance as marked in Figure 4.1. Since fload>>fs/2, in

this frequency range the closed-loop output impedance Zcso is the same as the open-loop

output impedance, ZOL. While, ZOL is mostly determined by paralleled output capacitors in

the high-frequency region [64]. Comparing (4.4) with (3.77), it can be found that for either

fs-fload=10kHz or 3fs-fload=10kHz, the attenuation from Ti’ loop gain is the same. Thus the

difference between Figure 4.2(a) and (b) must come from Zcso(ωload)*Hv(ωload). Hv is

normally designed to be a sharp low-pass filter after fs, its effect on the beat-frequency

oscillations is predictable. Therefore, the difference of magnitudes of the first-order and

higher-order beat-frequency is typically determined by the output impedance Zcso.

)( loadcv ω)( loadoi ω)( loadcsoZ ω−

)( loadov ω)( loadvH ω−

)(1 loadsL ki ωω −)(1 loadskd ωω −


Figure 4.6. Simplified kωs-ωload component model for 2-phase buck when k is an odd number.

Figure 4.7 shows the Bode plot of Zcso and its impact on the beat-frequency

oscillations. The dips and peaks of Zcso are determined by the configuration of capacitors as

in Figure 4.1. In this particular case, Zcso has a much higher value at 2.99-MHz than at 990-

kHz due to the ESL of decoupling capacitors. Although Hv is lower at 2.99-MHz, which

198


compensates a little bit of the impedance increase, Zcso*Hv is still higher at 2.99-MHz.

Therefore, the high peak of the output impedance at 3-MHz explains the reason why the

third-order beat-frequency oscillation is much severe in Figure 4.7(b) and (c).

f req / Hertz

1k 2k 4k 10k 20k 40k 100k200k 1M 2M 4M 10M20M 40M 100M

Gai

n / d

B

-120

-100

-80

-60

-40

-20

0

Frequency fload (Hz)

990k

2.99M

|ZC

so| (

dB)

(a) Zcso of the 2-phase buck VR.


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

30


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30


39.4A

A

-20

-10

0

10

20

fs-fload=10kHz

8A

& (A

)

& (A

)

i L2 i L2

i L1 i L1

Time (ms)

(b) fload=990 kHz. (c) fload=2.99 MHz.

Figure 4.7. Zcso of the VR leads to the higher magnitude of 3rd-order beat-frequency oscillations.

On the other hand, if k is an even number, the situation is very different. According

to Figure 4.5, the describing function of )(/)(2 loadcloads vkd ωωω − is ejkπejkDd2π=

ejkDd2π, which is exactly the same as the first phase. Therefore, there is no cancellation of

kωs-ωload component at the output: 0)( ≠− loadso kv ωω . This is better than the case when k

199


equals odd number, because the presence of Tv(kωs-ωload) helps to attenuate the higher-

order beat-frequency component, just like the single-phase case. Figure 4.8 shows the

simulation result when fload approaches 2fs. In contrast to Figure 4.2, the second-order beat-

frequency oscillations are so small that they are almost invisible.


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30

2fs-fload=10kHz

40mA

Time (ms)

&

(A)

i L2i L1

Figure 4.8. Simulation waveforms of the phase currents in a 1-MHz 2-phase buck VR with 5A

sinusoidal perturbation in load currents: fload=1.99MHz, fs=1MHz.

In conclusion, for a 2-phase interleaved buck VR, the higher-order beat-frequency

oscillations have two different situations. When k equals even number, the oscillation is

too small to be concerned. When k is an odd number, the oscillation magnitude is

determined by the output impedance. The worst case of beat-frequency oscillation happens

when kfs coincide with the peak of Zcso, thus if there is not enough attenuation from Hv, the

kth-order beat-frequency oscillation could be huge when fload approaches kfs.

4.3 The Extended Multi-Frequency Model for N-phase VR

In order to generalize the study, the multi-frequency model is extended to N-phase

interleaved VRs in the section. A peak-current mode controlled, N-phase interleaved buck

VR is shown in Figure 4.9 as the study case. Its small signal model for the kωs-ωload

components is shown in Figure 4.10.

200


PWM

Vc

Vin

Vo

PWM HvVref

L1

L2

d1

d2

iL1

iL2

Se

Se

PWM

LN

dN

iLN

Se

CbulkCdecp

io

CpkgCdie

Zcso

-+

Tv

Rdroopio

Figure 4.9. N-phase interleaved, peak-current mode controlled buck VR.

PWM

∑∑∑

feedback

)( loadso kv ωω −



)( loadsLN ki ωω −

)( loadsc kv ωω −

)( loadcv ω

Figure 4.10. Small signal model of the kωs-ωload components for a N-phase interleaved VR.

201


The PWM function is related to k and N. For phase #x, the describing function of

)(/)( loadcloadsx vkd ωωω − is:

mjkDNxjk

loadc

loadsx Feevkd ππ

ωωω 2/)1(2

)()( −=

− . (4.5)

If , where i is any integer, then: iNk ⋅≠

0)(1

/)1(22

1

=⋅=− ∑∑=

−

=

N

x

NxjkjkDmloads

N

xx eeFkd ππωω . (4.6)

If , then: iNk ⋅=

0)( 2

1

/)1(22

1≠⋅=⋅=− ∑∑

=

−

=

πππωω jkDm

N

x

NxjkjkDmloads

N

xx eNFeeFkd . (4.7)

Therefore, the kωs-ωload component from each phase gets cancelled at the output if

. However, they adds up at the output when iNk ⋅≠ iNk ⋅= . This is because of the

interleaving operation samples at different moments of one switching cycle for different

phases.

Figure 4.11 gives an intuitive example by drawing several different fload with 4-phase

interleaving. Only when fload is approaching 4fs, every phase sees the same value of

vc(ωload). Otherwise, the sampled values of vc from different phases always sum together to

be 0. As the result, for the iNk ⋅≠ case, there is no vo(kωs-ωload) and the only loop gain

attenuates iLx(kωs-ωload) is still Tix’. Hence, the describing function of beat-frequency’s

magnitude vs. the load transient is very similar to the 2-phase case:

202


)()('1

)(')(

)()(

)()(

loadcsoloadsix

loadsidxloadvm

loado

loadsLx

loado

loadsox

ZkT

kGHF

iki

iki

ωωω

ωωω

ωωω

ωωω

×−+

−=

−=

−

, (4.8)

)(/)(' loadsLxinloadsidx ωkZVωkG −=− ωω , (4.9)

)()(')( loadsesloadsidxmloadsix ωkHRωkGFωk'T −−=− ωωω . (4.10)

Equation (4.8) means that when iNk ⋅≠ , the kth-order beat-frequency oscillation in

inductor currents is closely related to the output impedance, Zcso at the perturbation

frequency. Comparing with 2-phase case, more phase interleaving does not benefit the

beat-frequency current sharing issue.

fload fs

vc(ωload)

fload 2fs

vc(ωload)

fload 2fs

vc(ωload)

fload 3fs

vc(ωload)

fload 3fs

vc(ωload)

Phase #2Phase #1

Phase #3

fload 4fs

vc(ωload)

fload 4fs

vc(ωload)

Phase #4

Figure 4.11. The cancellation of kωs-ωload component with 4-phase at different fload.

203


On the other hand, if iNk ⋅= , thus Tv(kωs-ωload) in Figure 4.10 is not cancelled.

Because of the additional attenuation from Tv(kωs-ωload), iLx(kωs-ωload) become much

smaller, just like the simulation case with 2-phase VR in Figure 4.8 when fload≅2fs.

5kHz

iL1

iL3

5kHz

iL1

iL3

ioio

(a) fload=585kHz, 2fs- fload=5KHz. (b) fload=880kHz, 3fs- fload=5KHz.

5kHz

iL1

iL3

iL1

iL3

io io

(c) fload=1175kHz, 4fs- fload=5KHz. (d) fload=1470kHz, 5fs- fload=5KHz.

Figure 4.12. Experimental waveforms of a 4-phase interleaved buck VR with fs=295kHz. Load current

jumps from 0 to 10A. Channel 1: iL1 (25A/div); Channel 2: iL3 (25A/div); Channel 4: io (10A/div).

Experiments have been done to verify the modeling and analyses regarding the

higher-order beat-frequency oscillations. The test-bed is a 4-phase interleaved buck VR

204


with fs=295kHz. High-frequency pulsed currents jumping from 0 to 10A were applied to

the load side to test the higher-order beat-frequency oscillations in phase #1 and #3. Figure

4.12 shows the test waveforms under different fload.

Figure 4.12 clearly demonstrates the difference between iNk ⋅≠ and iNk ⋅= .

Since N=4 in the experiments, the beat-frequency oscillations is negligible only when fload

getting close to 4fs in Figure 4.12(c). There is only very small oscillation in phase #1 due to

phase mismatching in hardware implementation. As for fload approaching 2fs, 3fs and 5fs,

the kfs-fload components are very obvious according to Figure 4.12(a), (b) and (d). The

magnitudes of oscillations are determined by the value of Hv*Zcso at fload. Therefore, the

worst case happens when fload≅2fs, where the impedance and Hv are both higher. For

fload≅5fs, the oscillations become smaller due to smaller Hv at higher frequency.

4.4 Avoid the Worst Case by Making Use of the Cancellation of Higher-

Order Beat-Frequency Components

The fact that higher-order beat-frequency oscillation becomes much smaller as fload

approaches N*i*fs makes it possible to purposely design the switching frequency or the

phase number to avoid the worst scenario. The worst scenario happens when the peak of

Zcso*Hv coincides with kfs and iNk ⋅≠ . For example, the 2-phase VR in section 4.2 has a

peak in Zcso at 3-MHz, which is 3 times of the switching frequency. Therefore, very high

amplitude 3rd-order beat-frequency (about 16 times of the load perturbation magnitude) is

observed when fload approaches 3fs. In order to avoid this disastrous situation, there are two

possible solutions. The first one is to change phase number from 2 to 3, thus the peak of

205


Zcso happens when and there would be adequate attenuation for the 3fiNk ⋅= s-fload

component. Figure 4.13 demonstrates this solution.


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30

fs-fload=10kHz

8A

Time (ms) time/mSecs 20? ecs/div

2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30

i L1&

(A

)i L2

i L1&

i L2 &

i L3(

A)

8A

fs-fload=10kHz

Time (ms)

(a) fload=990kHz, fs=1MHz, 2-phase. (b) fload=990kHz, fs=1MHz, 3-phase.


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-10

-5

0

5

10

15

Time (ms)

i L1&

i L2 (A

)


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-10

-5

0

5

10

15

15.5A

Time (ms)

40mA&

i L2 &

i L3(

A)i L1

2fs-fload=10kHz

(c) fload=1.99MHz, fs=1MHz, 2-phase. (d) fload=1.99MHz, fs=1MHz, 3-phase.


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30


39.4A


2.8 2.82 2.84 2.86 2.88 2.9 2.92 2.94 2.96 2.98 3

A

-20

-10

0

10

20

30

63mA

& i L2

& i L

3(A)

&

(A)

i L2i L1

i L1

Time (ms)

(e) fload=2.99MHz, fs=1MHz, 2-phase. (f) fload=2.99MHz, fs=1MHz, 3-phase.

Figure 4.13. Change the phase number to avoid the worst scenario (5-A sinusoidal perturbation was

added at load current for all simulations).

206


The other way is to modify the switching frequency of the original 2-phase converter

to 750-kHz so that 4fs=3MHz. The essence of this change is the same as the first method:

to make the peak of Zcso happen at N*i*fs. Still using the 2-phase 1-MHz VR as an

example,

Comparing Figure 4.13 (e) and (f), the amplitude of 3rd-order beat-frequency

oscillation is considerably reduced. Therefore, the worst case scenario can be avoided.

However, the improvement comes with a price. Namely, the 2nd-order beat-frequency

oscillation becomes much larger with 3-phase according to Figure 4.13 (c) and (d).

Nevertheless, the 2nd-order beat-frequency oscillation is still smaller than that of 3rd-order.

Therefore, this tradeoff can be justified.

4.5 Summary

Based on the multi-frequency model proposed in the last chapter, this chapter focuses

on the higher-order beat-frequency current sharing issue when fload approaches kfs. For

prediction and analyses purpose, the multi-frequency model is extended to include more

sidebands. The major concern still is about kfs-fload falling into the low-frequency range. It

is found that when k equals integer times of the phase number, N, there is not too much

problem of the higher-order beat-frequency oscillations due to additional attenuation from

the Tv loop. However, if , the higher-order beat-frequency oscillation’s amplitude

can be even higher than the first-order. The reason is because of the peak in the total output

impedance, which is mostly determined by the combination of output capacitors in the

high-frequency range where we are concerned about. Experiments and simulations have

verified these conclusions. Therefore, in order to avoid the worst scenario, which happens

iNk ⋅≠

207


when the peak of Zcso*Hv coincides with kfs and iNk ⋅≠ , there are two different ways to

make the peak of Zcso happen at N*i*fs. Namely, the switching frequency or the phase

number can be designed to avoid the worst case. One interesting thing to note is that

although the conventional output impedance cannot be directly used for high-frequency

dynamic current sharing analyses, the final result derived from an unconventional high-

frequency model again shows the importance of the output impedance concept.

208

Chapter 5. Conclusions

5.1 Conclusions

To meet the growing demand for higher power systems, as well as to supply the fast

evolving powerful IC chips, distributed power architecture is becoming the better choice

for more and more applications. The paralleling operation of DC/DC switching converters

is widely used in distributed power systems due to the request of high reliability and ease

of standardization. However, as a result of limited tolerance of components, current

sharing control is usually necessary for paralleling systems to balance the load current

among modules or phases. Passive current sharing methods such as droop rely on the

internal and/or external resistance of power converters to distribute current relatively

evenly, meanwhile the voltage regulation is degraded. Therefore, the active current sharing

schemes with a current sharing bus are much more favorable in the applications requiring

tight regulation.

Three active current sharing structures, including outer-loop, dual-loop and inner-

loop have been practiced in the industry. It has been analyzed and demonstrated that these

methods can achieve steady-state current balance with adequate accuracy; however, their

dynamic performance has not been clearly explored and compared. On the other hand, the

dynamic current sharing performance is very important in terms of system reliability, since

the overshoots and oscillations during transients could put a lot of stress on the

components. Therefore, it is the objective of this dissertation to study the dynamic current

sharing performance of a paralleling system under both low and high-frequency transients,

to improve the system’s feedback control design.

209

Juanjuan Sun Chapter 5. Conclusions

In the studying of dynamic current sharing performance with active current sharing

control schemes, the output impedance concept has been used through the whole research.

As a transfer function representing the small-signal terminal characteristic of a switching

converter, output impedance allows us to focus on the output performance of a system.

Under low-frequency load perturbations, conventional output impedances are adequate to

predict a paralleling system’s dynamic current sharing performance. However, with active

current sharing control schemes, the original output impedances of individual power

converters are modified, just as shown in Figure 5.1.

Zcs1+

-

Module #1

Module #2

Zcs2

oi

ov

2oi

1oi Zcso

LoadZo1

Δio

CS bus CS

control

Zo2

Figure 5.1. Output impedances of the paralleled modules.

It is found the difference of each module’s output impedance dominates the output

currents’ response during load transients. When there is no active current sharing control,

because of significant difference of Zo1 and Zo2, there exist large oscillations in the output

currents, which lead to over current condition in converters. To improve the dynamic

current sharing response, as well as ensure the steady-state current sharing accuracy, active

210


current sharing controls can be utilized to reduce the difference between output

impedances. There are three kinds of active current sharing structures; all of them function

in a way so that the output impedances of paralleled modules can be pulled to match with

each other. However, the benefit of active current feedback control can only be achieved

inside the current sharing loop’s bandwidth. Because of different implementations, outer-

loop, inner-loop and dual-loop schemes have different ability to increase the current

sharing loop’s bandwidth. Among them, outer-loop control has the strongest limitation,

while inner-loop and dual-loop structures provide the possibility of increasing Tcs’s

bandwidth beyond that of the voltage feedback loop. Table 5.1 shows the comparison

among three active current sharing schemes.

Table 5.1. Comparison of three active current sharing structures.

Outer-loop Dual-loop Inner-loop

Δz and Tcs Δz is attenuated by Tcs

Current sharing loop bandwidth Slow Flexible Fast

Interference between loops Minor Possible Minor

Noise immunity Moderate Poor Good

Applications Limited transients With stringent

transients

With stringent

transients

It is concluded in Chapter 2 that:

211


• The dynamic current sharing performance is improved inside the current sharing

loop bandwidth for all three control structures;

• The inner-loop and dual-loop schemes can achieve higher Tcs gain and

bandwidths than outer-loop structure;

• For dual-loop scheme, there is possibility of interaction between the voltage

regulation loop and the current sharing loop; therefore, it is recommended to not

design the current sharing loop to have similar bandwidth as that of the voltage

loop’s;

• The dynamic voltage regulation is impacted due to the current sharing control for

all three structures; however, with combination of the current control loop, the

inner-loop scheme has more flexibility to design a desired voltage feedback loop

and total output impedance;

• With faster current sharing loop design, the dual loop’s noise immunity is poor.

However, combined with the current loop, the inner-loop control has very good

noise immunity because the current loop also has the function of attenuating the

noise;

• Therefore, inner-loop is a better choice considering both dynamic current sharing

and voltage regulation performance.

While the traditional modeling technique can handle the dynamic current sharing

analyses for low-frequency perturbations, it is not valid when the perturbation frequency is

close or higher than half of the switching frequency. However, the need of high-frequency

dynamic current sharing also exists in reality. For example, the repetitive load transient

212


frequency can be close to or higher than the switching frequency for multiphase

interleaved VRs. Meanwhile, it is necessary to maintain balanced current among paralleled

phases under all kinds of transients.

With high-frequency load transients, a very special phenomenon has been observed:

large-magnitude beat-frequency oscillations occur in the phase currents when the load

transient frequency is approaching to or higher than the switching frequency. This is a

severe issue that can lead to failure of the whole VR system, especially as the speed of the

microprocessor keeps increasing. Yet this issue has not been widely recognized and there

is lack of research to help designers to understand and solve the issue.

)(1

)()(1

fpo

fpofpcs i

vZ −=

)(

)()(

fpo

fpofpcso i

vZ −=

)(1

)()(1

fpfso

fpofpfs i

vX

−− −=

)(2

)()(2

fpo

fpofpcs i

vZ −=

)(2

)()(2

fpfso

fpofpfs i

vX

−− −=

Figure 5.2. Output impedance concept is expanded for beat-frequency studies.

However, the conventional output impedance concept is no longer suitable for this

analysis with high-frequency perturbations, because it does not include any information of

the beat-frequency components. Therefore, to understand and study the beat-frequency

related high-frequency dynamic current sharing issue, Chapter 3 explores a similar concept

213


by representing terminal characteristics with extended describing functions. Figure 5.2

demonstrates this approach of using extended describing functions to evaluate the beat-

frequency current sharing issue. The extended describing functions X1 and X2 are defined

to represent the terminal characteristics for different frequency-components. Thus, the

current sharing error at beat-frequency as the response of high-frequency load transient can

also be derived. Again, it is found that the beat-frequency dynamic current sharing error is

determined by the difference of “impedances” which have the form of extended describing

functions. However, one difference between X and the conventional output impedance is:

X1 and X2 are negative to each other due to interleaving operation. This means their

difference is actually the sum of their magnitudes. Because of this, the beat-frequency

current sharing error could be very large even with same magnitude curves of X1 and X2.

In order to obtain the expressions of X1 and X2, Chapter 3 utilized the multi-

frequency model, which incorporates the information of beat-frequency components. The

key of this model is the nonlinear PWM function. Chapter 3 derived the PWM model for

current mode controlled buck VRs mathematically and then developed the complete

model. The findings in Chapter 3 are summarized as following:

• When the beat-frequency component falling into low-frequency range, the low-

pass filter of the power stage can no longer effectively attenuate its magnitude;

• For single-phase VRs, beat-frequency oscillation is usually not severe due to

attenuation from both voltage and current feedback loops;

• However, there exists cancellation effect in the beat-frequency component of

output voltage for multi-phase interleaved VRs; therefore, the only loop gain that

can reduce beat-frequency oscillation in each phase’s current is the current

214


feedback loop gain; this makes the beat-frequency oscillation issue much severe

for multi-phase VRs than that of single-phase VRs;

• The multi-frequency model is derived for current mode controlled VRs so that

terminal characteristics such as X1 and X2 can be obtained;

• Based on the proposed model, the magnitude of beat-frequency oscillation is

predicted and verified;

• To resolve the conflict between dynamic current sharing and voltage regulation

performance, several solutions such as notch filter and coupled inductor have

been proposed for high-performance VR systems.

Moreover, Chapter 4 generalized the beat-frequency related study by including

higher-order beat-frequency components in an N-phase interleaved VR. It is concluded that

the overall output-impedance is very important in determining the magnitude of higher-

order beat-frequency oscillations. Furthermore, it is found that if the load transient

frequency is close to N times of the switching frequency, the beat-frequency oscillations

become much smaller because of additional attenuations from the voltage feedback loop.

In summary, by utilizing the output impedance concept and its extension in the form

of extended describing function, the dynamic current sharing performance can be

conveniently evaluated for both low-frequency and high-frequency transients. Other than

that, the voltage regulation performance can also be studied based on impedance concept.

Thus, the objective of this work, which is studying dynamic current sharing response and

its impact on the voltage regulation performance of paralleling systems for both low-

frequency and high-frequency dynamics, is achieved by the impedance approach.

215


5.2 Future Works

The study of dynamic current sharing performance in this dissertation shows that

there is always a tradeoff between the dynamic voltage regulation and current sharing

responses, no matter the transient is low-frequency or high-frequency. Therefore, it would

be very useful if one can provide a solution to avoid this conflict. The inversely coupled

inductor has been demonstrated a very promising method to solve this issue for multiphase

interleaved VRs with current mode control. It will be very interesting to investigate the

benefit of this concept under other applications.

One interesting phenomenon addressed in this work is the beat-frequency oscillation.

The beat-frequency phenomenon can be observed in many different applications that have

nonlinear modulation functions [65][66]. It may result in detrimental influences under

certain conditions. Therefore, it will be very exciting if the multi-frequency modeling

concept can be extended and proven useful for those studies.

216

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Vita

The author, Juanjuan Sun, was born in Shaoyang, China, in 1978. She received her

Bachelor and Master degrees in Electrical Engineering from Tsinghua University, Beijing,

China, in 1999 and 2001, respectively.

Since spring 2002, the author has been working toward the Ph.D. degree in the

Center for Power Electronics Systems (CPES) at Virginia Polytechnic Institute and State

University, Blacksburg, Virginia. Her research interests include modeling and control of

switching converters, high-frequency power conversion, low-voltage high-current

conversion techniques, and distributed power systems.

225

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