DW8051 MacroCell Application Notes - search...

DesignWare MacroCellsDW8051

August 5, 2004

DW8051 MacroCell Application Notes

Copyright Notice and Proprietary InformationCopyright 2004 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

Destination Control StatementAll technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them.

DisclaimerSYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

Registered Trademarks (®)Synopsys, AMPS, Arcadia, C Level Design, C2HDL, C2V, C2VHDL, Cadabra, Calaveras Algorithm, CATS, COSSAP, CSim, DelayMill, Design Compiler, DesignPower, DesignWare, EPIC, Formality, HSPICE, Hypermodel, I, iN-Phase, InSpecs, in-Sync, Leda, MAST, Meta, Meta-Software, ModelAccess, ModelTools, NanoSim, OpenVera, PathMill, Photolynx, Physical Compiler, PowerMill, PrimeTime, RailMill, Raphael, RapidScript, Saber, SiVL, SmartLogic, SNUG, SolvNet, Stream Driven Simulator, Superlog, System Compiler, Testify, TetraMAX, TimeMill, TMA, VCS, Vera, and Virtual Stepper are registered trademarks of Synopsys, Inc.

Trademarks (™)abraCAD, abraMAP, Active Parasitics, AFGen, Apollo, Apollo II, Apollo-DPII, Apollo-GA, ApolloGAII, Astro, Astro-Rail, Astro-Xtalk, Aurora, AvanTestchip, AvanWaves, BCView, Behavioral Compiler, BOA, BRT, Cedar, ChipPlanner, Circuit Analysis, Columbia, Columbia-CE, Comet 3D, Cosmos, CosmosEnterprise, CosmosLE, CosmosScope, CosmosSE, Cyclelink, Davinci, DC Expert, DC Expert Plus, DC Professional, DC Ultra, DC Ultra Plus, Design Advisor, Design Analyzer, Design Vision, DesignerHDL, DesignTime, DFM-Workbench, DFT Compiler, Direct RTL, Direct Silicon Access, DW8051, DWPCI, Dynamic-Macromodeling, Dynamic Model Switcher, ECL Compiler, ECO Compiler, EDAnavigator, Encore, Encore PQ, Evaccess, ExpressModel, Floorplan Manager, Formal Model Checker, FoundryModel, FPGA Compiler II, FPGA Express, Frame Compiler, Galaxy, Gatran, HDL Advisor, HDL Compiler, Hercules, Hercules-Explorer, Hercules-II, Hierarchical Optimization Technology, High Performance Option, HotPlace, HSPICE-Link, iN-Tandem, Integrator, Interactive Waveform Viewer, i-Virtual Stepper, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, JVXtreme, Liberty, Libra-Passport, Library Compiler, Libra-Visa, LRC, Magellan, Mars, Mars-Rail, Mars-Xtalk, Medici, Metacapture, Metacircuit, Metamanager, Metamixsim, Milkyway, ModelSource, Module Compiler, MS-3200, MS-3400, Nova Product Family, Nova-ExploreRTL, Nova-Trans, Nova-VeriLint, Nova-VHDLlint, Optimum Silicon, Orion_ec, Parasitic View, Passport, Planet, Planet-PL, Planet-RTL, Polaris, Polaris-CBS, Polaris-MT, Power Compiler, PowerCODE, PowerGate, ProFPGA, Progen, Prospector, Proteus OPC, Protocol Compiler, PSMGen, Raphael-NES, RoadRunner, RTL Analyzer, Saturn, ScanBand, Schematic Compiler, Scirocco, Scirocco-i, Shadow Debugger, Silicon Blueprint, Silicon Early Access, SinglePass-SoC, Smart Extraction, SmartLicense, SmartModel Library, Softwire, Source-Level Design, Star, Star-DC, Star-MS, Star-MTB, Star-Power, Star-Rail, Star-RC, Star-RCXT, Star-Sim, Star-SimXT, Star-Time, Star-XP, SWIFT, Taurus, Taurus-Device, Taurus-Layout, Taurus-Lithography, Taurus-OPC, Taurus-Process, Taurus-Topography, Taurus-Visual, Taurus-Workbench, TimeSlice, TimeTracker, Timing Annotator, TopoPlace, TopoRoute, Trace-On-Demand, True-Hspice, TSUPREM-4, TymeWare, VCS Express, VCSi, Venus, Verification Portal, VFormal, VHDL Compiler, VHDL System Simulator, VirSim, and VMC are trademarks of Synopsys, Inc.

Service Marks (SM)MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.

SystemC is a trademark of the Open SystemC Initiative and is used under license.AMBA is a trademark of ARM Limited. ARM is a registered trademark of ARM Limited.All other product or company names may be trademarks of their respective owners.

2 Synopsys, Inc. August 5, 2004

DW8051 MacroCell Application Notes

August 5, 2004 Synopsys, Inc. 3

DW8051 MacroCell Application Notes Contents

Contents

Chapter 1Quick Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Step-by-Step Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Reloading the Configured Knowledge Base (KB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Software Development Tools for DW8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Adding New Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2Implementing Program Memory Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Implementation Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Synopsys-Supplied Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10The MOVC Inhibit Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Implementing MOVC Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Using the MOVC Inhibit Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Testing the MOVC Inhibit Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 3Designing with the DW8051 MacroCell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Using the DW8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17DW8051 in a Design with I/O Ports Visible at Chip Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19DW8051 I/O Ports Invisible at Chip Pins Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23DW8051 Using Standard I/O Ports that are Invisible at the Chip Pins . . . . . . . . . . . . . . . . . . . . . 24Debugging/Verifying your Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

In-Circuit Emulator Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Debug Monitor Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26


Contents DW8051 MacroCell Application Notes


DW8051 MacroCell Application Notes Chapter 1: Quick Start

1Quick Start

AttentionThis document assumes that you have an installed coreConsultant tool in your environment.

Before starting:

● Ensure your simulator setup is correct.

● For information on system requirements, setting environment variables, installing the DW8051, and creating a workspace, refer to the installation file at DW8051/3.70a/doc/install.txt.

● For details regarding installation directories and files, refer to Appendix C in the DesignWare DW8051 MacroCell Databook.

● In the coreConsultant GUI, use the right mouse button to click on any item to bring up context-sensitive help.

This application note is intended to aid you in going through the DW8051 MacroCell flow. The topics in this document are:

● Step-by-step instructions on how to use the DW8051● Pointers to the documentation on adding your own tests to the test suite● Pointers to the documentation on adding your own peripherals● Pointers to the documentation that are useful while designing with the DW8051

Step-by-Step InstructionsThese instructions describe how to use the DesignWare DW8051. You can exit coreConsultant during any point in your activity list without losing any information that you entered. You can reload the data and continue where you left off at any time.

1. The DW8051 3.70a coreKit is pre-installed.

To install, untar the downloaded file. The installed directory is located at download_dir/DW8051/3.70a.


Chapter 1: Quick Start DW8051 MacroCell Application Notes

2. Invoke the coreConsultant as follows:

% coreConsultant &

Enter the path and name of your workspace, and also enter the installed coreKit path. Click OK to create a new workspace.

3. After creating a new workspace, the Consultant Activity List appears. The Configure window appears, in which you should specify the required configuration by modifying different parameters.

NoteYou cannot proceed with the activities in the other two tabs before completing this step.

4. If you are using a non-Synopsys simulation tool, click Generate GTECH Model in the Create GTECH Simulation Model activity and select the options to generate the GTECH netlist. Then go to the Verify Component Activity. If you are using Synopsys tools, you can directly go to the Verify Component Activity and the go to step 5.

If you have a DW8051 source license, you do not need to generate a GTECH simulation model.

5. Click on the Simulator list item and select the simulator of your choice.

6. Click the View list item and choose between RTL and GTECH as appropriate for your simulator.

7. Click Execution Options in the list and select the options to launch the simulation.

8. Click the two Select Testsuite list items to select any or all of the tests from the test suite. Click Apply to run the simulation.

Results are displayed in the coreConsultant window.

9. Click the Specify Target Technology activity; a tools installation paths appears. Specify your $SYNOPSYS variable and, if necessary, provide paths for your technology library.

10. Click the Specify Clocks activity and provide a clock name and period.

11. Click Specify Operating Conditions to provide the appropriate values.

12. Click Specify Port Constraints to provide input/output constraints; default values are best.

13. Click the Specify Synthesis Methodology activity and provide common/advanced synthesis strategy attributes.

14. Click the Synthesize activity and select appropriate strategy and options for the synthesis run.

15. Click Apply to run the synthesis; results are displayed in the coreConsultant window. For more details, check the workspace/syn directory.

Reloading the Configured Knowledge Base (KB)You can save the information in your workspace at anytime and continue at a later time. To do this, reload the configured KB to invoke the coreConsultant by using the following command:

coreConsultant workspace

For more details regarding command line options, refer to the coreConsultant User Guide.


DW8051 MacroCell Application Notes Chapter 1: Quick Start

Software Development Tools for DW8051The DW8051 testbench accepts test cases in assembly. If you would like to write your test cases in a higher-level language such as C, you can use any of the commercially available software development tools – such as the “C51 Compiler” from Keil Software – to compile and assemble your code. The assembly-level code can then be included in the DW8051 testbench.

For more information on Keil Software development tools, visit http://www.keil.com. Other vendors are located at www.nohau.com and www.hitex.com.

Adding New TestsYou can extend the testbench to test user-defined peripherals connected to the DW8051_core by incorporating the peripherals into the testbench and writing test programs for the peripherals. For more details on how to make use of the testbench features to write test programs, refer to “Creating and Executing Custom Tests” in the DesignWare DW8051 MacroCell Databook.

http://www.keil.com

www.nohau.com

www.hitex.com


Chapter 1: Quick Start DW8051 MacroCell Application Notes


DW8051 MacroCell Application Notes Chapter 2: Implementing Program Memory Security

2Implementing Program Memory Security

This application note describes how to modify the DW8051 MacroCell to implement on-chip program memory security. Implementation of this feature prevents externally stored programs from reading the contents of on-chip program memory.

The DW8051 implementation of program memory security is similar to the “MOVC inhibit” function used in the Intel 8751. The DW8051 MOVC inhibit feature provides one level of security to protect on-chip program memory. When enabled, the MOVC inhibit feature prevents MOVC instructions that are executed from off-chip “external” memory from fetching data out of on-chip memory.

The MOVC inhibit feature, as described in this application note, has been tested successfully with the existing DW8051 test suite. If you implement the MOVC inhibit feature as described in this application note, you must also test the implementation with your own design and test suite.

Implementation OverviewThe DW8051 MOVC inhibit feature adds a new input pin (MOVC_inhibit) to DW8051_core. When MOVC_inhibit is asserted, MOVC instructions executing from off-chip memory are disabled from fetching code out of on-chip program memory.

The basic procedure to implement MOVC_inhibit is:

1. Rename your existing DW8051_core to DW8051_core_enhanced and modify DW8051_core_enhanced as follows:

❍ Add two new top-level output ports: PC and rom_data_read

❍ Connect the DW8051_cpu internal pc signal to the new PC port of DW8051_core_enhanced

❍ Connect the DW8051_cpu internal biu_rd_rom signal to the new rom_data_read port of DW8051_core_enhanced

2. Instantiate DW8051_core_enhanced in the new DW8051_core.

Synopsys supplies the source code for the new DW8051_core. The features of the new DW8051_core are:

❍ Instantiates DW8051_core_enhanced

❍ Includes additional logic that implements the MOVC inhibit functionality


Chapter 2: Implementing Program Memory Security DW8051 MacroCell Application Notes

❍ Matches the pinout of the original DW8051_core with one additional input pin, MOVC_inhibit

3. Test your implementation of the MOVC inhibit feature, using the Synopsys-supplied test program.

Synopsys-Supplied FilesIn addition to this application note, Synopsys supplies the following files to help you implement the MOVC inhibit feature:

● DW8051_core.v – Modified version of the original DW8051_core that instantiates your DW8051_core_enhanced

● Test programs for the MOVC inhibit feature:

❍ op_movc_ext.a51.unx❍ op_movc_ext.lst❍ op_movc_ext.hex

The MOVC Inhibit LogicThe MOVC inhibit logic provides the following functions:

● Latches the mem_ea_n input whenever the rst_out_n signal is de-asserted. The latched signal is called latched_ea_n

● Implements the locking function – logic that uses the values of the PC, rom_data_read, latched_ea_n, and MOVC_inhibit signals to control the internal ROM read signal (irom_rd_n) that is generated by DW8051_core (in this case, by the instantiated DW8051_core_enhanced)

In other words, the MOVC_inhibit (locking) logic conditions the unqualified internal-ROM-read signal (irom_rd_n) from DW8051_core_enhanced and supplies it to the external world as the irom_rd_n output from the new DW8051_core; refer to Figure 1.

Figure 1: MOVC_inhibit Block Diagram

DW8051_core_enhanced

DW8051_core

DW8051_cpu

MOVCInhibitLogic

MOVC_inhibit

i_rom_rd_n



Implementing MOVC InhibitTo implement the MOVC inhibit feature in the Verilog version of the DW8051 MacroCell, perform the following steps;

1. Go to the DW8051 source directory:

% cd dw8051_root/src

2. Create backup copies of the following files (in a separate directory):

DW8051_core.vDW8051_cpu.v

3. Move the DW8051_core.v file to a file called DW8051_core_enhanced.v:

% mv DW8051_core.v DW8051_core_enhanced.v

4. Make the following modifications to the DW8051_cpu.v file:

a. Add two new output ports to DW8051_cpu – PC_out and rom_data_read:

module DW8051_cpu (clk,por_n,rst_in_n,rst_out_n,.............PC_out, //For implementing lockrom_data_read //For implementing lock);

output [15:0] PC_out; //For implementing lockoutput rom_data_read; //For implementing lockwire [15:0] PC_out; //For implementing lockwire rom_data_read; //For implementing lock

b. Assign the new PC_out output port of DW8051_cpu to the pc signal of the DW8051_updn_ctr_16 module instantiated in DW8051_cpu (instance name i_pc):

DW8051_updn_ctr #(16) i_pc(.data (result),.up_dn (pc_cnt_dir),.load (set_pc_n),.cen (inc_pc),.clk (clk),.reset (rst_n),.count (pc),.tercnt (pc_tercnt)); // not used

assign PC_out = pc; //For implementing lock



c. Assign the new rom_data_read output port of DW8051_cpu to the biu_rd_rom signal of the DW8051_biu module instantiated in DW8051_cpu (instance name i_biu):

//--------------------// Bus Interface Unit://--------------------DW8051_biu #(rom_addr_size) i_biu

(.clk (clk),.rst_n (rst_n),.cycle (t_cycle),.ea_n (mem_ea_n),.stop_mode_n (t_stop_mode_n),...................int_rom_data_in (int_rom_data_in),.int_rom_rd_n (int_rom_rd_n),.int_rom_cs_n (int_rom_cs_n));

assign rom_data_read = biu_rd_rom; //For implementing lock

5. Make the following modifications to the DW8051_core_enhanced.v file:

a. Change the module name from DW8051_core to DW8051_core_enhanced and add two new output ports named PC and rom_data_read to DW8051_core_enhanced:

module DW8051_core_enhanced (clk,por_n,rst_in_n,rst_out_n,...................PC, //For implementing lockrom_data_read //For implementing lock);

output [15:0] PC; //For implementing lockoutput rom_data_read; //For implementing lock

b. Modify the instance of DW8051_cpu (instance i_cpu) to reflect the addition of the two new DW8051_cpu output signals (PC_out and rom_data_read). Then, use wires to connect the PC_out and rom_data_read ports of DW8051_cpu to the PC and rom_data_read ports (respectively) of DW8051_core _enhanced, as shown below:

wire [15:0] PC; //For implementing lockwire rom_data_read; //For implementing lock

//------------------------------// Implementation of CPU kernel://------------------------------DW8051_cpu #(ram_256, rom_addr_size, extd_intr) i_cpu

(.clk (clk),.por_n (por_n),.rst_in_n (rst_in_n),................PC_out (PC), //For implementing lock.rom_data_read (rom_data_read) //For implementing lock

);

6. Install the new Synopsys-supplied version of DW8051_core (DW8051_core.v) in your project directory (dw8051_root/src).



The new DW8051_core.v file instantiates DW8051_core_enhanced, matches the pinout of the original DW8051_core with the addition of the MOVC_inhibit pin, and includes the code that implements the MOVC inhibit feature.

You can now simulate and synthesize the DW8051 MacroCell, with the MOVC inhibit feature, using the procedures in the DesignWare DW8051 MacroCell Databook.

Using the MOVC Inhibit FeatureTo use the MOVC inhibit feature in your application, assert the MOVC_inhibit pin. This will disable MOVC instructions executing from external ROM from reading contents of the internal ROM.

Figure 2 shows the timing for an internal ROM access with MOVC_inhibit de-asserted. The low on MOVC_inhibit enables the assertion of irom_rd_n when unqualified_irom_rd_n is asserted.

Figure 2: MOVC_inhibit De-asserted

1fff

clk

max_introm_addr[15:0]

mem_addr[15:0]

mem_ale

mem_data_in[7:0]

mem_data_out[7:0]

mem_ea_n

mem_psrd_n

mem_pswr_n

mem_rd_n

mem_wr_n

MOVC_inhibit

PC[15:0]

por_n

rst_in_n

rst_out_n

rom_data_read

irom_rd_n

irom_data_out[7:0]

irom_addr[15:0]

unqualified_irom_rd_n

0080902990299028 902a 902b 902c

a31d5500b4b493

cc cc cc

9028 9029 9029 902a 902b 902c

00 00 55 00 00

0080902990299028 902a 902b 902c

1fff 1fff

Internal program memory read enabled



Figure 3 shows the timing for an internal ROM access with MOVC_inhibit asserted. The high on MOVC_inhibit prevents the assertion of irom_rd_n when unqualified_irom_rd_n is asserted.

Figure 3: MOVC_inhibit Asserted

Testing the MOVC Inhibit FeatureThe MOVC inhibit feature has been tested with the existing DW8051 test suite, plus one additional test (op_movc_ext) that covers all possible combinations of internal program memory accesses. To test your implementation of the DW8051 MOVC inhibit feature, perform the following steps:

1. Make a backup copy of the DW8051_core_tb.v file.

2. Make the following changes to DW8051_core_tb.v:

a. Add the MOVC_inhibit signal (for Verilog, use reg). Initialize MOVC_inhibit to 0.

b. Initialize mem_ea_n to 1 (default is 1).

1fff

clk

max_introm_addr[15:0]

mem_addr[15:0]

mem_ale

mem_data_in[7:0]

mem_data_out[7:0]

mem_ea_n

mem_psrd_n

mem_pswr_n

mem_rd_n

mem_wr_n

MOVC_inhibit

PC[15:0]

por_n

rst_in_n

rst_out_n

rom_data_read

irom_rd_n

irom_data_out[7:0]

irom_addr[15:0]

unqualified_irom_rd_n

0080902990299028 902a 902b 902c

a31d55b4b493

cc cc cc

9028 9029 9029 902a 902b 902c

00 00

0080902990299028 902a 902b 902c

1fff

00

Internal program memory read disabled



3. Install the Synopsys-supplied op_movc_ext test program in your dw8051_root/asm_tests directory. The files that Synopsys supplies for the op_movc_ext test are:

❍ op_movc_ext.a51.unx – Assembler source code❍ op_movc_ext.lst – List file generated by assembler❍ op_movc_ext.hex – Intel Hex file generated by Obj-Hex converter

4. Run the op_movc_ext test. Use the simulation procedures in the DesignWare DW8051 MacroCell Databook; the test should pass.

5. In the DW8051_core_tb.v file, initialize MOVC_inhibit to 0 and mem_ea_n to 0.

6. Run the op_movc_ext test again; the test should pass.


8. Run the op_movc_ext test again; the test should pass.


10. Run the op_movc_ext test; the test should fail. The testbench will return the following message:

---Error in test case detected!


DW8051 MacroCell Application Notes Chapter 3: Designing with the DW8051 MacroCell

3Designing with the DW8051 MacroCell

This application note describes the DW8051 MacroCell design process, from design specification to design layout. It includes methods for testing the microcontroller once you obtain your silicon. See Figure 4 on page 18 for a flow chart describing the overall steps in designing with the DW8051 MacroCell.

Using the DW8051There are three ways the DW8051 is used in a design:

● The DW8051 ports are visible at the chip pins (either in a standard 40-pin package or a custom package)

● The DW8051 ports are invisible at the chip pins

● The DW8051 with standard I/O ports is deeply embedded in a design

A detailed design flow for when the I/O ports are visible at the chip pins is described in “DW8051 in a Design with I/O Ports Visible at Chip Pins” on page 19. The description for the design where the ports are invisible at the chip pins is in “DW8051 I/O Ports Invisible at Chip Pins Design” on page 23.


Chapter 3: Designing with the DW8051 MacroCell DW8051 MacroCell Application Notes

Figure 4: Designing with the DW8051 - Design Flow Chart

Write the product specification

Partition design into modules.

Create new verification tests for

Code and test modules in RTL

Create black box timing

Combine RTL files for synthesis step

Perform static timing analysis.

Generate block definitions

the Product specification.

synthesis strategy).

and get it approved.

for the modules.

all aspects of chip based on

(perform functional verification).

models for non-RTL blocks.

(after determining appropriate

Test resultssatisfactory?

Test gate-level netlist back-

Send netlist to place and route 1.

1. Take care while writing out the netlist, to make sure the netlist format

verilogout_no_tri, and verilogout_singlebit variables to true.

Generate back-annotated database

Check post place and route

2. Read the netlist, with post place and route timing, into the Design

Compiler. Check for all constraints; use in place optimization with

appropriate switches if there are any violations.

Check for functional correctness with

maximum, mid-range and minimum

Send netlist to fab.

is accepted by the place and route tool. For example, it is safe to set

annotated with SDF information.

from place and route tool.

post place and route timing at

clock frequencies.

Dynamic timing requirements met?

netlist for static timing 2.

yes

no

no

yes



DW8051 in a Design with I/O Ports Visible at Chip PinsThis method can be used for a standard 40-pin design, or for a custom design with as few or as many pins as required.

The following design flow description considers a design with custom peripherals integrated into the DW8051, and a standard 40-pin pinout.

1. Write the product specification; once it is approved, you must determine:

❍ Number of peripherals (timers, serial ports, interrupts)

❍ Amount of internal RAM and ROM to be implemented in the DW8051

For details on configuring the DW8051, refer to “Specifying Your Configuration” in the DesignWare DW8051 MacroCell Databook.

For details on how to implement, simulate and interface internal RAM and ROM, refer to the “Interfacing to Internal RAM,” “Simulating Internal RAM,” “Interfacing to Internal ROM,” and “Simulating Internal ROM” sections in the DesignWare DW8051 MacroCell Databook.

It is important to budget for internal RAM or ROM blocks during synthesis. Use the timing information provided by the block vendor.

2. Design your custom peripherals.

The DW8051 provides two ways to integrate custom peripherals:

a. Interface to the SFR bus

b. Interface to the memory bus

Determine your peripheral interface with the DW8051 before actually designing it; this establishes the custom peripheral pinout.

3. Test the custom design.

Test the custom design in standalone mode before integrating it into your design. After integrating the custom peripherals into the DW8051:

a. Write tests in assembly language

b. Add the tests to the existing test suite

c. Run the entire suite

For details on integrating new tests into the test suite, refer to “Creating and Executing Custom Tests” in the DesignWare DW8051 MacroCell Databook.

Either write the tests in “C” and use a commercial compiler to convert it into assembly format, or write the tests directly in assembly format. Once the tests are in assembly format, they must be converted to Intel hex format; use standard assemblers available in the public domain. DesignWare recommends the freeware as8051 assembler; the syntax for converting assembly programs into hex format using the as8051 assembler is:

as8051 -l test.lst -o test.hex test.unx

The Verilog testbench requires tests be in Verilog memory format. The “asm_tests” directory has a Perl script called ihex2mem.pl, which converts Intel hex files into Verilog memory format. The syntax for using the ihex2mem.pl script is:

ihex2mem.pl test.hex test.mem



4. Create port control logic.

Create port control logic to combine the DW8051 pinout into a standard 40-pin format. The “example” directory provides examples of port control logic for the four ports, and it also contains a top-level module which instantiates the DW8051 and port control logic.

Figure 5 shows a schematic of the various blocks and the suggested hierarchy for designing a 40-pin chip using the DW8051 MacroCell.

Figure 5: DW8051 with I/O Ports Visible at Chip Pins

The exploded schematic of port0 shows individual connections between the port control logic and the pads. We recommend selecting the appropriate I/O cells to be used for the pads, and instantiate these cells in the port modules. To help you select I/O pads, refer to the manual of the chip you are building for detailed specifications. For example, if building an Intel 8032 chip, refer to the Intel 8032 manual.

InternalRAMBlack Box

InternalROMBlack Box

DW8051.db

Port1_cnt.v

Port2_cnt.v

Port3_cnt.v

p0[0]

p0[1]

p0[7]

p0[6]

p0[2]

p0[3]

p0[4]

p0[5]

Port0_cnt.v

Port0_cnt.v

p0[7]p0_data_out[7]

p0_data_in[7]

ena_obug[7]

my_peripheral.v



5. Synthesize the design.

Perform synthesis after verifying the entire design. There are two design synthesis methods:

❍ Synthesize the DW8051 core and use the .db file while integrating the complete design.

❍ Simultaneously synthesize the complete design, including the DW8051 core. This approach is not recommended because you will not be able to take advantage of the automatic synthesis script generation technology feature of the coreConsultant.

To synthesize the DW8051 core:

❍ Generate the gate-level netlist mapped to your desired technology library by following the steps outlined in “Quick Start” on page 5.

❍ Make use of the example test insertion script available in the DW8051_core/scan_chain_example directory for guidance during manufacturing test insertion (if manufacturing test is required). Ideally, test insertion is done at the top level only after you integrate your design.

After obtaining the gate-level netlist, verify it using the provided test suite. It is recommended that you constrain the DW8051 core to at least 10-15% faster than the maximum operating frequency of your design upon insertion of the ports.

6. Integrate the complete design.

Once the DW8051 is synthesized, create a dc_shell script to read in the top level of the design and:

a. Instantiate port control logic and custom peripherals

b. Set the clock frequency

c. Include timing models for black box modules

d. Implement compile strategy

By default, the DW8051 core netlist has a dont_touch attribute placed on it. Removing the dont_touch attribute on the DW8051 core and compiling the complete design provides the best quality – in terms of both timing and area – but results in a compile-time penalty.



The following is an example dc_script:

verilogout_single_bit = true /*to split busses*/bus_naming_style = %s_%d /*or the bus naming styleaccepted by your place androute tool */read -format db {“DW8051_core.db”} /*DW8051 core gate-levelnetlist*/read -f verilog por_n.v /*blackbox for power onreset circuitry*/read -f verilog port0.v /*Instantiated IO cells*/read -f verilog port0_cnt.v /*control logic for port0*/read -f verilog port1.v /*Instantiated IO cells*/read -f verilog port1_cnt.v /*control logic for port1*/read -f verilog port2_new.v /*Instantiated IO cells*/read -f verilog port2_cnt.v /*control logic for port2*/read -f verilog port3_new.v /*Instantiated IO cells*/read -f verilog port3_cnt.v /*control logic for port3*/read -f verilog my_perip.v /*your custom designedperipheral*/read -f verilog top.v /*Top level of your design*/linkset_operating_conditions “my_operating_conditions”create_clock -name “clk” -period 16 -waveform { “0” “8”}{“clk”}set_dont_touch_network find( clock, “clk”) /*Important*/set_drive 0 clkremove_attribute find(design,“DW8051_core.db:DW8051_core_1_0_0_1_0”) dont_touch/* Recommended for betterQoR*/report_constraints -all_violators> constraints.out/*constraints report*/ungroup -all /*choose your own compilestrategy*/set_flatten -effort high /*choose your own compilestrategy*/uniquify /*choose your own compilestrategy*/compilecurrent_design = s8031linkcompile -incremental -map_effort high /*if necessary*/write -hier -output my_top_design.dbwrite -f verilog -hierarchy -output my_top_design.vwrite_timing -f sdf -context verilog -o my_top_design.sdfreport_timing > my_top_design.outreport_area >> my_top_design.out

NoteThis is an example script; you may choose a different compile strategy. Your script must include timing models and constraints for custom peripherals and RAM/ROM cells.

7. Perform static timing analysis; when the test results are satisfactory, obtain the netlist.



8. Test the gate-level netlist:

❍ Verify it for functional correctness, zero timing, and ideal clock analysis (and/or use compare design commands in dc_shell)

❍ Check to see if any constraints have been violated.

9. Send the netlist to place and route.

10. Generate back-annotated database from the place-and-route tool.

11. Check the post place-and-route netlist for static timing:

❍ Read the propagated clock analysis post place-and-route netlist back into Design Compiler with the timing information, and check for constraint violations.

❍ If there are violations, do in-place optimization with the appropriate switches.

12. Verify the netlist for functional correctness at different operating frequencies – for example, maximum, mid-range, and minimum clock frequencies. Perform a dynamic timing test on fully annotated netlist physical analysis, PowerMill, TimeMill, DRC, LVS, and so on.

13. Tape out.

DW8051 I/O Ports Invisible at Chip Pins DesignThere are no I/O ports visible at the chip pins when the DW8051 is deeply embedded; this means that you must decide during the design phase whether or not emulator support is needed. Usually, emulator support requires approximately 19 pins; contact your emulator vendor to get this information. Nohau Inc., one of the leading suppliers of emulators, supports the DW8051 MacroCell; visit http://www.nohau.com for more information.

The steps for a DW8051 design where the I/O ports are invisible at the chip pins are similar to those for a design where the ports are visible; refer to “DW8051 in a Design with I/O Ports Visible at Chip Pins” on page 19. The only difference is that the custom logic interfaces with the DW8051 core instead of with the ports. Figure 6 provides a schematic scenario for I/O ports that are invisible at the chip pins in a DW8051design.

Figure 6: DW8051 Where I/O Ports are Invisible at the Chip Pins

DW8051.db

my_asic4.v

my_asic3.v

my_asic2.v

my_asic1.v

IO_cells.v top.v

http://www.nohau.com



DesignWare recommends synthesizing the DW8051 core, then using the gate-level netlist for complete design synthesis. A sample synthesis script is shown below:

verilogout_single_bit = true /*to split busses*/bus_naming_style = %s_%d /*or the bus namingstyle accepted by yourplace and route tool */read -format db{“DW8051_core.db”} /*DW8051 coregate-level netlist*/read -f verilog my_asic1.v /*Your custom design*/read -f verilog my_asic2.v /*Your custom design*/read -f verilog my_asic3.v /*Your custom design*/read -f verilog my_asic4.v /*Your custom design*/read -f verilog top.v /*Top level of yourdesign*/linkset_operating_conditions “my_operating_conditions”create_clock -name “clk” -period 16 -waveform { “0”“8”} {“clk”}set_dont_touch_network find(clock, “clk”) /*Important*/set_drive 0 clkremove_attribute find(design,“DW8051_core.db:DW8051_core_1_0_0_1_0”)dont_touch /*Recommended forbetter QoR*/compile /* choose your owncompile strategy*/write -hier -output my_top_design.dbwrite -f verilog -hierarchy -output my_top_design.vwrite_timing -f sdf -context verilog -omy_top_design.sdfreport_timing > my_top_design.outreport_area >> my_top_design.outreport_constraints -all_violators> constraints.out/*constraints report*/

NoteThe script above is an example; you may use a different compile strategy. However, the script must include timing models and constraints for custom designs and RAM/ROM cells.

After obtaining the gate-level netlist, follow the steps described in“DW8051 in a Design with I/O Ports Visible at Chip Pins” on page 19 for final tape out.

DW8051 Using Standard I/O Ports that are Invisible at the Chip Pins

Sometimes it is necessary to include standard I/O ports and port control logic even in applications where the DW8051 is deeply embedded; that is, where none of the DW8051 ports are visible at the chip pins. One good reason for doing this is the ability to use existing application software that make use of the standard I/O ports.



For such a design, you must synthesize the DW8051 core along with the port control logic as described in “DW8051 in a Design with I/O Ports Visible at Chip Pins” on page 19. Use the resulting netlist in your synthesis scripts as described in “DW8051 I/O Ports Invisible at Chip Pins Design” on page 23.

Debugging/Verifying your SiliconThere are two methods of testing your silicon:

● In-circuit emulator● Debug monitor

In-Circuit Emulator Method1. Connect an ICE to the chip; for example, Nohau.

2. Design the ASIC with a dedicated pin that places it into ICE mode. When the ICE pin is activated, the DW8051 is placed in a reset state. The external address bus is tristated and forced to an input mode.

3. Use the external address, connected to the address output from the ICE, to drive the internal address bus of the chip.

4. Handle the external data bus similar to step 3. Connect the data bus from the ICE to the ASIC external data bus pins. The ASIC data bus pins are normally set to input mode, except when the ICE is reading a memory address that is mapped inside the ASIC. At this point, the ASIC drives the external bus when the RD line is activated. This scenario implies that a different control mechanism should be used for the data bus tri-state drivers when the chip is used in ICE mode, as opposed to normal operation.

5. Input the control lines (RD and WR) to the ASIC during ICE mode. You can replicate ports 1 and 3 of the normal 80C320. During ICE mode, these pins are tristated and connected directly to the corresponding pins of the ICE. Use pins P3.6 and P3.7, which have the alternate function of RD and WR to input the RD and WR signals from the ICE.

When building hardware for ICE support, ensure the data bus is in the right state (input or output) at the correct time. To simulate the entire setup in your testbench, instantiate another DW8051 and configure it like an external ICE. This allows verification of ASIC operation in ICE mode with a simulated external processor.

NoteIf you have built new functions based on SFR registers, it will not be possible to duplicate this with the ICE. Consult your ICE vendor for ICE support.

6. Map all ASIC logic to the DW8051 XDATA space. This ensures a standard ICE will access the registers.

For more details on Nohau emulators, visit http://www.nohau.com.

http://www.nohau.com



Debug Monitor MethodIn this method, there is no emulation; instead, the user code is run on the target chip at full speed. This provides 90% of the functionality of the In-Circuit-Emulator method (refer to “In-Circuit Emulator Method” on page 25) without many of the concerns (such as requiring a socketed part and development pod). The “missing” 10% functionality is trace, which is a high-cost option for most ICEs.

Trace is useful for debugging systems, making heavy use of interrupts. However, breakpoints or inserted code can be used to toggle I/O pins specifically for debug. For example, you can program an I/O pin to drive HIGH when an ISR is entered and LOW when exited, then view it on a logic analyzer.

Use an 8051 software development kit (Keil’s for example) and work with the vendor to port their debug monitor to your board.

NoteKeil’s Windows SDK is an integrated system that compiles C and assembly language code. It includes a software simulator and hardware debugger that work in conjunction with the board once the debug monitor has been downloaded, as described above. The program communicates with the development board using a standard serial port. This is a benefit of having both serial ports in the core; one port is used for debug, the other port is available for the user application. For more information on Keil Software tools, visit http://www.keil.com.

Code can be modified, recompiled, downloaded, and run in a manner similar to an ICE. Then set breakpoints, single step, and inspect and change registers/memory locations, and so on, in a manner similar to an ICE.

However, the only difference is trace. One suggestion is to connect a logic analyzer to the 8051 address and data buses, which allows storage of a record of 8051 memory cycles. Make the expansion connectors on the development board pin-compatible with a popular HP logic-analyzer pod to avoid dozens of tiny clips.

It is suggested that you bring out the ALE signal for debug. If the address and data buses are non-multiplexed, the ALE is not needed. If there is a requirement to trace 8051 bus cycles with a logic analyzer, this signal would be available for synchronizing the 8051 cycles.

An advantage to the Debug Monitor Method is that the 8051 clock speed can be increased, without concern that the “ICE” tools will not keep up. The debug monitor always runs at full speed, since it is 8051 code.

http://www.keil.com

DW8051 MacroCell Application Notes - search...

Documents

Transcript of DW8051 MacroCell Application Notes - search...