Nov. 9, 20041 Lecture 6: Dynamic Scheduling with Scoreboarding and Tomasulo Algorithm (Section 2.4)
DVClub Advanced Scoreboarding Techniques-Francois
description
Transcript of DVClub Advanced Scoreboarding Techniques-Francois
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Advanced Scoreboard Techniques using UVM
Franois Cerisier Test and Verification Solutions
DVClub 9th Sept 2013
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DVClub Sept 9th 2013 - Advanced Scoreboard Techniques using UVM Franois Cerisier page 2
Abstract
Abstract This presentation describes scoreboarding techniques using UVM. It reviews the scoreboard principles and UVM features for scoreboarding and extends to more advanced techniques to verify full transaction contents, data, attributes and responses for data flow designs, bridges and interconnects. The presentation will go through the analysis_port requirements, search in lists, queues and pools and using the UVM factory to architect a generic scoreboard for complex multi protocol interconnects.
Biography Franois Cerisier has an Engineering Diploma in Digital Signal Processing from PolytechSophia, University of Nice-Sophia-Antipolis and over 13 years of experience in verification of IPs, CPUs and System-On-Chips and in hardware/software co-verification. Franois gained verification methodology expertise from industrial projects of major semiconductor companies (including Infineon, Broadcom, ST-Microelectronics, ST-Ericsson, NXP) and EDA start-ups. He is now leading Test and Verification Solutions subsidiary in France to provide verification services and consulting.
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Agenda
Introduction Scoreboard Principles
Case 1: Bridge / Data flow design Case 2: More complex data flow design Case 3: Memory controllers
Connecting Scoreboard to Agent analysis_port
Storing and searching for referenced data Pool Queues
Scoreboards for complex designs Requirements for predictor Divide and Conquer Using the UVM Factory
Interconnect Scoreboard Architecture Example Conclusion
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Scoreboard Tutorials
UVM User Guide Quick explanation how to connect a scoreboard
UVM Cookbook, Verification Academy
Straight to the code of a out of order comparator/predictor
Books, Online Materials, UVM Trainings A lot about UVM
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Random Verification Aspects
Verification using Constrained Random Generation : Generation of random test scenarios
Automate tests
Functional Coverage Know what has been automatically covered
Checks
Know that the design complies to a protocol assertions
Know that the design does what it should do
transaction checks scoreboards
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Scoreboard Roles
Check the design is doing what we expect transaction content
Data, address, attributes, opcode, response code
transaction ordering FIFO OOO Precedence relationship
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Data flow design example
DUT
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assertions assertions
Typical UVM testbench
DUT
sequencer
Test
sequences
driver
monitor
vif
vif
driver
monitor
sequences Bus A VIP
Master Agent Bus B VIP
Slave Agent
sequences
monitor monitor
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assertions assertions
Scoreboard principles data flow design
DUT
sequencer
Test
sequences
driver
monitor
vif
vif
driver
monitor
sequences Bus A VIP
Master Agent Bus B VIP
Slave Agent
sequences
trans Ref trans
Match ?
Storage Compare / Search
Scoreboard
Transaction Predictor
Response Scoreboard
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assertions assertions
Scoreboard principles complex data flow design
DUT
sequencer
Test
sequences
driver
monitor
vif
vif
driver
monitor
sequences Bus A VIP
Master Agent Bus B VIP
Slave Agent
sequences
trans Ref trans
Match ?
Storage Compare / Search
Request Scoreboard
TLM Reference
Model
Response Scoreboard
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assertions
Scoreboard principles memory controller
DUT
sequencer
Test
sequences
driver
monitor
vif
sequences Bus A VIP
Master Agent
Write trans
Ref trans
Match ?
Storage Compare / Search
Scoreboard
Transaction Predictor
Read trans
Reads are checked against previous Writes
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Connecting the scoreboard Analysis Ports
UVM 1.1 Class Reference Manual
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Connecting the scoreboard UVM Example
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Storing Data / Transactions
Storage structure strongly depends on ordering model FIFO queues OOO dynamic arrays, queues Memory associative array (indexed by address) Others:
Associative array of queues
Data type: Memory scalar, bytes, integers, Data path:
Scalar Transaction Item Class
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Storage of transactions
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Transaction Match
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Predictor / Reference Model
Predictor required when: Compared transaction has not the same format as the
input (protocol bridges)
Design is transforming data (encryption, filter, encoder,)
Re-Use concern: Encapsulation: implemented as a separated class uvm_analysis_port / imp to connect UVM Factory to extend, replace existing objects
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Divide and Conquer
What if the design has Different transaction paths/routes Different behaviour depending on
Address segments Opcodes or other transaction attributes
Option 1: TLM Reference Model Option 2: Divide and Conquer
Replace complex predictor with several simpler scoreboards
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Divide and Conquer AXI read/write separation
DUT scoreboard FIFO read
scoreboard
FIFO write scoreboard
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Improving reuse
UVM Factory Same architecture Different implementation, different behavior
DUT scoreboard FIFO read
scoreboard
FIFO write scoreboard
OOO read scoreboard
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Complex NoC / Fabrics scoreboard example
AHB adapter
AHB adapter
AHB adapter
AHB adapter
AHB adapter Route M0 to S0
Master I/F 5
Master I/F 4
Master I/F 3
Master I/F 2
Master I/F 1
Master I/F 0
Cohe
renc
y Do
mai
n
AXI Monitor
OCP Monitor
AXI / ACE-Lite Monitor
AHB adapter
AXI adapter
OCP adapter
AXI adapter
AXI adapter
AXI adapter
ACE adapter
ACE adapter
Master ACE I/F 1
Master ACE I/F 0
Route M1 to S1
ACE
Scor
eboa
rd
Slave I/F 0
Slave I/F 3
Slave I/F 1
Slave I/F 2
Slave I/F 4
AHB Monitor
OCP Monitor
AXI Monitor
APB Monitor
Route M2 to S2
Master VIP Monitors
Slave VIP Monitors
VIP to Scbd adapters
VIP to Scbd adapters
NoC Scoreboard VIP Address Map &
Configuration
NoC
AHB Monitor
Master 5 AHB
DUT
AXI Monitor
ACE Monitor
AXI Monitor
ACE Monitor
UVM Agent
AXI Monitor
UVM Agent
UVM Agent
UVM Agent
UVM Agent
UVM Agent
UVM Agent
UVM Agent
UVM Agent
UVM Agent
UVM Agent
APB Slave 4
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Conclusion
Scoreboards verify transaction functional correctness
SystemVerilog provides agregate types for transaction storage & search
Dynamic Arrays, Associative Arrays, Queues, Classes
UVM ease scoreboard development, providing:
UVM analysis ports ( easier than call backs) uvm_transaction compare() / do_compare() methods UVM factory for extension, replacement & reuse.
Divide and Conquer:
keep simple things simple. Compose simple blocks to build complex behavior
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Thank you
Questions?
Advanced Scoreboard Techniques using UVMAbstract AgendaScoreboard TutorialsRandom Verification AspectsScoreboard RolesData flow design exampleTypical UVM testbenchScoreboard principles data flow designScoreboard principles complex data flow designScoreboard principles memory controllerConnecting the scoreboard Analysis PortsConnecting the scoreboard UVM ExampleStoring Data / TransactionsStorage of transactionsTransaction MatchPredictor / Reference ModelDivide and ConquerDivide and Conquer AXI read/write separationImproving reuseComplex NoC / Fabrics scoreboard exampleConclusionThank you