DUNE CRYO WIB MODS2 - University of Hawaiiidlab/taskAndSchedule/DUNE/DUNE C… · cmd femb 1 cmd...
Transcript of DUNE CRYO WIB MODS2 - University of Hawaiiidlab/taskAndSchedule/DUNE/DUNE C… · cmd femb 1 cmd...
DUNE CRYO WIBModificationsBNL Team 1/23/2019
Modifications to ProtoDUNE WIB
• FEMB Clock distribution• Two clocks distributed to each FEMB bypassing FPGA
• FEMB Power • A linear regulator add to feed power down to FEMB
• FEMB communication• Two IO Signals added to FEMB data cable
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SI5344 SY58608
PLL Jitter Cleaner
1:2FANOUT
To FPGA
SY89832From FPGA
To FEMB DATA CABLEFEMB 0
CMD
FEMB 1CMD
FEMB 2CMD
FEMB 3CMD
SY89847
To FEMB DATA CABLEFEMB 0
CLK
FEMB 1CLK
FEMB 2CLK
FEMB 3CLK
From FPGA
Not Used
DUNE CLK DUNE CLK
ProtoDUNE WIB CLOCK DISTRIBUTION
1:5FANOUT
1:4FANOUT
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SI5344
SY89832
PLL Jitter Cleaner
To FPGA
Not Used
SY89847
From FPGA
To FEMB DATA CABLEFEMB 0
CMD
FEMB 1CMD
FEMB 2CMD
FEMB 3CMD
SY89847
To FEMB DATA CABLEFEMB 0
CLK
FEMB 1CLK
FEMB 2CLK
FEMB 3CLK
From FPGA
Not Used
Not Used
DUNE CLK DUNE CLK
DUNE CLK
1:2FANOUT
1:5FANOUT
1:5FANOUT
DUNE CRYO WIB CLOCK DISTRIBUTION
ProtoDUNE WIB POWER
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LTM4644
DC2DC
DC2DC
DC2DC
DC2DC
DC2DC LTM8029
LDOTPS73201
2.5V @ 140mA
2.5V @ 1A
2.5V @ 1A
2.5V @ 1A
LDO 2.5V @ 1ATPS74401
2.65V @ 1A
3.3V
2.65V
DUNE CRYO WIB POWERScheme 1
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LTM4644
DC2DC
DC2DC
DC2DC
DC2DC
DC2DC LTM8029
LDOTPS73201
2.5V @ 100mA
2.5V @ 1A
2.5V @ 1A
LDO 2.5V @ 1A
LDO 2.5V @ 1A
TPS74401
TPS74401
2.65V @ 1A
3.3V
2.65V
2.65V
DUNE CYRO FEMB POWERConnector
• Samtec Power cables
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Total combined current Should not exceed 140mA
DUNE CRYO WIB POWERScheme 2
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LTM4644
DC2DC
DC2DC
DC2DC LTM8029
LDO
LDO
LDO
5.5V
Front Pannel
FUSE
FUSE
FUSE
FUSE
DC2DC
DC2DC
FEMB
ADJ V@ 2.5A
V+ Sense
V- Sense
5 V@ 100mA
DUNE CYRO FEMB POWERConnector
• Samtec Power cables
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Total combined current Should not exceed 140mA
Total combined current Should not exceed 2.5A
Signals Added to FEMB Cold Data Cable
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Not connected to FPGA
Connected to FPGA
Connected to FPGADIFF Pairs
DUNE CYRO FEMB Cold DataConnector
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TX Data 0
TX Data 1
TX Data 2
TX Data 3
FPGA IO
FPGA IO
FPGA IO
FPGA IO
FPGA IO
FPGA IO
CLK 0
CLK 1
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS pairsswapped
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