Dual, Wideband, Voltage-Feedback Operational Amplifier with ...
Dual-Voltage Supply for Power Reduction
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Transcript of Dual-Voltage Supply for Power Reduction
December 1, 2005December 1, 2005 ELEC 6970 - Project PresentationELEC 6970 - Project Presentation 11
Dual-Voltage Supply for Dual-Voltage Supply for Power ReductionPower Reduction
ELEC 6970 – Low Power DesignELEC 6970 – Low Power DesignProject PresentationProject Presentation
bybyMuthubalaji RamkumarMuthubalaji Ramkumar
December 1, 2005December 1, 2005 ELEC 6970 - Project PresentationELEC 6970 - Project Presentation 22
Problem StatementProblem Statement To Use a dual-supply voltage in order to To Use a dual-supply voltage in order to
reduce the power consumption of the reduce the power consumption of the 32 x 32 bit integer array multiplier circuit 32 x 32 bit integer array multiplier circuit without compromising the overall delaywithout compromising the overall delay
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Power and DelayPower and Delay
Power Power → → VDD2
Delay Delay → → KVDD───────
(V(VDDDD – V – Vtt))αα
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ApproachApproach
Low Voltage Assignment to as many cells as Low Voltage Assignment to as many cells as possiblepossible
The interconnections in this multiplier circuit The interconnections in this multiplier circuit makes it difficultmakes it difficult
Therefore assign Low Voltage Supply to as many Therefore assign Low Voltage Supply to as many gates as possiblegates as possible
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Things to watchThings to watch Reducing the Voltage Supply will increase the Reducing the Voltage Supply will increase the
delay of a gatedelay of a gate
Therefore assign Low-Voltage Supply only to the Therefore assign Low-Voltage Supply only to the gates which do not have any influence on the gates which do not have any influence on the Critical Path Delay directly or indirectlyCritical Path Delay directly or indirectly
Low voltage gate should have adequate voltage Low voltage gate should have adequate voltage swing in order to drive a High Voltage gate its swing in order to drive a High Voltage gate its feeding in to.feeding in to.
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4 x 4 Multiplier4 x 4 Multiplier
0
0
0
0
0 0 0 0
A0
A1
A2
A3
B3 B2 B1 B0
Y0
Y1
Y2
Y3Y4Y5Y6Y7
Fulladder
B
A
Carry in
Sum output
Sum input
Carry out
Array Cell
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Multiplier CellMultiplier Cell
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Low-Voltage Supply AssignmentLow-Voltage Supply Assignment
Output Cells Output Cells along the along the
edgeedge
N-1N-1 G4G4
First RowFirst Row 3(N-1)3(N-1) G1,G2,G3G1,G2,G3Second Row Second Row to Last Rowto Last Row
N(N-1)N(N-1) G1G1
Left ColumnLeft Column 2(N-1)2(N-1) G2,G3G2,G3
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Total Number of gates = 6NTotal Number of gates = 6N22
Number of gates with Low Voltage Number of gates with Low Voltage assignment = (N-1)(N+6) assignment = (N-1)(N+6)
Percentage of the circuit with Reduced VPercentage of the circuit with Reduced VDD DD
== (N-1)(N+6) / 6N(N-1)(N+6) / 6N22
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Percentage of the Circuit with Percentage of the Circuit with Reduced Voltage SupplyReduced Voltage Supply
0 20 40 60 80 100 120 14016
18
20
22
24
26
28
30
32
34
N - No of bits
Percentage of Gates under Low Voltage Supply
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Experimental Results for a CellExperimental Results for a Cell
Voltage Voltage (Volts)(Volts)
PPdyn dyn (Microwatts)(Microwatts)
PPstaticstatic (Picowatts)(Picowatts)
DelayDelay(Sec)(Sec)
1.81.8 9.19.1 246246 251 p251 p
1.51.5 5.275.27 171171 358 p358 p
1.21.2 2.872.87 112112 537 p537 p
0.90.9 0.790.79 6767 1.14 n1.14 n
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Experimental Results for a Experimental Results for a 4 x 4 Multiplier4 x 4 Multiplier
Voltage Voltage (Volts)(Volts)
PPdyn dyn (Microwatts)(Microwatts)
PPstaticstatic (Nanowatts)(Nanowatts)
DelayDelay(Sec)(Sec)
1.81.8 213213 1.61.6 1.57 n1.57 n
1.51.5 132.1132.1 1.131.13 1.76 n1.76 n
1.21.2 75.875.8 0.750.75 1.97 n1.97 n
0.90.9 36.436.4 0.460.46 2.2 n2.2 n
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A Single InverterA Single Inverter
Voltage Voltage (Volts)(Volts)
PPdyn dyn (Microwatts)(Microwatts)
PPstaticstatic (Picowatts)(Picowatts)
DelayDelay(Sec)(Sec)
1.81.8 1.881.88 1010 82 p82 p
1.51.5 0.5880.588 77 91 p91 p
1.21.2 0.1140.114 4.64.6 108 p108 p
0.90.9 0.0470.047 2.82.8 236 p236 p
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4 x 4 bit array Multiplier4 x 4 bit array Multiplier N=4N=4 Total Number of Gates = 6N2 = 6(16) = 96
Number of Gates with Low VNumber of Gates with Low VDD DD = (N-1)(N+6) = (N-1)(N+6) = (3)(10) = = (3)(10) = 30 = 31.25 %30 = 31.25 %
Number of Gates with Normal VNumber of Gates with Normal VDDDD = = 96 – 30 = 96 – 30 = 66 = 68.75%66 = 68.75%
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Power EstimationPower Estimation
Using Dual-Voltages, Using Dual-Voltages, 1.8V & 1.5V1.8V & 1.5V
Power Consumption = Power Consumption = (0.3125)(132.1uW) + (0.6875)((0.3125)(132.1uW) + (0.6875)(213uW213uW))
= = 187.73 uW187.73 uW
12%12% Power Reduction Power Reduction
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Power EstimationPower Estimation
Using Dual-Voltages, Using Dual-Voltages, 1.8V & 1.2V1.8V & 1.2V
Power Consumption = Power Consumption = (0.3125)(75.8uW) + (0.6875)((0.3125)(75.8uW) + (0.6875)(213uW213uW))
= = 170.125 uW170.125 uW
20.13 %20.13 % Power Reduction Power Reduction
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32 x 32 bit array Multiplier32 x 32 bit array Multiplier N=32N=32
Total Number of Gates = 6N2 = 6(1024) = 6144
Number of Gates with Low VNumber of Gates with Low VDD DD = (N-1)(N+6) = (N-1)(N+6) = (31)(38) = = (31)(38) = 1178 = 19.2 %1178 = 19.2 %
Number of Gates with Normal VNumber of Gates with Normal VDDDD = = 6144 – 1178 = 6144 – 1178 = 4966 = 80.8%4966 = 80.8%
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Power EstimationPower Estimation
Using Dual-Voltages, Using Dual-Voltages, 1.8V & 1.5V1.8V & 1.5V
Power Consumption = Power Consumption = (0.192)(8.45mW) + (0.808)((0.192)(8.45mW) + (0.808)(13.63mW13.63mW))
= = 12.64 mW12.64 mW
7.3%7.3% Power Reduction Power Reduction
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Power EstimationPower Estimation
Using Dual-Voltages, Using Dual-Voltages, 1.8V & 1.2V1.8V & 1.2V
Power Consumption = Power Consumption = (0.192)(4.85mW) + (0.808)((0.192)(4.85mW) + (0.808)(13.63mW13.63mW))
= = 11.9 mW11.9 mW
12.4%12.4% Power Reduction Power Reduction
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ConclusionConclusionPros…Pros… Reduction in power Reduction in power Delay is not compromisedDelay is not compromised No change in Area No change in Area Dual-power supply is easy to generate using potential Dual-power supply is easy to generate using potential
dividersdividersCons…Cons… The percentage of the circuit that can be fed with Low The percentage of the circuit that can be fed with Low
Voltage supply is lessVoltage supply is less Requires careful assignment of Low Voltage SupplyRequires careful assignment of Low Voltage Supply
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CommentsComments Learnt VHDL basicsLearnt VHDL basics
Introduction to very useful EDA toolsIntroduction to very useful EDA tools
Get a feel of VLSI Design Get a feel of VLSI Design
Appreciation of Low Power DesignAppreciation of Low Power Design
Time Consuming but worth itTime Consuming but worth it