DSP ProcessorDSP Processor

Behdad Hosseini, 781413112Behdad Hosseini, 781413112

University of IsfahanUniversity of Isfahan

April, May 2002April, May 2002

Dedicated to Z. HaghshenasDedicated to Z. Haghshenas

2

IntroductionIntroduction

Digital signals & systemsDigital signals & systems DSP (Digital Signal Processing)DSP (Digital Signal Processing) Digital Signal Processors (DSPs) vs General Digital Signal Processors (DSPs) vs General

Purpose Processors (GPPs)Purpose Processors (GPPs)

3

DSPs FeaturesDSPs Features

High speed DSP computationsHigh speed DSP computations Specialized instruction set High performance repetitive numeric calculations Fast & efficient memory accesses

Special mechanism for real-time I/OSpecial mechanism for real-time I/O Low power consumptionLow power consumption Low cost in comparison with GPPsLow cost in comparison with GPPs

4

DSPs General ApplicationsDSPs General Applications

Digital cellular phonesDigital cellular phones Satellite communicationsSatellite communications Seismic analysisSeismic analysis Vehicle collision Vehicle collision

avoidance avoidance Secure communicationsSecure communications Voice over InternetVoice over Internet Tape less answering Tape less answering

machinesmachines Motor controlMotor control SonarSonar

Voice mailVoice mail Digital camerasDigital cameras Navigation equipmentNavigation equipment Modems (POTS, ISDN, Modems (POTS, ISDN,

cable,...)cable,...) Audio productionAudio production Noise cancellationNoise cancellation VideoconferencingVideoconferencing Medical ultrasoundMedical ultrasound Music synthesis, effectsMusic synthesis, effects RadarRadar

5

DSPs μPs ApplicationsDSPs μPs Applications

Speech and audio compressionSpeech and audio compression FilteringFiltering Modulation and demodulationModulation and demodulation Error correction coding and decodingError correction coding and decoding Audio processing (e.g., surround sound, noise reduction, Audio processing (e.g., surround sound, noise reduction,

equalization, sample rate conversion, echo cancellation)equalization, sample rate conversion, echo cancellation) Signaling (e.g., DTMF detection)Signaling (e.g., DTMF detection) Speech recognitionSpeech recognition Signal synthesis (e.g., music, speech synthesis)Signal synthesis (e.g., music, speech synthesis)

6

DSPs CharacteristicsDSPs Characteristics

1.1. Data path & internal ALU architectureData path & internal ALU architecture

2.2. Specialized instruction setSpecialized instruction set

3.3. External memory architectureExternal memory architecture

4.4. Specialized addressing modesSpecialized addressing modes

5.5. Specialized execution controlSpecialized execution control

6.6. Specialized peripherals for DSPSpecialized peripherals for DSP

7

Data PathData Path

DSPsDSPs Performs all key arithmetic Performs all key arithmetic

operations in 1 cycle.operations in 1 cycle. Hardware support for Hardware support for

managing numeric fidelity:managing numeric fidelity: Shifters Guard bits Saturation

GPPsGPPs Multiplies often take >1 Multiplies often take >1

cyclecycle Shifts often take >1 cycleShifts often take >1 cycle Other operations (e.g. Other operations (e.g.

saturation, rounding) saturation, rounding) typically take multiple typically take multiple cyclescycles

8

DSPs Data Path ExampleDSPs Data Path Example

A representative conventional fixed-point DSP processor data path (from the Motorola DSP560xx, a 24-bit, fixed point processor family)

9

Instruction SetInstruction Set

DSPs Specialized, complex Specialized, complex

instructionsinstructions Multiple operations per Multiple operations per

instruction (e.g. using instruction (e.g. using VLIW)VLIW)

GPPs General-purpose General-purpose

instructionsinstructions Typically only one Typically only one

operation per instructionoperation per instruction

10

VLIWVLIW

Major features:Major features: Multiple independent

operations per cycle Packed into a single large

“instruction” or “packet” More regular, orthogonal,

RISC-like operations Large, uniform register sets

Very long instruction word Very long instruction word (VLIW) architectures are (VLIW) architectures are garnering increased attention garnering increased attention for DSP applications.for DSP applications.

11

Memory ArchitectureMemory Architecture

DSPs Harvard architectureHarvard architecture 2-4 memory accesses/cycle2-4 memory accesses/cycle No caches—on-chip No caches—on-chip

SRAMSRAM

GPPs Von Neumann architectureVon Neumann architecture Typically 1 access/cycleTypically 1 access/cycle May use cachesMay use caches

12

Von Neumann ArchitectureVon Neumann Architecture

The Von Neumann memory architecture, common among micro controllers. Since there is only one data bus, operands cannot be loaded while instructions are fetched, creating a bottleneck that slows the execution of DSP algorithms.

13

Harvard ArchitectureHarvard Architecture

A Harvard architecture, common to many DSP processors. The processor can simultaneously access the two memory banks using two independent sets of buses, allowing operands to be loaded while

fetching instructions..

14

Addressing ModesAddressing Modes

DSPs Dedicated address Dedicated address

generation unitsgeneration units Specialized addressing Specialized addressing

modes; e.g.:modes; e.g.: Auto-increment Modulo (circular) Bit-reversed (for FFT)

Good immediate data Good immediate data supportsupport

GPPs Often, no separate address Often, no separate address

generation unitgeneration unit General-purpose General-purpose

addressing modesaddressing modes

15

Execution ControlExecution Control

Hardware support for fast loopingHardware support for fast looping ““Fast interrupts” for I/O handlingFast interrupts” for I/O handling Real-time debugging supportReal-time debugging support

16

PeripheralsPeripherals

Host portsHost ports Bit I/O portsBit I/O ports On-chip DMA controllerOn-chip DMA controller Clock generatorsClock generators Synchronous serial portsSynchronous serial ports Parallel portsParallel ports TimersTimers On-chip A/D, D/A convertersOn-chip A/D, D/A converters

17

DSPs classifications (1)DSPs classifications (1)

By arithmetic formatBy arithmetic format Fixed-point Floating-point Block floating-point

By data widthBy data width Typical fixed-point DSPs: 16-bit Typical floating-point DSPs: 32-bit

By memory organizationBy memory organization By multiprocessor supportBy multiprocessor support

18

DSPs classifications (2)DSPs classifications (2)

By speedBy speed Million of instruction per second (MIPS) A basic operation (e.g. MAC) A basic algorithm (e.g. FFT, FIR or IIR filter) Benchmark programs

By power consumptionBy power consumption Operating voltage Sleep or idle mode Programmable clock dividers Peripheral control

19

DSPs EvolutionDSPs Evolution

First generation (TI TMS32010)First generation (TI TMS32010) Second generation (Motorola DSP56001, AT&T Second generation (Motorola DSP56001, AT&T

DSP16A, Analog Dev. ADSP-2100, TI TMS320C50)DSP16A, Analog Dev. ADSP-2100, TI TMS320C50) Third generation (Motorola DSP56301, TI Third generation (Motorola DSP56301, TI

TMS320C541, TI TMS320C80, Motorola MC68356)TMS320C541, TI TMS320C80, Motorola MC68356) Fourth generation (TI TMS320C6201, Intel Pentium Fourth generation (TI TMS320C6201, Intel Pentium

MMX)MMX)

20

First Generation (1982)First Generation (1982)

16-bit fixed-point16-bit fixed-point Harvard architectureHarvard architecture AccumulatorAccumulator Specialized instruction setSpecialized instruction set 390 ns MAC time (228 ns 390 ns MAC time (228 ns

today)today)

21

Second Generation (1987)Second Generation (1987)

24-bit data, instructions24-bit data, instructions 3 memory spaces (X, Y, P)3 memory spaces (X, Y, P) Parallel movesParallel moves Single- and multi Single- and multi

instructioninstruction hardwarehardware loopsloops Modulo addressingModulo addressing 75 ns MAC (21 ns today)75 ns MAC (21 ns today)

22

Third Generation (1995)Third Generation (1995)

Enhanced conventional DSP architecturesEnhanced conventional DSP architectures 3.0 or 3.3 volts3.0 or 3.3 volts More on-chip memoryMore on-chip memory Application-specific function units in data path or as Application-specific function units in data path or as

co-processorsco-processors More sophisticated debugging and application More sophisticated debugging and application

development toolsdevelopment tools DSP cores (Pine & Oak from DSP G., cDSP from TI)DSP cores (Pine & Oak from DSP G., cDSP from TI) 20 ns MAC (10 ns today)20 ns MAC (10 ns today)

23

Fourth Generation (1998)Fourth Generation (1998)

Blazing clock speeds and super scalar architectures Blazing clock speeds and super scalar architectures VLIW-like architectures, achieve top performance VLIW-like architectures, achieve top performance

via high parallelism and increased clock speedsvia high parallelism and increased clock speeds 3 ns MAC throughput3 ns MAC throughput Expensive, power-hungryExpensive, power-hungry

24

DSPs Evolution ChartDSPs Evolution Chart

25

DSPs Performance ChartDSPs Performance Chart

Execution times for a 256-point complex FFT in microseconds

26

Role of GPPs (1)Role of GPPs (1)

Added capabilities:Added capabilities: Add single-instruction, multiple-data instruction set

extensions (e.g., MMX Pentium) Integrate a fixed-point DSP processor-like data path and

related resources with an existing mC/mP core (e.g. Hitachi SH-DSP)

Add a DSP co-processor to an existing mC/mP core (e.g., ARM Piccolo)

Create an all-new, hybrid architecture (e.g. Siemens TriCore)

27

Role of GPPs (2)Role of GPPs (2)

Assisted capabilities:Assisted capabilities: Very high clock rates (500-1000 MHz) Super scalar (“multi-issue”) architectures Single-cycle multiplication and arithmetic ops. Good memory bandwidth Branch prediction In some cases, single-instruction, multiple-data (SIMD)

ops Caching & pipelining

28

ConclusionConclusion

DSP processor performance has increased by a factor of about DSP processor performance has increased by a factor of about 150x over the past 15 years (~40%/year)150x over the past 15 years (~40%/year)

Processor architectures for DSP will be increasingly specialized Processor architectures for DSP will be increasingly specialized for applications, especially communications applications for applications, especially communications applications

General-purpose processors will become viable for many DSP General-purpose processors will become viable for many DSP applicationsapplications

Users of processors for DSP will have an expanding array of Users of processors for DSP will have an expanding array of choices choices

Selecting processors requires a careful, application-specific Selecting processors requires a careful, application-specific analysisanalysis

29

Web Links & InformationWeb Links & Information

http://www.bdti.comhttp://www.bdti.com http://www.eg3.com/dsp http://www.eg3.com/dsp

Buyer’s Guide to DSP ProcessorsBuyer’s Guide to DSP Processors, Berkeley, California: , Berkeley, California: Berkeley Design Technology, Inc., 1994, 1995, 1997, 1999. Berkeley Design Technology, Inc., 1994, 1995, 1997, 1999.

Phil Lapsley, Jeff Bier, Amit Shoham, and Edward A. Lee, Phil Lapsley, Jeff Bier, Amit Shoham, and Edward A. Lee, DSP Processor Fundamentals: Architectures and FeaturesDSP Processor Fundamentals: Architectures and Features, , Berkeley, California: Berkeley Design Technology, Inc., Berkeley, California: Berkeley Design Technology, Inc., 1996. 1996.

Will Strauss, Will Strauss, DSP Strategies 2002DSP Strategies 2002, Tempe, Arizona: , Tempe, Arizona: Forward Concepts, 1999. Forward Concepts, 1999.