Dsd Vhdl Ch5
Transcript of Dsd Vhdl Ch5
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Ch. 5 Digital Design with SM Chart
Flowchart for Hardware Design
- alternative to state diagram
- easier to understand
- condition for state graphs are satisfied automatically
- direct hardware realizationExamples
-multiplier
-dice game controller
Components of State Machine (Flow) Charts
SM Chart, or ASM(Algorithmic State Machine) Chart
3 components
1) State Box 2) Decision Box 3) Conditional Output Box
State box
State_name/output list, output list is optional
Optional state code
Condition: T rue , False branches
Conditional output box
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SM Block Contains only 1 state box + decision + cond. output
description of one state
All tests take place in one clock
1 Entrance path and one or more exit path
in p ath 3
z3=z4=0
link path
entrancepath exit
path(s)
Equivalent SM blocks
( b) is more complex
Next state
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Equivalent SM Chart for a Combinational
Networks
(a) (b)
Z1=1 if (A=1) or
(A=0,B=1, and C=1)
i.e. Z1=A+ABC =A+BC
Rules of SM block
1. For every valid c ombination of input variab les ,
there must be exactly one exit path defined.
2. Internal feedback is not allowed in SM block
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Equivalent SM Blocks
Correct in SM chart
concurrent!
sequential!
executed in one clock time,
serial form
Conversion of a State Graph to an SM Chart
Moore output : Za,Zb, Zc
Mealy output: Z1,
Z2
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Timing Chart
5.2 Derivation of SM Charts
draw block diagram
de fine input and o utput s ignals
construct SM chart
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SM chart for Binary Multiplier
K: completion signal
VHDL for SM Chart of Figure 5-9
entity Mult is
port (CLK,St,K,M: in bit;
Load,Sh,Ad,Done: out bi t ) ;
end mult;
architecture SMbehave of Mult is
signal State , Nexts ta te : integer range 0 to 3 ;
begin
process ( S t , K, M, S ta te ) - - s t a r t if s t at e o r in p ut schange
begin
Load
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when 2 = > Sh
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Flow Chart for Dice Game
SM Chart for Dice Game
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State Graph for Dice Game Controller
Behavioral Model for Dice Game
entity DiceGame is
port ( Rb, Res et, CLK: in bit;
Sum: in integer range 2 to 1 2 ;
Roll, Win, Lose : ou t bi t ) ;
e nd DiceGame;
library BITLIB;
us e BITLIB.bit_pack. all;
architecture DiceBehave of DiceGame is
signal State , Nexts ta te : integer range 0 to 5 ;
signal Point: intege r range 2 to 1 2 ;
signal Sp: bit;begin
process (Rb, Res et , Sum, State)
begin
Sp
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when 2 = > Win
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SM Chart for Dice Game Test
Dice Game Test Module
entity GameTest is
port (Rb, Rese t: out bit; Sum: out integer range 2 to 12;
CLK: inout bit; Roll, Win, Lose: in bit) ;
e nd GameTest ;
library BITLIB;
us e BITLIB.bit_pack.all;
architecture dicetest of GameTest issignal Ts tate , Tnext: integer range 0 to 3 ;
signal T rig1: bit;
type ar r is arra y ( 0 to 11) of integer;
constant Sumarray:ar r := (7 ,11 ,2 ,4 ,7 ,5 ,6 ,7 ,6 ,8 ,9 ,6) ;
begin
CLK
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process (Roll, Win, Lose, Tstate)
variable i: na tura l; - - i is i n it ia l ized to 0
begin
case T s t a t e is
when 0 = > Rb
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Simulation and Command File for Dice Game
Tester
list / dice test/ trig1 - NOTrigge r sum1 win1 los e1 / dice / point
run 2000
PLA Table for Multiplier Control
A+ = A'BM'K + A'BM + AB'K = A'B(M + K) + AB'K
B+ = A'B'St + A'BM'(K'+K) + AB'(K'+K) = A'B'St +
A'BM' + AB'
Sh = A'BM'(K'+K) + AB'(K'+K) = A'BM' + AB'
Load = A'B'St Ad = A'B MDone = A B
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PLA Realization of Dice Game Controller
PLA Table for Dice Game
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Maps Derived from Table 5-2
Data Flow Model for Dice Game
library BITLIB;
us e BITLIB.bit_pack.all;
architecture Dice_Eq of DiceGame is
signal Sp,Eq,D7,D711 ,D231 2: bit:= '0'; s ignal
DA,DB,DC,A,B,C :bit:= '0 ';
signal Point: integer range 2 to 12;
beginprocess (Clk)
begin
if rising_edge(Clk) then
A
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Win
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Complete Dice Gameentity Game is
port ( Rb, Res et, Clk: in bit;
Win, Lose : ou t bi t ) ;
e nd Game;
architecture Play1 of Game is
component Counter
port ( Clk, Roll: in bit;
Sum: out integer range 2 to 1 2 ) ;
end component ;
component DiceGame
port ( Rb, Res et, CLK: in bit;
Sum: in integer range 2 to 1 2 ;
Roll, Win, Lose : ou t bi t ) ;
end component ;signal roll1: bit;
signal sum1: integer range 2 to 1 2 ;
begin
Dice: Dicegame port map(Rb,Reset,Clk,sum1,roll1,Win,Lose);
Count: Counter port map(Clk,roll1,sum1);
e nd Play1;
Control Network Using an input Mux
to Select the Next State
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PLA/ ROM Table for Figure 5-27
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MUX for SM Chart of Fig. 5-27
Counter Network using a Counter for State
Register
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SM chart with Serial State Assignment and
Added X-states
SM Chart with Serial State Assignment and
Added X-state
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MUX for SM chart of Figure 5-30
PLA Table for Figure 5-31
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SM Charts for Serially Linked State Machine
Linked SM Charts for Dice Game
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Linked SM Charts for Dice Game