DS90UH925Q 720p 24-bit Color FPD-Link III Serializer … · R[7:0] HS VS PCLK PDB Serializer...

R[7:0]

HSVS

PCLK

PDBSerializer Deserializer

DE

RGB Display720p

24-bit color depth

RG

B D

igita

l Dis

play

Inte

rfac

e

HOSTGraphicsProcessor

FPD-Link III1 Pair / AC Coupled

DS90UH925Q-Q1 DS90UH926Q-Q1100 ohm STP Cable

PASS

VDDIO

OSS_SEL

SCLSDA

INTB

I2S AUDIO (STEREO)

OEN

LOCK

IDx DAP DAP

0.1 PF 0.1 PFG[7:0]B[7:0]

SCLSDAIDx

R[7:0]

HSVS

PCLKDE

G[7:0]B[7:0]

RIN+

RIN-

DOUT+

DOUT-

(1.8V or 3.3V)(1.8V or 3.3V) (3.3V) (3.3V)VDDIO

3/

I2S AUDIO (STEREO)

3/MODE_SEL MODE_SEL

MCLK

PDB

INTB_IN

VDD33 VDD33

Product

Folder

Sample &Buy

Technical

Documents

Tools &

Software

Support &Community

DS90UH925Q-Q1SNLS336J –OCTOBER 2010–REVISED NOVEMBER 2014

DS90UH925Q-Q1 720p 24-bit Color FPD-Link III Serializer with HDCP1 Features 3 Description

The DS90UH925Q-Q1 serializer, in conjunction with1• Integrated HDCP Cipher Engine with On-chip Key

the DS90UH926Q-Q1 deserializer, provides aStoragesolution for secure distribution of content-protected

• Bidirectional Control Interface Channel Interface digital video within automotive entertainmentwith I2C Compatible Serial Control Bus systems. This chipset translates a parallel RGB Video

Interface into a single pair high-speed serialized• Supports High Definition (720p) Digital Videointerface. The digital video data is protected using theFormatindustry standard HDCP copy protection scheme.• RGB888 + VS, HS, DE and I2S Audio Supported The serial bus scheme, FPD-Link III, supports video

• 5 to 85 MHz PCLK Supported and audio data transmission and full duplex control• Single 3.3V Operation with 1.8 V or 3.3 V including I2C communication over a single differential

link. Consolidation of video data and control over aCompatible LVCMOS I/O Interfacesingle differential pair reduces the interconnect size• AC-coupled STP Interconnect up to 10 metersand weight, while also eliminating skew issues and

• Parallel LVCMOS Video Inputs simplifying system design.• DC-balanced & Scrambled Data with Embedded The DS90UH925Q-Q1 serializer embeds the clock,Clock content protects the data payload, and level shifts the• HDCP Content Protected signals to high-speed low voltage differential

signaling. Up to 24 RGB data bits are serialized along• Supports HDCP Repeater Applicationwith three video control signals and up to two I2S• Internal Pattern Generationdata inputs.

• Low Power Modes Minimize Power DissipationEMI is minimized by the use of low voltage differential• Automotive Grade Product: AEC-Q100 Grade 2 signaling, data scrambling and randomization andQualified spread spectrum clocking compatibility.

• > 8k V HBM and ISO 10605 ESD ratingThe HDCP cipher engine is implemented in the• Backward Compatible Modes serializer and deserializer. HDCP keys are stored inon-chip memory.2 Applications

Device Information (1)• Automotive Display for NavigationPART NUMBER PACKAGE BODY SIZE• Rear Seat Entertainment Systems

DS90UH925Q-Q1 WQFN (48) 7.00 mm x 7.00 mm

(1) For all available packages, see the orderable addendum atthe end of the datasheet.

Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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DS90UH925Q-Q1SNLS336J –OCTOBER 2010–REVISED NOVEMBER 2014 www.ti.com

Table of Contents7.3 Feature Description................................................. 141 Features .................................................................. 17.4 Device Functional Modes........................................ 212 Applications ........................................................... 17.5 Programming........................................................... 253 Description ............................................................. 17.6 Register Maps ......................................................... 274 Revision History..................................................... 2

8 Applications and Implementation ...................... 425 Pin Configuration and Functions ......................... 38.1 Application Information............................................ 426 Specifications......................................................... 68.2 Typical Application .................................................. 436.1 Absolute Maximum Ratings ..................................... 6

9 Power Supply Recommendations ...................... 456.2 Handling Ratings....................................................... 69.1 Power Up Requirements and PDB Pin ................... 456.3 Recommended Operating Conditions....................... 69.2 CML Interconnect Guidelines.................................. 456.4 Thermal Information .................................................. 7

10 Layout................................................................... 466.5 DC Electrical Characteristics ................................... 710.1 Layout Guidelines ................................................. 466.6 AC Electrical Characteristics..................................... 810.2 Layout Example .................................................... 476.7 DC and AC Serial Control Bus Characteristics......... 9

11 Device and Documentation Support ................. 496.8 Recommended Timing for Serial Control Bus .......... 911.1 Documentation Support ........................................ 496.9 Switching Characteristics ........................................ 1211.2 Trademarks ........................................................... 496.10 Typical Charateristics ........................................... 1311.3 Electrostatic Discharge Caution............................ 497 Detailed Description ............................................ 1411.4 Glossary ................................................................ 497.1 Overview ................................................................. 14

12 Mechanical, Packaging, and Orderable7.2 Functional Block Diagram ....................................... 14Information ........................................................... 49

4 Revision History

Changes from Revision I (April 2013) to Revision J Page

• Added, updated, or renamed the following sections: Device Information Table, Pin Configuration and Functions,Application and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support;Mechanical, Packaging, and Ordering Information................................................................................................................. 1

• Fixed typo for GPIO configuration ........................................................................................................................................ 17• Removed two MODE_SEL modes: I2S Channel B, and Backward Compatible.................................................................. 22• Removed IDx addresses 0x22, 0x24, 0x2C, 0x2E, 0x30, 0x32, 0x34 ................................................................................. 25• Changed suggested resistor values for IDx addresses 0x1E, 0x20, 0x26, 0x28, 0x2A....................................................... 25

Changes from Revision H (October 2010) to Revision I Page

• Changed layout from National Data Sheet style to TI format................................................................................................. 1

2 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: DS90UH925Q-Q1


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R2

G1/

GP

IO3

DS90UH925Q-Q1TOP VIEW

B6

B7

HS

VS

DE

CA

PL1

2

SC

L

SD

A

PC

LK

I2S

_DA

/GP

O_R

EG

6

I2S

_WC

/GP

O_R

EG

7

I2S_CLK/GPO_REG8

CAPP12

RES0

NC

CAPHS12

RES1

DOUT-

DOUT+

PDB

VDD33

CMF

MODE_SEL

R1/

GP

IO1

R3

R4

VD

DIO

INT

B

R5

R6

R7

B5

B4

B3

B2

B1/I2S_DB/GPO_REG5

B0/GPO_REG4

G7

G6

G5

G4

G3

G2

DAP = GND

IDx

13

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19

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IO2

R0/

GP

IO0

DS90UH925Q-Q1www.ti.com SNLS336J –OCTOBER 2010–REVISED NOVEMBER 2014

5 Pin Configuration and Functions

48-PinPackage RHS

(Top View)

Pin FunctionsPIN

I/O, TYPE DESCRIPTIONNAME NUMBER

LVCMOS PARALLEL INTERFACER[7:0] 34, 33, 32, 29, I, LVCMOS RED Parallel Interface Data Input Pins

28, 27, 26, 25 w/ pull down Leave open if unused.R0 can optionally be used as GPIO0 and R1 can optionally be used as GPIO1.

G[7:0] 42, 41, 40, 39, I, LVCMOS GREEN Parallel Interface Data Input Pins38, 37, 36, 35 w/ pull down Leave open if unused.

G0 can optionally be used as GPIO2 and G1 can optionally be used as GPIO3.B[7:0] 2, 1, 48, 47, I, LVCOS BLUE Parallel Interface Data Input Pins

46, 45, 44, 43 w/ pull down Leave open if unusedB0 can optionally be used as GPO_REG4 and B1 can optionally be used as GPO_REG5.

HS 3 I, LVCMOS Horizontal Sync Input Pinw/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse whenthe Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.See Table 6.

VS 4 I, LVCMOS Vertical Sync Input Pinw/ pull down Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width

is 130 PCLKs.

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Pin Functions (continued)PIN


DE 5 I, LVCMOS Data Enable Input Pinw/ pull down Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the

Control Signal Filter is enabled. There is no restriction on the minimum transition pulse whenthe Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.See Table 6.

PCLK 10 I, LVCMOS Pixel Clock Input Pin. Strobe edge set by RFB configuration register. See Table 6.w/ pull downI2S_CLK, 13, 12, 11 I, LVCMOS Digital Audio Interface Data Input PinsI2S_WC, w/ pull down Leave open if unused.I2S_DA I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as

GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.OPTIONAL PARALLEL INTERFACEI2S_DB 44 Second Channel Digital Audio Interface Data Input pin at 18–bit color mode and set by

I, LVCMOS MODE_SEL pin or configuration registerw/ pull down Leave open if unused.

I2S_DB can optionally be used as B1 or GPO_REG5.GPIO[3:0] 36, 35, 26, 25 General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or

I/O, LVCMOS configuration register. See Table 6.w/ pull down Leave open if unused

Shared with G1, G0, R1 and R0.GPO_REG[ 13, 12, 11, 44, O, LVCMOS General Purpose Outputs and set by configuration register. See Table 6.8:4] 43 w/ pull down Share with I2S_CLK, I2S_WC, I2S_DA, I2S_DB or B1, B0.CONTROLPDB 21 I, LVCMOS Power-down Mode Input Pin

w/ pull-down PDB = H, device is enabled (normal operation)Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.PDB = L, device is powered down.When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL isshutdown, and IDD is minimized. Control Registers are RESET.

MODE_SEL 24 I, Analog Device Configuration Select. See Table 4.I2CIDx 6 I, Analog I2C Serial Control Bus Device ID Address Select

External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.Connect to external pull-up and pull-down resistor to create a voltage divider. See Figure 19.

SCL 8 I/O, LVCMOS I2C Clock Input / Output InterfaceOpen Drain Must have an external pull-up to VDD33, DO NOT FLOAT.

Recommended pull-up: 4.7kΩ.SDA 9 I/O, LVCMOS I2C Data Input / Output Interface

Open Drain Must have an external pull-up to VDD33, DO NOT FLOAT.Recommended pull-up: 4.7kΩ.




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Pin Functions (continued)PIN


STATUSINTB 31 O, LVCMOS HDCP Interrupt

Open Drain INTB = H, normalINTB = L, Interrupt requestRecommended pull-up: 4.7kΩ to VDDIO

FPD-Link III SERIAL INTERFACEDOUT+ 20 O, LVDS True Output

The output must be AC-coupled with a 0.1µF capacitor.DOUT- 19 O, LVDS Inverting Output

The output must be AC-coupled with a 0.1µF capacitor.CMF 23 Analog Common Mode Filter.

Connect 0.1µF to GNDPOWER (1) and GROUNDVDD33 22 Power Power to on-chip regulator 3.0 V - 3.6 V. Requires 4.7 uF to GNDVDDIO 30 Power LVCMOS I/O Power 1.8 V ±5% OR 3.0 V - 3.6 V. Requires 4.7 uF to GNDGND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN

package. Connect to the ground plane (GND) with at least 9 vias.REGULATOR CAPACITORCAPHS12, 17, 14 CAP Decoupling capacitor connection for on-chip regulator. Requires a 4.7uF to GND at eachCAPP12 CAP pin.CAPL12 7 CAP Decoupling capacitor connection for on-chip regulator. Requires two 4.7uF to GND at this

CAP pin.OTHERSNC 16 NC Do not connect.RES[1:0] 18, 15 GND Reserved. Tie to Ground.

(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.




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6 Specifications

6.1 Absolute Maximum Ratings (1) (2)

over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT

Supply Voltage – VDD33 -0.3 4.0 VSupply Voltage – VDDIO -0.3 4.0 VLVCMOS I/O Voltage (3) -0.3 VDDIO + 0.3 VSerializer Output Voltage -0.3 2.75 VJunction Temperature 150 °C

(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability andspecifications.

(2) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation ofdevice reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings orother conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended OperatingConditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(3) The maximum limit (VDDIO +0.3V) does not apply to the PDB pin during the transition to the power down state (PDB transitioning fromHIGH to LOW).

6.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range -65 +150 °CHuman body model (HBM), per AEC Q100-002 (1) ±8 ±8

kVV(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 ±1.25 ±1.25

Machine Model (MM) ±250 ±250 VAir Discharge ±15 ±15ESD Rating (IEC 61000-4-2, (DOUT+, DOUT-)

powered-up only)Contact DischargeRD= 330Ω, CS = 150pF ±8 ±8(DOUT+, DOUT-)

kVAir Discharge ±15 ±15ESD Rating (ISO 10605) (DOUT+, DOUT-)

RD= 330Ω, CS = 150pF/330pFContact DischargeRD= 2KΩ, CS = 150pF/330pF ±8 ±8(DOUT+, DOUT-)

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITSupply Voltage (VDD33) 3.0 3.3 3.6 VLVCMOS Supply Voltage (VDDIO) 3.0 3.3 3.6 VORLVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 VOperating Free Air Temperature (TA) −40 25 105 °CPCLK Frequency 5 85 MHzSupply Noise 100 mVP-P




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6.4 Thermal InformationRHS

THERMAL METRIC (1) UNIT48 PINS

RθJA Junction-to-ambient thermal resistance 35RθJC(top) Junction-to-case (top) thermal resistance 5.2RθJB Junction-to-board thermal resistance 5.5

°C/WψJT Junction-to-top characterization parameter 0.1ψJB Junction-to-board characterization parameter 5.5RθJC(bot) Junction-to-case (bottom) thermal resistance 1.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 DC Electrical Characteristics (1) (2) (3)

Over recommended operating supply and temperature ranges unless otherwise specified.PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT

LVCMOS I/O DC SPECIFICATIONSVIH High Level Input Voltage VDDIO = 3.0 to 3.6V 2.0 VDDIO VVIL Low Level Input Voltage VDDIO = 3.0 to 3.6V PDB GND 0.8 VIIN Input Current VIN = 0V or VDDIO = 3.0 to 3.6V −10 ±1 10 μA

VDDIO = 3.0 to 3.6V 2.0 VDDIO VVIH High Level Input Voltage 0.65*VDDIO = 1.71 to 1.89V VDDIO VVDDIOR[7:0], G[7:0],

VDDIO = 3.0 to 3.6V GND 0.8 VB[7:0], HS, VS,VIL Low Level Input Voltage DE, PCLK, 0.35*VDDIO = 1.71 to 1.89V GND VI2S_CLK, VDDIOI2S_WC,

VDDIO = 3.0 I2S_DA, I2S_DB −10 ±1 10 μAto 3.6VIIN Input Current VIN = 0V or VDDIO VDDIO = 1.71 −10 ±1 10 μAto 1.89V

VDDIO = 3.0 to 2.4 VDDIO V3.6VVOH High Level Output Voltage IOH = −4mA

VDDIO = 1.71 VDDIO - VDDIO Vto 1.89V 0.45VDDIO = 3.0 to GND 0.4 VGPIO[3:0],3.6V

VOL Low Level Output Voltage IOL = +4mA GPO_REG[8:4]VDDIO = 1.71 GND 0.35 Vto 1.89V

IOS Output Short Circuit Current VOUT = 0V −50 mATRI-STATE® OutputIOZ VOUT = 0V or VDDIO, PDB = L, −10 10 μACurrent

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except asotherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only andare not ensured.

(2) Typical values represent most likely parametric norms at VDD = 3.3 V, TA = +25 °C, and at the Recommended Operating Conditions atthe time of product characterization and are not ensured.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to groundexcept VOD and ΔVOD, which are differential voltages.




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DC Electrical Characteristics(1) (2) (3) (continued)Over recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNITFPD-LINK III CML DRIVER DC SPECIFICATIONS

Differential Output VoltageVODp-p RL = 100Ω, Figure 1 1160 1250 1340 mVp-p(DOUT+) – (DOUT-)ΔVOD Output Voltage Unbalance 1 50 mV

2.5-Offset Voltage – Single- 0.25*VOVOS RL = 100Ω, Figure 1 Vended Dp-pDOUT+, DOUT-

(TYP)

Offset Voltage UnbalanceΔVOS 1 50 mVSingle-endedIOS Output Short Circuit Current DOUT+/- = 0V, PDB = L or H −38 mA

Internal TerminationRT 40 52 62 ΩResistor - Single endedSUPPLY CURRENTIDD1 VDD33= 3.6V VDD33 148 170 mA

Supply Current Checker Board Pattern, VDDIO = 3.6V 90 180 μA(includes load current) Figure 2IDDIO1 VDDIOVDDIO =RL = 100Ω, f = 85 MHz 1 1.6 mA1.89VIDDS1 VDD33 = 3.6V VDD33 1.2 2.4 mA

Supply Current Remote 0x01[7] = 1, deserializer VDDIO = 3.6V 65 150 μAAuto Power Down Mode is powered downIDDIOS1 VDDIOVDDIO = 55 150 μA1.89V

IDDS2 VDD33 = 3.6V VDD33 1 2 mAPDB = L, All LVCMOSSupply Current Power VDDIO = 3.6V 65 150 μAinputs are floating or tiedDownIDDIOS2 VDDIOVDDIO =to GND 50 150 μA1.89V

6.6 AC Electrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)

PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNITGPIO BIT RATE

Forward Channel Bit Rate f = 5 – 85 0.25* f MbpsBR See (4) (5) MHz

Back Channel Bit Rate 75 kbpsGPIO[3:0]RECOMMENDED TIMING for PCLKtTCP PCLK Period 11.76 T 200 nstCIH PCLK Input High Time See (4) (5) PCLK 0.4*T 0.5*T 0.6*T nstCIL PCLK Input Low Time 0.4*T 0.5*T 0.6*T ns

PCLK Input Transition Time f = 5 MHz 4.0 nstCLKT Figure 3 (4) (5)

f = 85 MHz 0.5 nstIJIT PCLK Input Jitter Tolerance, f = 5 –f / 40 < Jitter Freq < f / 20 (5) (6) 0.4 0.6 UIBit Error Rate ≤10–10 78MHz




(4) Specification is ensured by design and is not tested in production.(5) Specification is ensured by characterization and is not tested in production.(6) Jitter Frequency is specified in conjunction with DS90UH926 PLL bandwidth.




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6.7 DC and AC Serial Control Bus CharacteristicsOver 3.3V supply and temperature ranges unless otherwise specified. (1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVIH 0.7*Input High Level SDA and SCL VDD33 VVDD33

VIL 0.3*Input Low Level Voltage SDA and SCL GND VVDD33

VHY Input Hysteresis >50 mVVOL SDA, IOL = 1.25 mA 0 0.36 VIin SDA or SCL, VIN = VDD33 or GND -10 10 µAtR SDA RiseTime – READ 430 ns

SDA, RPU = 10 kΩ, Cb ≤ 400 pF, see Figure 8tF SDA Fall Time – READ 20 nstSU;DAT Set Up Time — READ See Figure 8 560 nstHD;DAT Hold Up Time — READ See Figure 8 615 nstSP Input Filter 50 nsCin Input Capacitance SDA or SCL <5 pF




6.8 Recommended Timing for Serial Control BusOver 3.3V supply and temperature ranges unless otherwise specified.

MIN TYP MAX UNITSfSCL Standard Mode 0 100 kHz

SCL Clock FrequencyFast Mode 0 400 kHz

tLOW Standard Mode 4.7 usSCL Low Period

Fast Mode 1.3 ustHIGH Standard Mode 4.0 us

SCL High PeriodFast Mode 0.6 us

tHD;STA Hold time for a start or a Standard Mode 4.0 usrepeated start condition

Fast Mode 0.6 usFigure 8tSU:STA Set Up time for a start or a Standard Mode 4.7 us

repeated start conditionFast Mode 0.6 usFigure 8

tHD;DAT Standard Mode 0 3.45 usData Hold TimeFigure 8 Fast Mode 0 0.9 us

tSU;DAT Standard Mode 250 nsData Set Up TimeFigure 8 Fast Mode 100 ns

tSU;STO Standard Mode 4.0 usSet Up Time for STOP Condition,Figure 8 Fast Mode 0.6 usBus Free Time Standard Mode 4.7 us

tBUF Between STOP and START,Fast Mode 1.3 usFigure 8Standard Mode 1000 nsSCL & SDA Rise Time,tr Figure 8 Fast Mode 300 nsStandard Mode 300 nsSCL & SDA Fall Time,tf Figure 8 Fast mode 300 ns




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100:

DOUT+

DOUT-CL

CL80%

20%

80%

20%Vdiff = 0V

tLHT tHLT

DifferentialSignal

PCLK

20%

80%

20%

80%

0V

VDDIO

CLKTttCLKT

GND

VDDIO

GND

VDDIORGB[n] (odd),

VS, HS

PCLK

RGB[n] (even),DE GND

VDDIO

DOUT+

0V

0V

VOD+

VOD-

VOD-

VODSingle Ended

Differential

VOS

DOUT-

(DOUT+) - (DOUT-)

|

PA

RA

LLE

L-T

O-S

ER

IAL

30RGB[7:0],

HS,VS,DE, I2S

100:

PCLK

DOUT-

DOUT+

D

100 nF

100 nF

SCOPEBW û 4GHz

Differential probeInput Impedance û 100 k:

CL ú 0.5 pfBW û 3.5 GHz

VOD+


Figure 1. Serializer VOD DC Output

Figure 2. Checkboard Data Pattern

Figure 3. Serializer Input Clock Transition Time

Figure 4. Serializer CML Output Load and Transition Time




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SCL

SDA

tHD;STA

tLOW

tr

tHD;DAT

tHIGH

tf

tSU;DAT

tSU;STA tSU;STO

tf

START REPEATEDSTART

STOP

tHD;STA

START

tSP

trBUFt

DOUT(Diff.)

tDJIT

VOD (+)

tBIT (1 UI)

EYE OPENING

VOD (-)

0V

tDJIT

PDB 1/2 VDDIO

PCLK

DOUT(Diff.)

Driver OFF, VOD = 0V Driver On

VDDVDDIO

tPLD

0V

VDDIO

PCLK

RGB[7:0], HS,VS,DE

tTCP

tDIH

Setup

Hold VDDIO/2

VDDIO/2

tDIS

VDDIO/2 VDDIO/2

VDDIO/2


Figure 5. Serializer Setup and Hold Times

Figure 6. Serializer Lock Time

Figure 7. Serializer CML Output Jitter

Figure 8. Serial Control Bus Timing Diagram




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6.9 Switching Characteristicsover operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCML Output Low-to-HightLHT 80 130 psTransition Time DOUT+,See Figure 4 DOUT-CML Output High-to-LowtHLT 80 130 psTransition Time

tDIS Data Input Setup to PCLK R[7:0], 2.0 nsG[7:0],B[7:0],

HS, VS,DE,See Figure 5 PCLK,tDIH Data Input Hold from PCLK 2.0 ns

I2S_CLK,I2S_WC,I2S_DA,I2S_DB

f = 5 – 85tPLD Serializer PLL Lock Time Figure 6 (1) 131*T nsMHzf = 5 – 85tSD Delay — Latency 145*T nsMHz

RL = 100Ω 0.25 0.30 UIOutput Total Jitter, f = 85MHz, LFMODE = L DOUT+,tTJIT Bit Error Rate ≥10-10DOUT-RL = 100ΩFigure 7 (2) (3) (4) 0.25 0.30 UIf = 5MHz, LFMODE = H

(1) tPLD is the time required by the device to obtain lock when exiting power-down state with an active PCLK.(2) Specification is ensured by characterization and is not tested in production.(3) Specification is ensured by design and is not tested in production.(4) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 35*PCLK). The UI scales with PCLK frequency.




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78 MHz TX Pixel Clock

Input (2 V/DIV)

78 MHz RX Pixel Clock

Output (2 V/DIV)

Time (10 ns/DIV)

Time (1.25 ns/DIV)

CM

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eria

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Dat

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V/D

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6.10 Typical Charateristics

Note: On the rising edge of each clock period, the CML driveroutputs a low Stop bit, high Start bit, and 33 DC-scrambled databits.

Figure 10. Comparison of Deserializer LVCMOS RX PCLKFigure 9. Serializer CML Driver Output Output Locked to a 78 MHz TX PCLKwith 78 MHZ TX Pixel Clock




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C1

C0

RGB [7:0]

PCLK

24

PLL

Timingand

Control

Inpu

t lat

ch

Par

alle

l to

Ser

ial

DC

Bal

ance

Enc

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HSVSDE

PDBMODE_SEL

HD

CP

Cip

her

SDASCL

3

DOUT -

DOUT +D

REGULATOR

CMF

INTB

I2S_CLKI2S_WC I2S_DA

IDx


7 Detailed Description

7.1 OverviewThe DS90UH925Q-Q1 serializer transmits a 35-bit symbol over a single serial FPD-Link III pair operating up to2.975 Gbps line rate. The serial stream contains an embedded clock, video control signals and DC-balancedvideo data and audio data which enhance signal quality to support AC coupling. The DS90UH925Q-Q1 serializesvideo and audio data then applies encryption through a High-Bandwidth Digital Content Protection (HDCP)Cipher and transmits out through the FPD-Link III interface. Audio encryption is supported. The serializer alsoincludes the HDCP cipher. On board non-volatile memory stores the HDCP keys. All key exchange is conductedover the FPD-Link III bidirectional control interface. The serializer is intended for use with the DS90UH926Q-Q1deserializer, but is also backward compatible with DS90UR906Q or DS90UR908Q FPD-Link II deserializer.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 High Speed Forward Channel Data TransferThe High Speed Forward Channel (HS_FC) is composed of 35 bits of data containing RGB data, sync signals,HDCP, I2C, and I2S audio transmitted from Serializer to Deserializer. Figure 11 illustrates the serial stream perPCLK cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized,balanced and scrambled.

Figure 11. FPD-Link III Serial Stream

The device supports clocks in the range of 5 MHz to 85 MHz. The application payload rate is 2.975 Gbpsmaximum (175 Mbps minimum) with the actual line rate of 2.975 Gbps maximum and 525 Mbps Minimum.




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PCLK IN

PCLK OUT

HS/VS/DE IN

HS/VS/DE OUT

Latency

Pulses 1 or 2 PCLKs wide

Filetered OUT


Feature Description (continued)7.3.2 Low Speed Back Channel Data TransferThe Low-Speed Backward Channel (LS_BC) of the DS90UH925Q-Q1 provides bidirectional communicationbetween the display and host processor. The information is carried back from the Deserializer to the Serializerper serial symbol. The back channel control data is transferred over the single serial link along with the high-speed forward data, DC balance coding and embedded clock information. This architecture provides a backwardpath across the serial link together with a high speed forward channel. The back channel contains the I2C,HDCP, CRC and 4 bits of standard GPIO information with 10 Mbps line rate.

7.3.3 Backward Compatible ModeThe DS90UH925Q-Q1 is also backward compatible to DS90UR906Q and DS90UR908Q FPD Link IIdeserializers at 5-65 MHz of PCLK. It transmits 28-bits of data over a single serial FPD-Link II pair operating atthe line rate of 140 Mbps to 1.82 Gbps. The backward configuration mode can be set via MODE_SEL pin(Table 4) or the configuration register (Table 6). Note: frequency range = 15 - 65MHz when LFMODE = 0 andfrequency range = 5 - <15MHz when LFMODE = 1.

7.3.4 Common Mode Filter Pin (CMF)The serializer provides access to the center tap of the internal termination. A capacitor must be placed on this pinfor additional common-mode filtering of the differential pair. This can be useful in high noise environments foradditional noise rejection capability. A 0.1 μF capacitor must be connected to this pin to Ground.

7.3.5 Video Control Signal FilterWhen operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the followingrestrictions:• Normal Mode with Control Signal Filter Enabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, the transition pulse must be 3 PCLK or longer.• Normal Mode with Control Signal Filter Disabled: DE and HS — Only 2 transitions per 130 clock cycles are

transmitted, no restriction on minimum transition pulse.• VS — Only 1 transition per 130 clock cycles are transmitted, minimum pulse width is 130 clock cycles.

Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signalcan cause a visual display error. This feature allows for the chipset to validate and filter out any high frequencynoise on the control signals. See Figure 12.

Figure 12. Video Control Signal Filter Waveform




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Feature Description (continued)7.3.6 Power Down (PDB)The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin can be controlled by thehost or through the VDDIO, where VDDIO = 3.0V to 3.6V or VDD33. To save power disable the link when the displayis not needed (PDB = LOW). When the pin is driven by the host, make sure to release it after VDD33 and VDDIOhave reached final levels; no external components are required. In the case of driven by the VDDIO = 3.0V to 3.6Vor VDD33 directly, a 10 kohm resistor to the VDDIO = 3.0V to 3.6V or VDD33 , and a >10uF capacitor to the groundare required see Figure 23.

7.3.7 Remote Auto Power Down ModeThe Serializer features a remote auto power down mode. During the power down mode of the pairingdeserializer, the Serializer enters the remote auto power down mode. In this mode, the power dissipation of theSerializer is reduced significantly. When the Deserializer is powered up, the Serializer enters the normal poweron mode automatically. This feature is enabled through the register bit 0x01[7] Table 6.

7.3.8 LVCMOS VDDIO Option1.8V or 3.3V Inputs and Outputs are powered from a separate VDDIO supply to offer compatibility with externalsystem interface signals. Note: When configuring theVDDIO power supplies, all the single-ended data and controlinput pins for device need to scale together with the same operating VDDIO levels.

7.3.9 Input PCLK Loss DetectThe serializer can be programmed to enter a low power SLEEP state when the input clock (PCLK) is lost. Aclock loss condition is detected when PCLK drops below approximately 1MHz. When a PCLK is detected again,the serializer will then lock to the incoming PCLK. Note – when PCLK is lost, the Serial Control Bus Registersvalues are still RETAINED.

7.3.10 Serial Link Fault DetectThe serial link fault detection is able to detect any of following seven (7) conditions1. cable open2. “+” to “-“ short3. “+” short to GND4. “-“ short to GND5. “+” short to battery6. “-“ short to battery7. Cable is linked correctly

If any one of the fault conditions occurs, The Link Detect Status is 0 (cable is not detected) on bit 0 of address0x0C Table 6.

7.3.11 Pixel Clock Edge Select (RFB)The RFB control register bit selects which edge of the Pixel Clock is used. For the serializer, this pin determinesthe edge that the data is latched on. If RFB is HIGH (‘1’), data is latched on the Rising edge of the PCLK. If RFBis LOW (‘0’), data is latched on the Falling edge of the PCLK.

7.3.12 Low Frequency Optimization (LFMODE)The LFMODE is set via register (0x04[1:0]) or MODE_SEL Pin 24 (Table 4). It controls the operating frequencyof the serializer. If LFMODE is Low (default), the PCLK frequency is between 15 MHz and 85 MHz. If LFMODE isHigh, the PCLK frequency is between 5 MHz and <15 MHz. Please note when the device LFMODE is changed,a PDB reset is required.




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Feature Description (continued)7.3.13 Interrupt Pin — Functional Description and Usage (INTB)1. On DS90UH925Q-Q1, set register 0xC6[5] = 1 and 0xC6[0] = 12. DS90UH926Q-Q1 deserializer INTB_IN (pin 16) is set LOW by some downstream device.3. DS90UH925Q-Q1 serializer pulls INTB (pin 31) LOW. The signal is active low, so a LOW indicates an

interrupt condition.4. External controller detects INTB = LOW; to determine interrupt source, read HDCP_ISR register .5. A read to HDCP_ISR will clear the interrupt at the DS90UH925Q-Q1, releasing INTB.6. The external controller typically must then access the remote device to determine downstream interrupt

source and clear the interrupt driving INTB_IN. This would be when the downstream device releases theINTB_IN (pin 16) on the DS90UH926Q-Q1. The system is now ready to return to step (1) at next falling edgeof INTB_IN.

7.3.14 EMI Reduction Features

7.3.14.1 Input SSC Tolerance (SSCT)The DS90UH925Q-Q1 serializer is capable of tracking a triangular input spread spectrum clocking (SSC) profileup to +/-2.5% amplitude deviations (center spread), up to 35 kHz modulation at 5–85 MHz, from a host source.

7.3.14.2 GPIO[3:0] and GPO_REG[8:4]In 18-bit RGB operation mode, the optional R[1:0] and G[1:0] of the DS90UH925Q-Q1 can be used as thegeneral purpose IOs GPIO[3:0] in either forward channel (Inputs) or back channel (Outputs) application.

7.3.14.2.1 GPIO[3:0] Enable Sequence

See Table 1 for the GPIO enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UH925Q-Q1 only.DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.

Step 2: To enable GPIO3 forward channel, write 0x03 to address 0x0F on DS90UH925Q-Q1, then write 0x05 toaddress 0x1F on DS90UH926Q-Q1.

Table 1. GPIO Enable Sequencing Table# DESCRIPTION DEVICE FORWARD BACK

CHANNEL CHANNEL1 Enable 18-bit DS90UH925Q-Q1 0x12 = 0x04 0x12 = 0x04

mode DS90UH926Q-Q1 Auto Load from DS90UH925Q-Q1 Auto Load from DS90UH925Q-Q12 GPIO3 DS90UH925Q-Q1 0x0F = 0x03 0x0F = 0x05

DS90UH926Q-Q1 0x1F = 0x05 0x1F = 0x033 GPIO2 DS90UH925Q-Q1 0x0E = 0x30 0x0E = 0x50

DS90UH926Q-Q1 0x1E = 0x50 0x1E = 0x304 GPIO1 DS90UH925Q-Q1 0x0E = 0x03 0x0E = 0x05

DS90UH926Q-Q1 0x1E = 0x05 0x1E = 0x035 GPIO0 DS90UH925Q-Q1 0x0D = 0x93 0x0D = 0x95

DS90UH926Q-Q1 0x1D = 0x95 0x1D = 0x93

7.3.14.2.2 GPO_REG[8:4] Enable Sequence

GPO_REG[8:4] are the outputs only pins. They must be programmed through the local register bits. See Table 2for the GPO_REG enable sequencing.

Step 1: Enable the 18-bit mode either through the configuration register bit Table 6 on DS90UH925Q-Q1 only.DS90UH926Q-Q1 is automatically configured as in the 18-bit mode.

Step 2: To enable GPO_REG8 outputs an “1”, write 0x90 to address 0x11 on DS90UH925Q-Q1.




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Table 2. GPO_REG Enable Sequencing Table# DESCRIPTION DEVICE LOCAL LOCAL

ACCESS OUTPUT1 Enable 18-bit mode DS90UH925Q-Q1 0x12 = 0x042 GPO_REG8 DS90UH925Q-Q1 0x11 = 0x90 “1”

0x11 = 0x10 “0”3 GPO_REG7 DS90UH925Q-Q1 0x11 = 0x09 “1”



0x10 = 0x01 “0”6 GPO_REG4 DS90UH925Q-Q1 0x0F = 0x90 “1”

0x0F = 0x10 “0”

7.3.14.3 I2S TransmittingIn normal 24-bit RGB operation mode, the DS90UH925Q-Q1 supports 3 bits of I2S. They are I2S_CLK, I2S_WCand I2S_DA. The optionally encrypted and packetized audio information can be transmitted during the videoblanking (data island transport) or during active video (forward channel frame transport). Note: The bit rates ofany I2S bits must maintain one fourth of the PCLK rate. The audio encryption capability is supported per HDCPv1.3.

7.3.14.3.1 Secondary I2S Channel

In I2S Channel B operation mode, the secondary I2S data (I2S_DB) can be used as the additional I2S audio inaddition to the 3–bit of I2S. The I2S_DB input must be synchronized to I2S_CLK and aligned with I2S_DA andI2S_WC at the input to the serializer. This operation mode is enabled through either the MODE_SEL pin(Table 4) or through the register bit 0x12[0] (Table 6). Table 3 below covers the range of I2S sample rates.

Table 3. Audio Interface FrequenciesSAMPLE RATE (kHz) I2S DATA WORD SIZE (bits) I2S CLK (MHz)

32 16 1.02444.1 16 1.41148 16 1.53696 16 3.072

192 16 6.14432 24 1.536

44.1 24 2.11748 24 2.30496 24 4.608

192 24 9.21632 32 2.048

44.1 32 2.82248 32 3.07296 32 6.144

192 32 12.288




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7.3.14.4 HDCPThe Cipher function is implemented in the serializer per HDCP v1.3 specification. The DS90UH925Q-Q1provides HDCP encryption of audiovisual content when connected to an HDCP capable FPD-Link III deserializersuch as the DS90UH926Q-Q1. HDCP authentication and shared key generation is performed using the HDCPControl Channel which is embedded in the forward and backward channels of the serial link. An on-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during themanufacturing process and are not accessible external to the device.

The DS90UH925Q-Q1 uses the Cipher engine to encrypt the data as per HDCP v1.3. The encrypted data istransmitted through the FPD-Link III interface.

7.3.14.5 Built In Self Test (BIST)An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high speed serial link and thelow- speed back channel. This is useful in the prototype stage, equipment production, in-system test and also forsystem diagnostics. Note: BIST not available in backwards compatible mode.

7.3.14.5.1 BIST Configuration and Status

The BIST mode is enabled at the deseralizer by the Pin select (Pin 44 BISTEN and Pin 16 BISTC) orconfiguration register (Table 6) through the deserializer. When LFMODE = 0, the pin based configuration defaultsto external PCLK or 33 MHz internal Oscillator clock (OSC) frequency. In the absence of PCLK, the user canselect the desired OSC frequency (default 33 MHz or 25MHz) through the register bit. When LFMODE = 1, thepin based configuration defaults to external PCLK or 12.5MHz MHz internal Oscillator clock (OSC) frequency.

When BISTEN of the deserializer is high, the BIST mode enable information is sent to the serializer through theBack Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the testpattern and monitors it for errors. The PASS output pin toggles to flag any payloads that are received with 1 to35 bit errors.

The BIST status is monitored real time on PASS pin. The result of the test is held on the PASS output until reset(new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASSindicates one or more errors were detected. The duration of the test is controlled by the pulse width applied tothe deserializer BISTEN pin. This BIST feature also contains a Link Error Count and a Lock Status. If theconnection of the serial link is broken, then the link error count is shown in the register. When the PLL of thedeserializer is locked or unlocked, the lock status can be read in the register. See Table 6.

7.3.14.5.1.1 Sample BIST Sequence

See Figure 13 for the BIST mode flow diagram.

Step 1: For the DS90UH925Q-Q1 and DS90UH926Q-Q1 FPD-Link III chipset, BIST Mode is enabled via theBISTEN pin of DS90UH926Q-Q1 FPD-Link III deserializer. The desired clock source is selected through BISTCpin.

Step 2: The DS90UH925Q-Q1 serializer is woken up through the back channel if it is not already on. The allzero pattern on the data pins is sent through the FPD-Link III to the deserializer. Once the serializer and thedeserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high andBIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch lowfor one half of the clock period. During the BIST test, the PASS output can be monitored and counted todetermine the payload error rate.

Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking thedata. The final test result is held on the PASS pin. If the test ran error free, the PASS output will be High. If therewas one or more errors detected, the PASS output will be Low. The PASS output state is held until a new BISTis run, the device is RESET, or Powered Down. The BIST duration is user controlled by the duration of theBISTEN signal.




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X XX

PCLK(RFB = L)

BISTEN(DES)

PASS

DATA(internal)

PASS

BIST Duration

Prior Result

BIST ResultHeld

PASS

FAIL

X = bit error(s)

RGB[7:0]HS, VS, DE

DATA(internal)

Case 1 - P

assC

ase 2 - Fail

Prior Result

Normal SSO BIST Test Normal

DE

S O

utputs

BISTstart

BISTstop

BISTWait

Step 1: DES in BIST

Step 2: Wait, SER in BIST

Step 3: DES in Normal Mode - check PASS

Step 4: DES/SER in Normal

Normal


Step 4: The Link returns to normal operation after the deserializer BISTEN pin is low. Figure 14 shows thewaveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multipleerrors. In most cases it is difficult to generate errors due to the robustness of the link (differential datatransmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,reducing signal condition enhancements (Rx Equalization).

Figure 13. BIST Mode Flow Diagram

7.3.14.5.2 Forward Channel and Back Channel Error Checking

While in BIST mode, the serializer stops sampling RGB input pins and switches over to an internal all-zeropattern. The internal all-zeroes pattern goes through scrambler, dc-balancing etc. and goes over the serial link tothe deserializer. The deserializer on locking to the serial stream compares the recovered serial stream with all-zeroes and records any errors in status registers and dynamically indicates the status on PASS pin. Thedeserializer then outputs a SSO pattern on the RGB output pins.

The back-channel data is checked for CRC errors once the serializer locks onto back-channel serial stream asindicated by link detect status (register bit 0x0C[0]). The CRC errors are recorded in an 8-bit register. Theregister is cleared when the serializer enters the BIST mode. As soon as the serializer exits BIST mode, thefunctional mode CRC register starts recording the CRC errors. The BIST mode CRC error register is active inBIST mode only and keeps the record of last BIST run until cleared or enters BIST mode again.

Figure 14. BIST Waveforms




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SERR4

MODE_SEL

R3

VR4

VDD33


7.3.14.6 Internal Pattern GenerationThe DS90UH925Q-Q1 serializer supports the internal pattern generation feature. It allows basic testing anddebugging of an integrated panel through the FPD-Link III output stream. The test patterns are simple andrepetitive and allow for a quick visual verification of panel operation. As long as the device is not in power downmode, the test pattern will be displayed even if no parallel input is applied. If no PCLK is received, the testpattern can be configured to use a programmed oscillator frequency. For detailed information, refer to SNLA132.

7.4 Device Functional Modes

7.4.1 Configuration Select (MODE_SEL)Configuration of the device may be done via the MODE_SEL input pin, or via the configuration register bit. A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SELinput (VR4) and VDD33 to select one of the other 10 possible selected modes. See Figure 15 and Table 4.

Figure 15. MODE_SEL Connection Diagram




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Device Functional Modes (continued)Table 4. Configuration Select (MODE_SEL)

# IDEAL IDEAL VR4 SUGGESTED SUGGESTED LFMODE REPEATER BACKWARD I2SRATIO (V) RESISTOR RESISTOR COMPA- CHANNEL B

VR4/VDD33 R3 kΩ (1% tol) R4 kΩ (1% tol) TIBLE (18–bitMODE)

1 0 0 Open 40.2 or Any L L L L2 0.164 0.541 255 49.9 L H L L3 0.221 0.729 243 69.8 L H L H4 0.285 0.941 237 95.3 H L L L5 0.359 1.185 196 110 H L L H6 0.453 1.495 169 140 H H L L7 0.539 1.779 137 158 H H L H8 0.728 2.402 90.9 243 H L H* L

LFMODE:L = frequency range is 15 – 85 MHz (Default)H = frequency range is 5 – <15 MHz

Repeater:L = Repeater OFF (Default)H = Repeater ON

Backward Compatible:L = Backward Compatible is OFF (Default)H = Backward Compatible is ON; DES = DS90UR906Q or DS90UR916Q or DS90UR908Q

– frequency range = 15 - 65 MHz when LFMODE = 0– frequency range = 5 - <15 MHz when LFMODE = 1

I2S Channel B:L = I2S Channel B is OFF, Normal 24-bit RGB Mode (Default)H = I2S Channel B is ON, 18-bit RGB Mode with I2S_DB Enabled. Note: use of GPIO(s) on unused inputs must be enabled by register.

7.4.2 HDCP RepeaterWhen DS90UH925Q-Q1 and DS90UH926Q-Q1 are configured as the HDCP Repeater application, it provides amechanism to extend HDCP transmission over multiple links to multiple display devices. This repeaterapplication provides a mechanism to authenticate all HDCP Receivers in the system and distribute protectedcontent to the HDCP Receivers using the encryption mechanisms provided in the HDCP specification.




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TXSource

TX

TX

RX

1:3 Repeater

TX

TX

TX

RX

1:3 Repeater

TX

TX

TX

RX

1:3 Repeater

TX

TX

TX

RX

1:3 Repeater

TX

RX Display

RX Display

RX Display

RX Display

RX Display

RX Display

RX Display

RX Display

RX Display


7.4.3 Repeater ConfigurationIn HDCP repeater application, In this document, the DS90UH925Q-Q1 is referred to as the HDCP Transmitter ortransmit port (TX), and the DS90UH926Q-Q1 is referred to as the HDCP Receiver (RX). Figure 16 shows themaximum configuration supported for HDCP Repeater implementations using the DS90UH925Q-Q1 (TX) andDS90UH926Q-Q1 (RX). Two levels of HDCP Repeaters are supported with a maximum of three HDCPTransmitters per HDCP Receiver.

Figure 16. HDCP Maximum Repeater Application

To support HDCP Repeater operation, the DS90UH926Q-Q1 Deserializer includes the ability to control thedownstream authentication process, assemble the KSV list for downstream HDCP Receivers, and pass the KSVlist to the upstream HDCP Transmitter. An I2C master within the DS90UH926Q-Q1 communicates with the I2Cslave within the DS90UH925Q-Q1 Serializer. The DS90UH925Q-Q1 Serializer handles authenticating with adownstream HDCP Receiver and makes status available through the I2C interface. The DS90UH926Q-Q1monitors the transmit port status for each DS90UH925Q-Q1 and reads downstream KSV and KSV list valuesfrom the DS90UH925Q-Q1.

In addition to the I2C interface used to control the authentication process, the HDCP Repeater implementationincludes two other interfaces. A parallel LVCMOS interface provides the unencrypted video data in 24-bit RGBformat and includes the DE/VS/HS control signals. In addition to providing the RGB video data, the parallelLVCMOS interface communicates control information and packetized audio data during video blanking intervals.A separate I2S audio interface may optionally be used to send I2S audio data between the HDCP Receiver andHDCP Transmitter in place of using the packetized audio over the parallel LVCMOS interface. All audio andvideo data is decrypted at the output of the HDCP Receiver and is re-encrypted by the HDCP Transmitter.




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R[7:0]

G[7:0]

B[7:0]

DE

VS

HS

I2S_CLK

I2S_WC

I2S_DA

INTB_IN

SDA

SCL

DS90UH925Q-Q1

R[7:0]

G[7:0]

B[7:0]

DE

VS

HS

I2S_CLK

I2S_WC

I2S_DA

INTB

SDA

SCL

MODE_SEL

ID[x]

MODE_SEL

ID[x]

VDD33

VDD33VDD33

VDD33

VDD33

VDDIO

Optional

DS90UH926Q-Q1

I2CMaster

upstreamTransmitter

HDCP TransmitterDS90UH925Q-Q1

I2CSlave

HDCP ReceiverDS90UH926Q-Q1

ParallelLVCMOS

I2S Audio

I2C

HDCP TransmitterDS90UH925Q-Q1

I2CSlave

downstreamReceiverorRepeater

downstreamReceiverorRepeater

FPD-Link III interfaces


Figure 17 provides more detailed block diagram of a 1:2 HDCP repeater configuration.

Figure 17. HDCP 1:2 Repeater Configuration

7.4.4 Repeater ConnectionsThe HDCP Repeater requires the following connections between the HDCP Receiver and each HDCPTransmitter Figure 18.1. Video Data – Connect PCLK, RGB and control signals (DE, VS, HS).2. I2C – Connect SCL and SDA signals. Both signals should be pulled up to VDD33 with 4.7 kΩ resistors.3. Audio – Connect I2S_CLK, I2S_WC, and I2S_DA signals.4. IDx pin – Each HDCP Transmitter and Receiver must have an unique I2C address.5. MODE_SEL pin – All HDCP Transmitter and Receiver must be set into the Repeater Mode.6. Interrupt pin – Connect DS90UH926Q-Q1 INTB_IN pin to DS90UH925Q-Q1 INTB pin. The signal must be

pulled up to VDDIO.

Figure 18. HDCP Repeater Connection Diagram




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HOSTor

Salve

SERor

DESSCL

SDA

4.7k 4.7k R2

SCL

SDA

To other Devices

IDx

VDD33

R1VDD33

VR2


7.5 Programming

7.5.1 Serial Control BusThe DS90UH925Q-Q1 is configured by the use of a serial control bus that is I2C protocol compatible. This bus isalso used by the Host source to control and monitor status of the HDCP function. Multiple serializer devices mayshare the serial control bus since 16 device addresses are supported. Device address is set via R1 and R2values on IDx pin. See Figure 19 below.

The serial control bus consists of two signals and a configuration pin. The SCL is a Serial Bus Clock Input /Output. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an externalpull-up resistor to VDD33. For most applications a 4.7 k pull-up resistor to VDD33 may be used. The resistor valuemay be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or drivenLow.

Figure 19. Serial Control Bus Connection

The configuration pin is the IDx pin. This pin sets one of 9 possible device addresses. A pull-up resistor and apull-down resistor of suggested values may be used to set the voltage ratio of the IDx input (VR2) and VDD33 toselect one of the other 9 possible addresses. Table 5 defines the required VR2 and VR2/VDD33 ratios, andsuggests standard resistor values to achieve these ratios. In systems where excessive noise may be present, werecommend reducing the resistor values (by a factor of 10x or 100x) while maintaining the required ratio. Thisprovides tighter coupling to supply rails, and more stability of VR2 in the presence of coupled noise. Note thatreducing the resistor values will increase the current consumed by the resistor divider. See Table 5.

Table 5. Serial Control Bus Addresses for IDxIDEAL SUGGESTED SUGGESTEDIDEAL VR2 ADDRESS 8'b# RATIO RESISTOR RESISTOR ADDRESS 7'b(V) APPENDEDVR2 / VDD33 R1 kΩ (1% tol) R2 kΩ (1% tol)

1 0 0 Open 40.2 or Any 0x0C 0x182 0.121 0.399 294 40.2 0x0D 0x1A3 0.152 0.502 280 49.9 0x0E 0x1C4 0.180 0.594 137 30.1 0x0F 0x1E5 0.208 0.685 118 30.9 0x10 0x206 0.303 0.999 115 49.9 0x13 0x267 0.345 1.137 102 53.6 0x14 0x288 0.389 1.284 115 73.2 0x15 0x2A9 0.727 2.399 90.9 243 0x1B 0x36




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Slave Address Register Address Data

S 0ack

ack

ack P

A0

A1

A2

Slave Address Register Address Slave Address Data

S 0 1ack

ack

ack

ackS P

A0

A1

A2

A1

A2

A0

SDA

SCL

START condition, orSTART repeat condition

STOP condition

S P


The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs whenSCL transitions Low while SDA is High. A STOP occurs when SDA transition High while SCL is also HIGH. SeeFigure 20.

Figure 20. START and STOP Conditions

To communicate with a remote device, the host controller (master) sends the slave address and listens for aresponse from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus isaddressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn'tmatch a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKsalso occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs afterevery data byte is successfully received. When the master is reading data, the master ACKs after every databyte is received to let the slave know it wants to receive another data byte. When the master wants to stopreading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the busbegins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stopcondition. A READ is shown in Figure 21 and a WRITE is shown in Figure 22.

If the Serial Bus is not required, the three pins may be left open (NC).

Figure 21. Serial Control Bus — READ

Figure 22. Serial Control Bus — WRITE




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7.6 Register Maps

Table 6. Serial Control Bus RegistersREG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE

0 0x00 I2C Device ID 7:1 RW Device ID 7–bit address of Serializer0 RW ID Setting I2C ID Setting

1: Register I2C Device ID (Overrides IDx pin)0: Device ID is from IDx pin

1 0x01 Reset 7 RW 0x00 Remote Remote Auto Power DownAuto Power 1: Power down when no Bidirectional ControlDown Channel link is detected

0: Do not power down when no Bidirectional ControlChannel link is detected

6:2 Reserved.1 RW Digital Reset the entire digital block including registers

RESET1 This bit is self-clearing.1: Reset0: Normal operation

0 RW Digital Reset the entire digital block except registersRESET0 This bit is self-clearing

1: Reset0: Normal operation

3 0x03 Configuration 7 RW 0xD2 Back Back Channel Check Enable[0] channel 1: Enable

CRC 0: DisableCheckerEnable

6 Reserved.5 RW I2C Remote Automatically Acknowledge I2C Remote Write

Write Auto When enabled, I2C writes to the Deserializer (orAcknowledg any remote I2C Slave, if I2C PASS ALL is enabled)e are immediately acknowledged without waiting for

the Deserializer to acknowledge the write. Thisallows higher throughput on the I2C bus1: Enable0: Disable

4 RW Filter HS, VS, DE two clock filter When enabled, pulsesEnable less than two full PCLK cycles on the DE, HS, and

VS inputs will be rejected1: Filtering enable0: Filtering disable

3 RW I2C Pass- I2C Pass-Through Modethrough 1: Pass-Through Enabled

0: Pass-Through Disabled2 Reserved1 RW PCLK Auto Switch over to internal OSC in the absence of PCLK

1: Enable auto-switch0: Disable auto-switch

0 RW TRFB Pixel Clock Edge Select1: Parallel Interface Data is strobed on the RisingClock Edge.0: Parallel Interface Data is strobed on the FallingClock Edge.




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Register Maps (continued)Table 6. Serial Control Bus Registers (continued)

REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE4 0x04 Configuration 7 RW 0x80 Failsafe Input Failsafe State

[1] State 1: Failsafe to Low0: Failsafe to High

6 Reserved5 RW CRC Error Clear back channel CRC Error Counters

Reset This bit is NOT self-clearing1: Clear Counters0: Normal Operation

4 Reserved3 RW Backward Backward Compatible (BC) mode set by

Compatible MODE_SEL pin or registerselect by 1: BC is set by register bit. Use register bitpin or reg_0x04[2] to set BC Moderegister 0: BC is set by MODE_SEL pin.control

2 RW Backward Backward compatible (BC) mode to DS90UR906QCompatible or DS90UR908Q, if reg_0x04[3] = 1Mode 1: Backward compatible with DS90UR906Q orSelect DS90UR908Q

0: Backward Compatible is OFF (default)1 RW LFMODE Frequency range is set by MODE_SEL pin or

select by registerpin or 1: Frequency range is set by register. Use registerregister bit reg_0x04[0] to set LFMODEcontrol 0: Frequency range is set by MODE_SEL pin.

0 RW LFMODE Frequency range select1: PCLK range = 5MHz - <15 MHz), if reg_0x04[1] =10: PCLK range = 15MHz - 85MHz (default)

5 0x05 I2C Control 7:5 0x00 Reserved4:3 RW SDA Output SDA output delay

Delay Configures output delay on the SDA output. Settingthis value will increase output delay in units of 40ns.Nominal output delay values for SCL to SDA are00: 240ns01: 280ns10: 320ns11: 360ns

2 RW Local Write Disable remote writes to local registersDisable Setting the bit to a 1 prevents remote writes to local

device registers from across the control channel. Itprevents writes to the Serializer registers from anI2C master attached to the Deserializer.Setting this bit does not affect remote access to I2Cslaves at the Serializer

1 RW I2C Bus Speed up I2C bus watchdog timerTimer 1: Watchdog timer expires after ~50 ms.Speedup 0: Watchdog Timer expires after ~1 s

0 RW I2C Bus Disable I2C bus watchdog timertimer When the I2C watchdog timer may be used toDisable detect when the I2C bus is free or hung up following

an invalid termination of a transaction.If SDA is high and no signalling occurs for ~1 s, theI2C bus assumes to be free. If SDA is low and nosignaling occurs, the device attempts to clear thebus by driving 9 clocks on SCL




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE6 0x06 DES ID 7:1 RW 0x00 DES Device 7-bit Deserializer Device ID

ID Configures the I2C Slave ID of the remoteDeserializer. A value of 0 in this field disables I2Caccess to the remote Deserializer. This field isautomatically configured by the Bidirectional ControlChannel once RX Lock has been detected.Software may overwrite this value, but should alsoassert the FREEZE DEVICE ID bit to preventoverwriting by the Bidirectional Control Channel.

0 RW Device ID Freeze Deserializer Device IDFrozen Prevents autoloading of the Deserializer Device ID

by the Bidirectional Control Channel. The ID will befrozen at the value written.

7 0x07 Slave ID 7:1 RW 0X00 Slave 7-bit Remote Slave Device IDDevice ID Configures the physical I2C address of the remote

I2C Slave device attached to the remoteDeserializer. If an I2C transaction is addressed tothe Slave Device Alias ID, the transaction will beremapped to this address before passing thetransaction across the Bidirectional Control Channelto the Deserializer

0 Reserved8 0x08 Slave Alias 7:1 RW 0x00 Slave 7-bit Remote Slave Device Alias ID

Device Assigns an Alias ID to an I2C Slave device attachedAlias ID to the remote Deserializer. The transaction will be

remapped to the address specified in the Slave IDregister. A value of 0 in this field disables access tothe remote I2C Slave.

0 Reserved10 0x0A CRC Errors 7:0 R 0x00 CRC Error Number of back channel CRC errors – 8 least

LSB significant bits11 0x0B 7:0 R 0x00 CRC Error Number of back channel CRC errors – 8 most

MSB significant bits12 0x0C General Status 7:4 0x00 Reserved

3 R BIST CRC Back channel CRC error during BISTError communication with Deserializer.

The bit is cleared upon loss of link, restart of BIST,or assertion of CRC ERROR RESET in register0x04.

2 R PCLK PCLK StatusDetect 1: Valid PCLK detected

0: Valid PCLK not detected1 R DES Error Back channel CRC error during communication with

Deserializer.The bit is cleared upon loss of link or assertion ofCRC ERROR RESET in register 0x04.

0 R LINK Detect LINK Status1: Cable link detected0: Cable link not detected (Fault Condition)




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE13 0x0D Revision ID and 7:4 R 0xA0 Rev-ID Revision ID: 1010

GPIO0 Production DeviceConfiguration 3 RW GPIO0 Local GPIO output value

Output This value is output on the GPIO pin when theValue GPIO function is enabled, the local GPIO direction

is Output, and remote GPIO control is disabled.2 RW GPIO0 Remote GPIO control

Remote 1: Enable GPIO control from remote Deserializer.Enable The GPIO pin will be an output, and the value is

received from the remote Deserializer.0: Disable GPIO control from remote Deserializer.

1 RW GPIO0 Local GPIO DirectionDirection 1: Input

0: Output0 RW GPIO0 GPIO function enable

Enable 1: Enable GPIO operation0: Enable normal operation

14 0x0E GPIO2 and 7 RW 0x0 GPIO2 Local GPIO output valueGPIO1 Output This value is output on the GPIO pin when theConfigurations Value GPIO function is enabled, the local GPIO direction







3 RW GPIO1 Local GPIO output valueOutput This value is output on the GPIO pin when theValue GPIO function is enabled, the local GPIO direction










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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE15 0x0F GPO_REG4 7 RW 0x00 GPO_REG Local GPO_REG4 output value

and GPIO3 4 Output This value is output on the GPO pin when the GPOConfigurations Value function is enabled.

(The local GPO direction is Output, and remoteGPO control is disabled)

6:5 Reserved4 RW GPO_REG GPO_REG4 function enable

4 Enable 1: Enable GPO operation0: Enable normal operation

3 RW GPIO3 Local GPIO output valueOutput This value is output on the GPIO pin when theValue GPIO function is enabled, the local GPIO direction







16 0x10 GPO_REG6 7 RW 0x00 GPO_REG Local GPO_REG6 output valueand 6 Output This value is output on the GPO pin when the GPOGPO_REG5 Value function is enabled.Configurations (The local GPO direction is Output, and remote

GPO control is disabled)6:5 Reserved4 RW GPO_REG GPO_REG6 function enable


3 RW GPO_REG Local GPO_REG5 output value5 Output This value is output on the GPO pin when the GPOValue function is enabled, the local GPO direction is

Output, and remote GPO control is disabled.2:1 Reserved0 RW GPO_REG GPO_REG5 function enable





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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE17 0x11 GPO_REG8 7 RW 0x00 GPO_REG Local GPO_REG8 output value

and 8 Output This value is output on the GPO pin when the GPOGPO_REG7 Value function is enabled.Configurations (The local GPO direction is Output, and remote

GPO control is disabled)6:5 Reserved4 RW GPO_REG GPO_REG8 function enable


3 RW GPO_REG Local GPO_REG7 output value7 Output This value is output on the GPO pin when the GPOValue function is enabled, the local GPO direction is

Output, and remote GPO control is disabled.2:1 Reserved0 RW GPO_REG GPO_REG7 function enable


18 0x12 Data Path 7 0x00 ReservedControl 6 RW Pass RGB Setting this bit causes RGB data to be sent

independent of DE.It allows operation in systems which may not useDE to frame video data or send other data when DEis de-asserted.Note that setting this bit prevents HDCP operationand blocks packetized audio.This bit does not need to be set in BackwardsCompatible mode1: Pass RGB independent of DE0: Normal operation(DE gates RGB data transmission - RGB data istransmitted only when DE is active)

5 RW DE Polarity The bit indicates the polarity of the Data Enable(DE) signal.1: DE is inverted (active low, idle high)0: DE is positive (active high, idle low)

4 RW I2S I2S Repeater RegenerationRepeater 1: Repeater regenerate I2S from I2S pinsRegenerati 0: Repeater pass through I2S from video pinson

3 RW I2S I2S Channel B EnableChannel B 1: Set I2S Channel B Enable from reg_0x12[0]Enable 0: Set I2S Channel B Enable from MODE_SEL pinOverride

2 RW 18-bit Video 18–bit video selectSelect 1: Select 18-bit video mode

Note: use of GPIO(s) on unused inputs must beenabled by register.0: Select 24-bit video mode

1 RW I2S I2S Transport Mode SelectTransport 1: Enable I2S Data Forward Channel FrameSelect Transport

0: Enable I2S Data Island Transport0 RW I2S I2S Channel B Enable

Channel B 1: Enable I2S Channel B on B1 inputEnable 0: I2S Channel B disabled




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE19 0x13 Mode Status 7:5 0x10 Reserved

4 R MODE_SE MODE_SEL StatusL 1: MODE_SEL decode circuit is completed

0: MODE_SEL decode circuit is not completed3 R Low Low Frequency Mode Status

Frequency 1: Low frequency (5 - <15 MHz)Mode 0: Normal frequency (15 - 85 MHz)

2 R Repeater Repeater Mode StatusMode 1: Repeater mode ON

0: Repeater Mode OFF1 R Backward Backward Compatible Mode Status

Compatible 1: Backward compatible ONMode 0: Backward compatible OFF

0 R I2S I2S Channel B Mode StatusChannel B 1: I2S Channel B ON, 18-bit RGB mode withMode I2S_DB enabled

0: I2S Channel B OFF; normal 24-bit RGB mode20 0x14 Oscillator Clock 7:3 0x00 Reserved

Source and 2:1 RW OSC Clock OSC Clock SourceBIST Status Source (When LFMODE = 1, Oscillator = 12.5MHz ONLY)00: External Pixel Clock01: 33 MHz Oscillator10: Reserved11: 25 MHz Oscillator

0 R BIST BIST statusEnable 1: EnabledStatus 0: Disabled

22 0x16 BCC Watchdog 7:1 RW 0xFE Timer Value The watchdog timer allows termination of a controlControl channel transaction if it fails to complete within a

programmed amount of time.This field sets the Bidirectional Control ChannelWatchdog Timeout value in units of 2 ms.This field should not be set to 0

0 RW Timer Disable Bidirectional Control Channel WatchdogControl Timer

1: Disables BCC Watchdog Timer operation0: Enables BCC Watchdog Timer operation

23 0x17 I2C Control 7 RW 0x5E I2C Pass I2C ControlAll 1: Enable Forward Control Channel pass-through of

all I2C accesses to I2C Slave IDs that do not matchthe Serializer I2C Slave ID.0: Enable Forward Control Channel pass-throughonly of I2C accesses to I2C Slave IDs matchingeither the remote Deserializer Slave ID or theremote Slave ID.

6 Reserved5:4 RW SDA Hold Internal SDA Hold Time

Time Configures the amount of internal hold timeprovided for the SDA input relative to the SCL input.Units are 40 ns

3:0 RW I2C Filter Configures the maximum width of glitch pulses onDepth the SCL and SDA inputs that will be rejected. Units

are 5 ns




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE24 0x18 SCL High Time 7:0 RW 0xA1 SCL HIGH I2C Master SCL High Time

Time This field configures the high pulse width of the SCLoutput when the Serializer is the Master on the localI2C bus. Units are 40 ns for the nominal oscillatorclock frequency. The default value is set to providea minimum 5us SCL high time with the internaloscillator clock running at 32.5MHz rather than thenominal 25MHz.

25 0x19 SCL Low Time 7:0 RW 0xA5 SCL LOW I2C SCL Low TimeTime This field configures the low pulse width of the SCL

output when the Serializer is the Master on the localI2C bus. This value is also used as the SDA setuptime by the I2C Slave for providing data prior toreleasing SCL during accesses over theBidirectional Control Channel. Units are 40 ns forthe nominal oscillator clock frequency. The defaultvalue is set to provide a minimum 5us SCL low timewith the internal oscillator clock running at 32.5MHzrather than the nominal 25MHz.

27 0x1B BIST BC Error 7:0 R 0x00 BIST Back BIST Mode Back Channel CRC Error CounterChannel This error counter is active only in the BIST mode. ItCRC Error clears itself at the start of the BIST run.Counter

100 0x64 Pattern 7:4 RW 0x10 Pattern Fixed Pattern SelectGenerator Generator This field selects the pattern to output when in FixedControl Select Pattern Mode. Scaled patterns are evenly

distributed across the horizontal or vertical activeregions. This field is ignored when Auto-ScrollingMode is enabled. The following table shows thecolor selections in non-inverted followed by invertedcolor mode0000: Reserved0001: White/Black0010: Black/White0011: Red/Cyan0100: Green/Magenta0101: Blue/Yellow0110: Horizontally Scaled Black to White/White toBlack0111: Horizontally Scaled Black to Red/Cyan toWhite1000: Horizontally Scaled Black to Green/Magentato White1001: Horizontally Scaled Black to Blue/Yellow toWhite1010: Vertically Scaled Black to White/White toBlack1011: Vertically Scaled Black to Red/Cyan to White1100: Vertically Scaled Black to Green/Magenta toWhite1101: Vertically Scaled Black to Blue/Yellow toWhite1110: Custom color (or its inversion) configured inPGRS, PGGS, PGBS registers1111: Reserved

3:1 Reserved0 RW Pattern Pattern Generator Enable

Generator 1: Enable Pattern GeneratorEnable 0: Disable Pattern Generator




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE101 0x65 Pattern 7:5 0x00 Reserved

Generator 4 RW Pattern 18-bit Mode SelectConfiguration Generator 1: Enable 18-bit color pattern generation. Scaled18 Bits patterns will have 64 levels of brightness and the R,

G, and B outputs use the six most significant colorbits.0: Enable 24-bit pattern generation. Scaled patternsuse 256 levels of brightness.

3 RW Pattern Select External Clock SourceGenerator 1: Selects the external pixel clock when usingExternal internal timing.Clock 0: Selects the internal divided clock when using

internal timingThis bit has no effect in external timing mode(PATGEN_TSEL = 0).

2 RW Pattern Timing Select ControlGenerator 1: The Pattern Generator creates its own videoTiming timing as configured in the Pattern Generator TotalSelect Frame Size, Active Frame Size. Horizontal Sync

Width, Vertical Sync Width, Horizontal Back Porch,Vertical Back Porch, and Sync Configurationregisters.0: the Pattern Generator uses external video timingfrom the pixel clock, Data Enable, Horizontal Sync,and Vertical Sync signals.

1 RW Pattern Enable Inverted Color PatternsGenerator 1: Invert the color output.Color Invert 0: Do not invert the color output.

0 RW Pattern Auto-Scroll Enable:Generator 1: The Pattern Generator will automatically move toAuto-Scroll the next enabled pattern after the number of framesEnable specified in the Pattern Generator Frame Time

(PGFT) register.0: The Pattern Generator retains the current pattern.

102 0x66 Pattern 7:0 RW 0x00 Indirect This 8-bit field sets the indirect address forGenerator Address accesses to indirectly-mapped registers. It shouldIndirect Address be written prior to reading or writing the Pattern

Generator Indirect Data register.See AN-2198 (SNLA132)

103 0x67 Pattern 7:0 RW 0x00 Indirect When writing to indirect registers, this registerGenerator Data contains the data to be written. When reading fromIndirect Data indirect registers, this register contains the read

back value.See AN-2198 ( SNLA132)

128 0x80 RX_BKSV0 7:0 R 0x00 RX BKSV0 BKSV0: Value of byte 0 of the Deserializer KSV129 0x81 RX_BKSV1 7:0 R 0x00 RX BKSV1 BKSV1: Value of byte 1 of the Deserializer KSV130 0x82 RX_BKSV2 7:0 R 0x00 RX BKSV2 BKSV2: Value of byte 2 of the Deserializer KSV131 0x83 RX_BKSV3 7:0 R 0x00 RX BKSV3 BKSV3: Value of byte 3of the Deserializer KSV132 0x84 RX_BKSV4 7:0 R 0x00 RX BKSV4 BKSV4: Value of byte 4of the Deserializer KSV144 0x90 TX_KSV0 7:0 R 0x00 TX KSV0 KSV0: Value of byte 0 of the Serializer KSV145 0x91 TX_KSV1 7:0 R 0x00 TX KSV1 KSV1: Value of byte 1 of the Serializer KSV146 0x92 TX_KSV2 7:0 R 0x00 TX KSV2 KSV2: Value of byte 2 of the Serializer KSV147 0x93 TX_KSV3 7:0 R 0x00 TX KSV3 KSV3: Value of byte 3 of the Serializer KSV148 0x94 TX_KSV4 7:0 R 0x00 TX KSV4 KSV4: Value of byte 4 of the Serializer KSV




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE160 0xA0 RX BCAPS 7 0x13 Reserved

6 R Repeater Indicates if the attached Receiver supportsdownstream connections. This bit is valid once theBksv is ready as indicated by the BKSV_RDY bit inthe HDCP

5 R KSV FIFO KSV FIFO ReadyIndicates the receiver has built the list of attachedKSVs and computed the verification value

4 R Fast I2C Fast I2C: The HDCP Receiver supports fast I2C.Since the I2C is embedded in the serial data, this bitis not relevant

3:2 Reserved1 R Features HDCP v1.1_Features

The HDCP Receiver supports the EnhancedEncryption Status Signaling (EESS), AdvanceCipher, and Enhanced Link Verification options.

0 R Fast Re- The HDCP Receiver is capable of receivingauth (unencrypted) video signal during the session re-

authentication.161 0xA1 RX BSTATUS0 7 R 0x00 Max Maximum Devices Exceeded: Indicates a topology

Devices error was detected. Indicates the number ofdownstream devices has exceeded the depth of theRepeater's KSV FIFO

6:0 R Device Total number of attached downstream device. For aCount Repeater, this will indicate the number of

downstream devices, not including the Repeater.For an HDCP Receiver that is not also a Repeater,this field will be 0

162 0xA2 RX BSTATUS1 7:4 0x00 Reserved3 R Max Maximum Cascade Exceeded: Indicates a topology

Cascade error was detected. Indicates that more than sevenlevels of repeaters have been cascad-ed together

2:0 R Cascade Indicates the number of attached levels of devicesDepth for the Repeater

163 0xA3 KSV FIFO 7:0 R 0x00 KSV FIFO KSV FIFOEach read of the KSV FIFO returns one byte of theKSV FIFO list composed by the downstreamReceiver.




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE192 0xC0 HDCP DBG 7:4 0x00 Reserved

3 RW RGB Enable RGB video line checksumCHKSUM Enables sending of ones-complement checksum for

each 8-bit RBG data channel following end of eachvideo data line

2 RW Fast LV Fast Link VerificationHDCP periodically verifies that the HDCP Receiveris correctly synchronized. Setting this bit willincrease the rate at which synchronization isverified. When set to a 1, Pj is computed every 2frames and Ri is computed every 16 frames. Whenset to a 0, Pj is computed every 16 frames and Ri iscomputed every 128 frames.

1 RW TMR Speed Timer SpeedupUp Speed up HDCP authentication timers.

0 RW HDCP I2C HDCP I2C Fast Mode EnableFast Setting this bit to a 1 will enable the HDCP I2C

Master in the HDCP Receiver to operate with Fastmode timing. If set to a 0, the I2C Master willoperate with Standard mode timing. This bit ismirrored in the IND_STS register




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE194 0xC2 HDCP CFG 7 RW 0x80 ENH LV Enable Enhanced Link Verification

Allows checking of the encryption Pj value on every16th frame1: Enhanced Link Verification enabled0: Enhanced Link Verification disabled

6 RW HDCP Enables Enhanced Encryption Status SignalingEESS (EESS) instead of the Original Encryption Status

Signaling (OESS)1: EESS mode enabled0: OESS mode enabled

5 RW TX RPTR Transmit Repeater EnableEnables the transmitter to act as a repeater. In thismode, the HDCP Transmitter incorporates theadditional authentication steps required of an HDCPRepeater.1: Transmit Repeater mode enabled0: Transmit Repeater mode disabled

4:3 RW ENC Mode Encryption Control ModeDetermines mode for controlling whether encryptionis required for video frames00: Enc_Authenticated01: Enc_Reg_Control10: Enc_Always11: Enc_InBand_Control (per frame)If the Repeater strap option is set at power-up,Enc_InBand_Control (ENC_MODE == 11) will bese-lected. Otherwise, the default will beEnc_Authenticated mode (ENC_MODE == 00).

2 RW Wait Enable 100ms WaitThe HDCP 1.3 specification allows for a 100ms waitto allow the HDCP Receiver to compute the initialencryption values. The FPD-Link III implementationensures that the Receiver will complete thecomputations before the HDCP Transmitter. Thusthe timer is unnecessary. To enable the 100mstimer, set this bit to a 1.

1 RW RX DET RX Detect SelectSEL Controls assertion of the Receiver Detect Interrupt.

If set to 0, the Receiver Detect Interrupt will beasserted on detection of an FPD-Link III Receiver. Ifset to 1, the Receiver Detect Interrupt will alsorequire a receive lock indication from the receiver.

0 RW HDCP AV Enable AVMUTEMUTE Setting this bit to a 1 will initiate AVMUTE operation.

The transmitter will ignore encryption status controlswhile in this state. If this bit is set to a 0, normaloperation resumes. This bit may only be set if theHDCP_EESS bit is also set.




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE195 0xC3 HDCP CTL 7 RW 0x00 HDCP RST HDCP Reset

Setting this bit will reset the HDCP transmitter anddisable HDCP authentication. This bit is self-clearing.

6 Reserved5 RW KSV List The controller sets this bit after validating the

Valid Repeater’s KSV List against the Key revocation list.This allows completion of the Authenticationprocess. This bit is self-clearing

4 RW KSV Valid The controller sets this bit after validating theReceiver’s KSV against the Key revocation list. Thisallows continuation of the Authentication process.This bit will be cleared upon assertion of theKSV_RDY flag in the HDCP_STS register. Settingthis bit to a 0 will have no effect

3 RW HDCP ENC HDCP Encrypt DisableDIS Disables HDCP encryption. Setting this bit to a 1 will

cause video data to be sent without encryption.Authentication status will be maintained. This bit isself-clearing

2 RW HDCP ENC HDCP Encrypt EnableEN Enables HDCP encryption. When set, if the device

is authenticated, encrypted data will be sent. Ifdevice is not authenticated, a blue screen will besent. Encryption should always be enabled whenvideo data requiring content protection is beingsupplied to the transmitter. When this bit is not set,video data will be sent without encryption. Note thatwhen CFG_ENC_MODE is set to Enc_Always, thisbit will be read only with a value of 1

1 RW HDCP DIS HDCP DisableDisables HDCP authentication. Setting this bit to a 1will disable the HDCP authentication.This bit is self-clearing

0 RW HDCP EN HDCP Enable/RestartEnables HDCP authentication. If HDCP is alreadyenabled, setting this bit to a 1 will restartauthentication. Setting this bit to a 0 will have noeffect. A register read will return the current HDCPenabled status




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE196 0xC4 HDCP STS 7 R 0x00 I2C ERR HDCP I2C Error Detected

DET This bit indicates an error was detected on theembedded communications channel with the HDCPReceiver. Setting of this bit might indicate that aproblem exists on the link between the HDCPTransmitter and HDCP Receiver. This bit will becleared on read

6 R RX INT RX InterruptStatus of the RX Interrupt signal.The signal is received from the attached HDCPReceiver and is the status on the INTB_IN pin of theHDCP Receiver. The signal is active low, a 0indicates an interrupt condition

5 R RX Lock Receiver Lock DetectDET This bit indicates that the downstream Receiver has

indicated Receive Lock to incoming serial data4 R DOWN Hot Plug Detect

HPD This bit indicates the local device or a downstreamrepeater has reported a Hot Plug event, indicatingaddition of a new receiver. This bit will be clearedon read

3 R RX DET Receiver DetectThis bit indicates that a downstream Receiver hasbeen detected

2 R KSV LIST HDCP Repeater KSV List ReadyRDY This bit indicates that the Receiver KSV list has

been read and is available in the KSV_FIFOregisters. The device will wait for the controller toset the KSV_LIST_VALID bit in the HDCP_CTLregister before continuing. This bit will be clearedonce the controller sets the KSV_LIST_VALID bit.

1 R KSV RDY HDCP Receiver KSV ReadyThis bit indicates that the Receiver KSV has beenread and is available in the HDCP_ BKSV registers.If the device is not a Repeater, it will wait for thecontroller to set the KSV_VALID bit in theHDCP_CTL register before continuing.This bit will be cleared once the controller sets theKSV_VALID bit.. The bit will also be cleared ifauthentication fails.

0 R AUTHED HDCP AuthenticatedIndicates the HDCP authentication has completedsuccessfully. The controller may now send videodata requiring content protection. This bit will becleared if authentication is lost or if the controllerrestarts authentication




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REG-ADD ADD REGISTER DEFAULTBit(s) ISTER FUNCTION DESCRIPTION(dec) (hex) NAME (hex)TYPE198 0xC6 HDCP ICR 7 RW 0x00 IE IND ACC Interrupt on Indirect Access Complete

Enables interrupt on completion of Indirect RegisterAccess

6 RW IE RXDET Interrupt on Receiver DetectINT Enables interrupt on detection of a downstream

Receiver. If HDCP_CFG:RX_DET_SEL is set to a 1,the interrupt will wait for Receiver Lock Detect.

5 RW IS_RX_INT Interrupt on Receiver interruptEnables interrupt on indication from the HDCPReceiver. Allows propagation of interrupts fromdownstream devices

4 RW IE LIST Interrupt on KSV List ReadyRDY Enables interrupt on KSV List Ready

3 RW IE KSV Interrupt on KSV ReadyRDY Enables interrupt on KSV Ready

2 RW IE AUTH Interrupt on Authentication FailureFAIL Enables interrupt on authentication failure or loss of

authentication1 RW IE AUTH Interrupt on Authentication Pass

PASS Enables interrupt on successful completion ofauthentication

0 RW INT Enable Global Interrupt EnableEnables interrupt on the interrupt signal to thecontroller.

199 0xC7 HDCP ISR 7 R 0x00 IS IND ACC Interrupt on Indirect Access CompleteIndirect Register Access has completed

6 R INT Detect Interrupt on Receiver Detect interruptA downstream receiver has been detected

5 R IS RX INT Interrupt on Receiver interruptReceiver has indicated an interrupt request fromdown-stream device

4 R IS LIST Interrupt on KSV List ReadyRDY The KSV list is ready for reading by the controller

3 R IS KSV Interrupt on KSV ReadyRDY The Receiver KSV is ready for reading by the

controller2 R IS AUTH Interrupt on Authentication Failure

FAIL Authentication failure or loss of authentication hasoccurred

1 R IS AUTH Interrupt on Authentication PassPASS Authentication has completed successfully

0 R INT Global InterruptSet if any enabled interrupt is indicated

240 0xF0 HDCP TX ID 7:0 R 0x5F ID0 First byte ID code, ‘_’241 0xF1 7:0 R 0x55 ID1 Second byte of ID code, ‘U’242 0xF2 7:0 R 0x48 ID2 Third byte of ID code. Value will be either ‘B’ or ‘H’.

‘H’ indicates an HDCP capable device243 0xF3 7:0 R 0x39 ID3 Forth byte of ID code: ‘9’244 0xF4 7:0 R 0x32 ID4 Fifth byte of ID code: '2'245 0xF5 7:0 R 0x35 ID5 Sixth byte of ID code: '5'




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8 Applications and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe DS90UH925Q-Q1, in conjunction with the DS90UH926Q-Q1, is intended for interface between a HDCPcompliant host (graphics processor) and a Display. It supports a 24-bit color depth (RGB888) and high definition(720p) digital video format. It can receive a three 8-bit RGB stream with a pixel rate up to 85 MHz together withthree control bits (VS, HS and DE) and three I2S-bus audio stream with an audio sampling rate up to 192 kHz.The included HDCP 1.3 compliant cipher block allows the authentication of the DS90UH926Q-Q1, whichdecrypts both video and audio contents. The keys are pre-loaded by TI into Non-Volatile Memory (NVM) formaximum security.




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R7R6R5R4R3R2R1R0

G7G6G5G4G3G2G1G0

B7B6B5B4B3B2B1B0

PCLK

PDB

DOUT+DOUT-

CAPL12

CMF

DAP (GND)

CAPP12

CAPHS12

VDD33

3.3VDS90UH925Q-Q1

C6

C7

C1

C2

NOTE:FB1-FB2: Impedance = 1 k: @ 100MHz, Low DC resistance (<1:)C1-C3 = 0.1 PF (50 WV; C1, C2: 0402; C3: 0603)C4-C9 = 4.7 PFC10 =>10 PF

R1 and R2 (see IDx Resistor Values Table 5)

R3 and R4 (see MODE_SEL Resistor Values Table 1)

R5 = 10 k:

R6 = 4.7 k:* or VDDIO = 3.3V+0.3V

LVCMOSParallel

VideoInterface

SerialFPD-Link IIIInterface

VSDE

HS

INTB

I2S_CLKI2S_WCI2S_DA

SCLSDA

ID[X]

3.3V/1.8V

RES

C5

C10

LVCMOSControl

Interface

VDDIO

FB1 FB2

C8

C4

C3

VDD33

4.7k

4.7k

NC

MODE_SEL

R5

VDDIO

C9

VDD33*

VDD33

R4

R3

R2

R1R6


8.2 Typical Application

Figure 23. Typical Connection Diagram




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R[7:0]

HSVS

PCLK

PDBSerializer Deserializer

DE

RGB Display720p

24-bit color depth

RG

B D

igita

l Dis

play

Inte

rfac

e

HOSTGraphicsProcessor

FPD-Link III1 Pair / AC Coupled

DS90UH925Q-Q1 DS90UH926Q-Q1100 ohm STP Cable

PASS

VDDIO

OSS_SEL

SCLSDA

INTB

I2S AUDIO (STEREO)

OEN

LOCK

IDx DAP DAP

0.1 PF 0.1 PFG[7:0]B[7:0]

SCLSDAIDx

R[7:0]

HSVS

PCLKDE

G[7:0]B[7:0]

RIN+

RIN-

DOUT+

DOUT-

(1.8V or 3.3V)(1.8V or 3.3V) (3.3V) (3.3V)VDDIO

3/

I2S AUDIO (STEREO)

3/MODE_SEL MODE_SEL

MCLK

PDB

INTB_IN

VDD33 VDD33


Typical Application (continued)

Figure 24. Typical Display System Diagram

8.2.1 Design RequirementsFor the typical desing application, use the following as input parameters.

Table 7. Design ParametersDESIGN PARAMETER EXAMPLE VALUE

VDDIO 1.8 V or 3.3 VVDD33 3.3 V

AC Coupling Capacitor for DOUT± 100 nFPCLK Frequency 85 MHz

8.2.2 Detailed Design ProcedureFigure 23 shows a typical application of the DS90UH925Q-Q1 serializer for an 85 MHz 24-bit Color DisplayApplication. The CML outputs must have an external 0.1 μF AC coupling capacitor on the high speed serial lines.The serializer has an internal termination. Bypass capacitors are placed near the power supply pins. At aminimum, six (6) 4.7μF capacitors (and two (2) additional 1μF capacitors should be used for local devicebypassing. Ferrite beads are placed on the two (2) VDDs (VDD33 and VDDIO) for effective noise suppression. Theinterface to the graphics source is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail. ARC delay is placed on the PDB signal to delay the enabling of the device until power is stable.




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Mag

nitu

de (

80 m

V/D

IV)

Time (100 ps/DIV)

CM

L S

eria

lizer

Dat

a T

hrou

ghpu

t(2

00 m

V/D

IV)

78 M

Hz

TX

Pix

el C

lock

Inpu

t(5

00 m

V/D

IV)

Time (2.5 ns/DIV)


8.2.3 Application Curves

Figure 25. Serializer Eye Diagram with 78 MHz TX Pixel Figure 26. Serializer CML Output with 78 MHz TX PixelClock Clock

9 Power Supply RecommendationsThis device is designed to operate from an input core voltage supply of 3.3V. Some devices provide separatepower and ground pins for different portions of the circuit. This is done to isolate switching noise effects betweendifferent sections of the circuit. Separate planes on the PCB are typically not required. Pin description tablestypically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, anexternal filter may be used to provide clean power to sensitive circuits such as PLLs.

9.1 Power Up Requirements and PDB PinThe VDDs (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. A large capacitoron the PDB pin is needed to ensure PDB arrives after all the VDDs have settled to the recommended operatingvoltage. When PDB pin is pulled to VDDIO = 3.0V to 3.6V or VDD33, it is recommended to use a 10 kΩ pull-up anda >10 uF cap to GND to delay the PDB input signal.

All inputs must not be driven until VDD33 and VDDIO has reached its steady state value.

9.2 CML Interconnect GuidelinesSee AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.• Use 100Ω coupled differential pairs• Use the S/2S/3S rule in spacings

– S = space between the pair– 2S = space between pairs– 3S = space to LVCMOS signal

• Minimize the number of Vias• Use differential connectors when operating above 500 Mbps line speed• Maintain balance of the traces• Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TexasInstruments web site at: www.ti.com/lvds.




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10 Layout

10.1 Layout GuidelinesCircuit board layout and stack-up for the FPD-Link III devices should be designed to provide low-noise powerfeed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs tominimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatlyimproved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides planecapacitance for the PCB power system with low-inductance parasitics, which has proven especially effective athigh frequencies, and makes the value and placement of external bypass capacitors less critical. External bypasscapacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in therange of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of thetantalum capacitors should be at least 5X the power supply voltage being used.

Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors persupply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of powerentry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It isrecommended to connect power and ground pins directly to the power and ground planes with bypass capacitorsconnected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an externalbypass capacitor will increase the inductance of the path.

A small body size X7R chip capacitor, such as 0603 or 0402, is recommended for external bypass. Its small bodysize reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency ofthese external bypass capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiplecapacitors are often used to achieve low impedance between the supply rails over the frequency of interest. Athigh frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducingthe impedance at high frequency.

Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolateswitching noise effects between different sections of the circuit. Separate planes on the PCB are typically notrequired. Pin Description tables typically provide guidance on which circuit blocks are connected to which powerpin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such asPLLs.

Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the CMLlines to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ohmsare typically recommended for CML interconnect. The closely coupled lines help to ensure that coupled noise willappear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.

Information on the WQFN style package is provided in TI Application Note: AN-1187 (SNOA401).




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10.2 Layout ExampleStencil parameters such as aperture area ratio and the fabrication process have a significant impact on pastedeposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improveboard assembly yields. If the via and aperture openings are not carefully monitored, the solder may flowunevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:

Figure 27. No Pullback WQFN, Single Row Reference Diagram

Table 8. No Pullback WQFN Stencil Aperture SummaryDevice Pin MKT Dwg PCB I/O PCB PCB DAP Stencil I/O Stencil DAP Number of Gap Between DAP

Count Pad Size Pitch size (mm) Aperture Aperture DAP Aperture (Dim A(mm) (mm) (mm) (mm) Aperture mm)

OpeningsDS90UH925 0.25 x48 SQA48A 0.5 5.1 x 5.1 0.25 x 0.7 1.1 x 1.1 16 0.2Q-Q1 0.6

Figure 28. 48-Pin WQFN Stencil Example of Via and Opening Placement




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Figure 29 shows the PCB layout example derived from the layout design of the DS90UH925QSEVB EvaluationBoard. The graphic and layout description are used to determine both proper routing and proper soldertechniques when designing the Serializer board.

Figure 29. DS90UH925Q-Q1 Serializer Example Layout




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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation• AN-2198 Exploring the Internal Test Pattern Generation SNLA132• AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines SNLA008• SCAN18245T Non-Inverting Transceiver with TRI-STATE Outputs SNLA035• TI Interface Website www.ti.com/lvds• AN-1187 Leadless Leadframe Package (LLP) SNOA401• Semiconductor and IC Package Thermal Metrics SPRA953

11.2 TrademarksAll trademarks are the property of their respective owners.

11.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

www.ti.com 11-May-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

DS90UH925QSQ/NOPB ACTIVE WQFN RHS 48 1000 Green (RoHS& no Sb/Br)

CU SN Level-3-260C-168 HR -40 to 105 UH925QSQ

DS90UH925QSQE/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS& no Sb/Br)


DS90UH925QSQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

DS90UH925QSQ/NOPB WQFN RHS 48 1000 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

DS90UH925QSQE/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

DS90UH925QSQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Sep-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90UH925QSQ/NOPB WQFN RHS 48 1000 367.0 367.0 38.0

DS90UH925QSQE/NOPB WQFN RHS 48 250 210.0 185.0 35.0

DS90UH925QSQX/NOPB WQFN RHS 48 2500 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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PACKAGE OUTLINE

C

SEE TERMINALDETAIL

48X 0.300.18

5.1 0.1

48X 0.50.3

0.80.7

(A) TYP

0.050.00

44X 0.5

2X5.5

2X 5.5

A 7.156.85

B

7.156.85

0.300.18

0.50.3

(0.2)

WQFN - 0.8 mm max heightRHS0048APLASTIC QUAD FLATPACK - NO LEAD

4214990/B 04/2018

DIM AOPT 1 OPT 2(0.1) (0.2)

PIN 1 INDEX AREA

0.08 C

SEATING PLANE

1

1225

36

13 24

48 37

(OPTIONAL)PIN 1 ID 0.1 C A B

0.05

EXPOSEDTHERMAL PAD

49 SYMM

SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 1.800

DETAILOPTIONAL TERMINAL

TYPICAL

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EXAMPLE BOARD LAYOUT

0.07 MINALL AROUND

0.07 MAXALL AROUND

48X (0.25)

48X (0.6)

( 0.2) TYPVIA

44X (0.5)

(6.8)

(6.8)

(1.25) TYP

( 5.1)

(R0.05)TYP

(1.25)TYP

(1.05) TYP

(1.05)TYP


4214990/B 04/2018

SYMM

1

12

13 24

25

36

3748

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:12X

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

49

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKDEFINED

EXPOSEDMETAL

METAL EDGE

SOLDER MASKOPENING

SOLDER MASK DETAILS

NON SOLDER MASKDEFINED

(PREFERRED)

EXPOSEDMETAL

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EXAMPLE STENCIL DESIGN

48X (0.6)

48X (0.25)

44X (0.5)

(6.8)

(6.8)

16X( 1.05)

(0.625) TYP

(R0.05) TYP

(1.25)TYP

(1.25)TYP

(0.625) TYP


4214990/B 04/2018

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

49

SYMM

METALTYP

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

68% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGESCALE:15X

SYMM

1

12

13 24

25

36

3748

IMPORTANT NOTICE

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