DS0131 RTG4 FPGA Datasheet - Microsemi

RTG4trade FPGA

IntroductionRTG4 FPGAs integrate Microchips fourth-generation flash-based FPGA fabric and high-performance interfacessuch as serializationdeserialization (SerDes) on a single-chip while maintaining the resistance to radiation-inducedconfiguration upsets in the harshest radiation environments such as space flight (LEO MEO GEO HEO deepspace) high altitude aviation medical electronics and nuclear power plant control The RTG4 family offers up to151824 registers which are hardened by design against radiation-induced single-event upsets (SEUs) Each RTG4logic element includes a 4-input LookUp Table (LUT4) with fast carry chains providing high-performance FPGA fabricup to 300 MHz

Multiple embedded memory options and embedded multiply-accumulate blocks perform Digital Signal Processing(DSP) up to 300 MHz A high-speed serial interface provides 3125 Gbps native SerDes communication while doubledata rate DDR2DDR3LPDDR memory controllers provide high-speed memory interfaces

Device StatusThe following table lists the development status of the RTG4 FPGA devices

Table 1 Device Status

Device Package Status

RT4G150 CGLGCB1657 Production

RT4G150 CQ352 Production

RT4G150 FCGFC1657 Production

Note For CQ352 package qualification Group D5 which includes the salt atmosphere test is only done with thedevices lid face down

Technical Briefs and Pin DescriptionsThe following list shows the technical brief and pin descriptions of the RTG4 FPGAs that are published separately

bull RTG4 FPGAs Technical Briefbull RTG4 FPGA Pin Descriptionsbull RTG4 Plastic Pin Assignment

copy 2021 Microchip Technology Incand its subsidiaries

Datasheet DS00003669B-page 1

Table of Contents

Introduction1

1 Device Status 12 Technical Briefs and Pin Descriptions 1

1 General Specifications 4

11 Operating Conditions4

2 Power Consumption 11

21 Quiescent Supply Current 11

3 Junction Temperature and Derating Factors 13

4 User IO Characteristics 14

41 Input Buffer1442 Output Buffer and AC Loading 1543 Tristate Buffer and AC Loading 1644 IO Speeds 1745 Detailed IO Characteristics1946 Single-Ended IO Standards2047 Memory Interface and Voltage Reference IO Standards3348 Differential IO Standards 5649 IO Register Specifications70410 DDR Module Specification 75

5 Logic Element Specifications 81

51 LUT48152 Sequential Module82

6 Global Resource Characteristics85

7 FPGA Fabric SRAM 86

71 FPGA Fabric Large SRAM (LSRAM) 8672 FPGA Fabric Micro SRAM (microSRAM)90

8 FPGA Fabric Micro PROM (μPROM)100

9 JTAG 101

91 Live Probe 101

10 Power-up to Functional Times102

11 Device Reset DEVRST_N104

12 On-Chip Oscillator106

13 Clock Conditioning Circuits (CCC) 107

14 System Controller SPI Characteristics111

15 Mathblock Timing Characteristics112



16 IO Delay Block Characteristics115

17 SerDes Electrical and Timing Characteristics 118

18 SpaceWire Clock and Data Recovery125

19 Temperature Sensing Diode127

20 Revision History 128

The Microchip Website134

Product Change Notification Service134

Customer Support 134

Microchip Devices Code Protection Feature 134

Legal Notice 134

Trademarks 135

Quality Management System 136

Worldwide Sales and Service137



1 General SpecificationsThe following sections describe general specifications of the RTG4 FPGA devices

11 Operating ConditionsAbsolute maximum ratings are stress ratings only functional operation of the device at these or any other conditionsbeyond those listed under the recommended operating conditions specified in table Recommended OperatingConditions is not implied

Note Stresses beyond those listed in the following table might cause permanent damage to the device Exposure toabsolute maximum rating conditions for extended periods may affect device reliability

Table 1-1 Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD DC FPGA core supply voltage It must alwayspower this pin

ndash03 136 V

AC FPGA core supply voltage1 ndash03 145 V

VPP Power supply for charge pumps (for normaloperation and programming) Must alwayspower this pin

ndash03 363 V

VDDPLL Power for eight corner PLLs PLLs in SerDesPCIePCS blocks and FDDR PLL

ndash03 363 V

SERDES_x_Lyz_VDDAIO TxRx analog IO voltage Low voltage power forlane-y and lane-z of SERDES_x It is a 12VSerDes PMA supply

ndash03 132 V

SERDES_x_Lyz_VDDAPLL Analog power for SERDES_x PLL lanes yz It isa 25V SerDes internal PLL supply

ndash03 275 V

SERDES_VDDI Power for SerDes reference clock receiversupply Must always power this pin

ndash03 363 V

VDDIx DC FPGA IO bank supply voltage for MSIOand JTAG IO Banks

ndash03 363 V

AC FPGA IO buffer supply voltage for MSIOJTAG IO Bank2

ndash03 375 V

DC FPGA IO bank supply voltage for MSIODand DDRIO IO Banks

ndash03 275 V

AC FPGA IO buffer supply voltage for MSIODDDRIO IO Bank2

ndash03 285 V

VI IO Input voltage for MSIO and JTAG IO Banks ndash03 363 V

IO Input voltage for MSIOD and DDRIO IOBanks

ndash03 275 V

Single ended voltage on SerDes RX pads ndash03 132 V

TSTG Storage temperature3 ndash65 150 degC

General Specifications



continuedSymbol Parameter Min Max Units

TJ Junction temperature mdash 135 degC

Notes 1 The AC transient VDD limit is for radiation-induced transients less than 10 micros duration and not intended for

repetitive Core voltage that spikes from a single event transient does not negatively affect the reliability of thedevice if for this non-repetitive event the transient does not exceed 145V at any time and the total time thatthe transient exceeds 126V does not exceed 10 micros in duration

2 The AC transient VDDI limit is for radiation-induced transients less than 10 micros duration and not intended forrepetitive

3 For Flash programming and retention maximum limits see table Operating Limits The following table lists therecommended operating conditions

Table 1-2 Recommended Operating Conditions

Symbol Parameter Min Typ Max Units

TJ Operating junction temperature ndash55 25 125 degC

Programming junction temperature 0 25 85 degC

VDD DC FPGA core supply voltage It mustalways power this pin

114 12 126 V

VPP Power supply for charge pumps (fornormal operation and programming) Itmust always power this pin

315 33 345 V

VDDPLL Power for eight corner PLLs PLLs inSerDes PCIePCS blocks and FDDRPLL

315 33 345 V

SERDES_x_Lyz_VDDAIO

TxRx analog IO voltage Low voltagepower for lane-y and lane-z ofSERDES_x It is a 12V SerDes PMAsupply

114 12 126 V

SERDES_x_Lyz_VDDAPLL

Analog power for SERDES_x PLL lanesyz It is a 25V SerDes internal PLLsupply

2375 25 2625 V

SERDES_VDDI Power for SerDes reference clockreceiver 18V supply Must alwayspower this pin

171 18 189 V

Power for SerDes reference clockreceiver 25V supply Must alwayspower this pin

2375 25 2625 V


315 33 345 V

SERDES_VREF1 Reference voltage for SerDes receiverreference clocks

049 times

SERDES_VDDI

05 times

SERDES_VDDI

051 times

SERDES_VDDI

V




continuedSymbol Parameter Min Typ Max Units

VDDIx 12V DC supply voltage for FPGA IOBanks

114 12 126 V

15V DC supply voltage for FPGA IOBanks

1425 15 1575 V

18V DC supply voltage for FPGA andJTAG IO Banks

171 18 189 V


2375 25 2625 V


315 33 345 V

DC supply voltage for LVDS25differential IO Banks

2375 25 2625 V


315 33 345 V

DC supply voltage for BLVDS MLVDSMini-LVDS and RSDS differential IOBanks

2375 25 2625 V

DC supply voltage for LVPECLdifferential IO Banks

315 33 345 V

Note 1 Maximum input leakage current for SERDES_VREF is 10 microA

The recommended power supply tolerances in the preceeding table include DC offset of the supply plus any powersupply ripple over the customer design frequencies of interest as measured at the device package pins An examplefor a valid power supply that meets the recommendations for the VDD supply is 12 V plusmn2 for DC offset with anadditional power supply ripple of plusmn3 for a total of 12 V plusmn5

For more information about power supply grouping requirements see AC439 Board Design Guidelines for RTG4FPGA Application Note Power supply ramps must all be strictly monotonic and without plateaus

Table 1-3 Operating Limits

Programming

Temperature

Operating

Temperature

Programming

Cycles

Verify Cyclesper

Program Cycle

In-FlightReprogramming TID(Maximum)

Retention1

(BiasedUnbiased)

Min TJ = 0 degC

Max TJ = 85 degC

Min TJ = ndash55 degC

Max TJ = 125 degC

200 200 50 Krad 10 years

Notes

1 For retention limits at other TJ points see Table 1-4 and Figure 1-12 Stand-alone verify must be performed immediately after in-flight programming to ensure programming integrity

For more information see UG0602 RTG4 FPGA Programming User Guide When not performing in-flightprogramming stand-alone verify must not be attempted after the part has been deployed in space or exposedto radiation as it might result in false failures




3 Stand-alone erase is not required because erase is always performed on RTG4 devices prior to programmingIf a stand-alone erase is applied it increases the programming cycle count by two For flight units ensure thatthe programming cycle count stays within 200 cycles including program and stand-alone erase cycles

4 RTG4 μPROM has an unlimited number of read cycles The μPROM write cycle limit retention limit in-flightreprogramming TID and verify cycles per program cycle limit is the same as the FPGA fabric programmingcycles listed in Table 1-3 (since its part of the fabric)




The following table and figure show retention at different junction temperatures

Table 1-4 High Temperature Data Retention (HTR) Lifetime

Tj (degC) Flash HTR1 (Years)

90 20

95 20

100 20

105 20

110 20

115 20

120 14

125 10

130 72

135 53

140 39

145 28

150 21

Note 1 HTR lifetime is the period during which a verify failure is not expected due to flash leakage

The following figure shows HTR (derived junction temperature versus lifetime)

Figure 1-1 High Temperature Data Retention (HTR) Lifetime




111 OvershootUndershoot LimitsFor AC signals the input signal might undershoot during transitions to ndash08V for no longer than 10 of the periodThe current during the transition must not exceed 100 mA

For AC signals the input signal might overshoot during transitions to VDDIx + 08V for no longer than 10 of theperiod The current during the transition must not exceed 100 mA

Note The preceeding specification does not apply to the PCI standard The RTG4 PCI IOs are compliant to thePCI standard including the PCI overshootundershoot specifications

112 Power-Up and Power-Down SequenceThe following sections show the power-up and power-down sequences of the RTG4 FPGA devices

1121 Power-Up SequenceVDDPLL Requirements

No power-up sequence is required if the device is held in reset by asserting DEVRST_N until VDDPLL supplies reachtheir minimum recommended level as shown in Recommended Operating Conditions

If the device cannot be held in reset either of the following power-up requirements apply

bull All PLLs are held in reset until VDDPLL supply reaches its minimum recommended level To meet thisrequirement see the UG0586 RTG4 Clocking Resources User Guide for suggested methods using theREADY_VDDPLL input to the RTG4 Fabric CCC

bull VDDPLL must not be the last supply to ramp up and must reach its minimum recommended level before the lastsupply (VDD or VDDIx) starts ramping up

SERDES_x_Lyz_VDDAIO Requirements

No power-up sequence occurs if SERDES_x_Lyz_VDDAIO supplies are tied to VDD If SERDES_x_Lyz_VDDAIO andVDD cannot be tied together then the SERDES_x_Lyz_VDDAIO must be powered up at the same time as VDD

For more information see the AC439 Board Design Guidelines for RTG4 FPGA Application Note and the associatedAC439 Addendum

1122 Power-Down SequenceThere is no power-down sequence if an external 1 kΩ pull-down resistor is used for each critical output which cannottolerate an output glitch during power-down or DEVRST_N assertion If an external resistor cannot be used either ofthe following requirements apply

bull VDDIx supplies are powered down first all the way to 0Vbull VPP is powered down last

If VPP or VDD falls below the minimum recommended level then both VPP and VDD must be powered down all the wayto 0V before powering back up Powering down VPP without powering down VDD is not allowed


113 Thermal CharacteristicsThe temperature variable in the Microchip SoC Products Group Liberoreg SoC software refers to the junctiontemperature not the ambient case or board temperatures This is an important distinction because dynamic andstatic power consumption will cause the chips junction temperature to be higher than the ambient case or boardtemperatures

The following equations show the relationship between thermal resistance temperature gradient and power

ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where

ΘJB = Junction-to-board thermal resistance

ΘJC = Junction-to-case thermal resistance




TJ = Junction temperature

TA = Ambient temperature

TB = Board temperature (measured 10 mm away from the package edge)

TC = Case temperature

P = Total power dissipated by the device

The following table lists the details of package thermal resistance

Table 1-5 Package Thermal Resistance

RTG4 Product ΘJA ΘJB ΘJC Units

CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW

Notes Theta-JC and Theta-JB values are simulated with conduction heat transfer only1 Theta-JA values are simulated for still air2 Theta-JB for CCGA1657 and FCGFC1657 refers to the thermal resistance between the junction to the board

as defined in the JESD51 standards3 Theta-JB for CQFP352 and LGA1657 refers to the thermal resistance between the junction and the bottom

surface of the package4 Theta-JC refers to the thermal resistance between the junction and the top surface (package lid)

1131 Theta-JBJunction-to-board thermal resistance (ΘJB) measures the ability of the package to dissipate heat from the surface ofthe chip to the PCB As defined by the JEDEC (JESD-51) standard the thermal resistance from junction to boarduses an isothermal ring cold plate zone concept The ring cold plate is simply a means to generate an isothermalboundary condition at the perimeter The cold plate is mounted on a JEDEC standard board with a minimum distanceof 50 mm away from the package edge

1132 Theta-JCJunction-to-case thermal resistance (ΘJC) measures the ability of a device to dissipate heat from the surface of thechip to the top or bottom surface of the package It is applicable for packages used with external heat sinks Constanttemperature is applied to the surface under consideration and acts as a boundary condition This only applies tosituations where all or nearly all of the heat is dissipated through the surface under consideration




2 Power ConsumptionThe following sections describe the power consumption of the RTG4 FPGA devices

21 Quiescent Supply CurrentTable 2-1 Quiescent Supply Current Characteristics

Power SuppliesBlocks Standby Mode

FPGA Core VDD On

VPP On

VDDPLL 0V

SERDES_x_Lyz_VDDAPLL1 0V

SERDES_x_Lyz_VDDAIO1 On

VDDIx2 3 On

VREF0 VREF94 On

50 MHz Oscillator Enabled

Notes 1 SerDes and DDR blocks are in RESET states2 VDDIx supplies to all IO Banks are set to ON in standby mode3 No differential IO or On-Die Termination (ODT) resistor is used4 Maximum input leakage current for VREF0 and VREF9 is 10 microA

Table 2-2 RTG4 Quiescent Supply Current

Devices Conditions IDC1 Units

RT4G150 Typical (TJ = 25 degC) VDD = 12V 410 mA

Worst-case (TJ = 125 degC) VDD = 126V 4100 mA

RT4G150L Typical (TJ = 25 degC) VDD = 12V 310 mA


Note 1 IDC is the current measured on the VDD supply in standby mode

211 Programming CurrentsThe following table lists the device programming currents Worst-case conditions 0 degC le TJ le 85 degC

Table 2-3 Programming Currents

Supply Voltage (V) Programming Current (mA)

VDD 114 756

VDDI 2375 41

Power Consumption



continuedSupply Voltage (V) Programming Current (mA)

VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2

SerDes VDDAPLL 2375 1

Power Consumption



3 Junction Temperature and Derating FactorsThe following table lists the junction temperature and derating factors for fabric timing delays normalized to TJ = 125degC In worst-case VDD = 114V

Table 3-1 JunctionTemperature and Voltage Derating Factors for Fabric Timing Delays

Core Voltage

VDD (V)

ndash55 degC ndash40 degC 0 degC 25 degC 70 degC 85 degC 100 degC 125 degC

114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090

Junction Temperature and Derating Factors



4 User IO CharacteristicsThree types of IOs supported in the RTG4 FPGA families are MSIO MSIOD and DDRIO The IO standardssupported by the different IO banks is described in the UG0741 RTG4 FPGA IO User Guide The Libero SoCautomatically configures unused user IOs with the input buffer disabled and output buffer tristated with weak pull-upenabled

For information about IO states during programming see the UG0602 RTG4 FPGA Programming Users Guide

41 Input BufferThe following figure shows the input buffer delays

Figure 4-1 Input Buffer

User IO Characteristics



42 Output Buffer and AC LoadingThe following figure shows the output buffer delays and AC loading

Figure 4-2 Output Buffer and AC Loading




43 Tristate Buffer and AC LoadingThe tristate path for enable path loadings is described in the respective specifications The following figure shows themethodology of characterization illustrated by the enable path test point

Figure 4-3 Tristate Buffer for Enable Path Test Point

Note For LVTTLLVCMOS standards tLZ and tHZ = Time taken from 50 of enable de-assertion to driver leakagecurrent reduction to 10 μA or less




44 IO SpeedsThe following section describes the maximum data rate summary of IO in worst-case military conditions

TJ = 125 degC VDD = 114V and VDDIx at minimum recommended value shown in Recommended Operating Conditionsis for respective IO standard

Table 4-1 Maximum IO Data Rate for Worst-Case Military Conditions

Single-Ended IO MSIO MSIOD DDRIO Units

PCI 33V 630 mdash mdash Mbps

LVTTL 33V 600 mdash mdash Mbps

LVCMOS 33V 600 mdash mdash Mbps

LVCMOS 25V 410 420 700 Mbps




LPDDRndashLVCMOS 18V mode mdash mdash 266 Mbps

Voltage-Referenced IO MSIO MSIOD DDRIO Units

LPDDR mdash mdash 266 Mbps

HSTL15V Class I 140 180 400 Mbps

HSTL15V Class II mdash mdash 400 Mbps

HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps

SSTL 15V mdash mdash 800 Mbps

Differential IO MSIO MSIOD DDRIO Units

LVPECL (input only) 700 mdash mdash Mbps

LVDS 33V 700 mdash mdash Mbps

LVDS 25V 750 750 mdash Mbps

RSDS 520 700 mdash Mbps

BLVDS 500 500 mdash Mbps

MLVDS 500 500 mdash Mbps

Mini-LVDS 520 700 mdash Mbps

HCSL (input only) 350 350 mdash Mbps




Table 4-2 Maximum IO Frequency Summary for Worst-Case Military Conditions


PCI 33V 315 mdash mdash MHz

LVTTL 33V 300 mdash mdash MHz

LVCMOS 33V 300 mdash mdash MHz

LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz

LVCMOS 12V 70 70 180 MHz

LPDDRndashLVCMOS 18V mode mdash mdash 133 MHz


LPDDR mdash mdash 133 MHz

HSTL15V Class I 70 90 200 MHz

HSTL15V Class II mdash mdash 200 MHz

HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz

SSTL 15V mdash mdash 400 MHz


LVPECL (input only) 350 mdash mdash MHz

LVDS 33V 350 mdash mdash MHz

LVDS 25V 375 375 mdash MHz

RSDS 260 350 mdash MHz

BLVDS 250 250 mdash MHz

MLVDS 250 250 mdash MHz

Mini-LVDS 260 350 mdash MHz

HCSL (input only) 175 175 mdash MHz




45 Detailed IO CharacteristicsThe following section shows the IO characteristics of the RTG4 FPGA devices

Table 4-3 Input Capacitance

Symbol Definition Min Max Units

CIN Input capacitance mdash 20 pF

TRAMPIN 1 Input ramp time (Applicable to all digital inputs) mdash 50 ns

Note

1 Voltage ramp must be monotonic

Table 4-4 IO Weak Pull-UpPull-Down Resistance Values for DDRIO MSIO and MSIOD Banks

VDDI DDRIO IO Bank MSIO IO Bank MSIOD IO Bank

R(WEAK PULL-UP)

at VOH KΩ

R(WEAK PULL-DOWN) at VOLKΩ

R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)at VOL KΩ


Min Max Min Max Min Max Min Max Min Max Min Max

33V mdash mdash mdash mdash 99 171 998 175 mdash mdash mdash mdash

25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191

Notes bull R(WEAK PULLndashDOWN MAX) = (VOLspec)I(WEAK PULLndashDOWN MIN)bull R(WEAK PULL-UP MAX) = (VDDImaxndashVOHspec)I(WEAK PULL-UP MIN)

The following table lists the hysteresis voltage value for schmitt trigger mode input buffers

Table 4-5 Schmitt Trigger Input Hysteresis

Input Buffer Configuration Hysteresis Value (Typical unless otherwise noted)

33V LVTTLLVCMOSPCIPCI-X 005 times VDDI (worst-case)

25V LVCMOS 005 times VDDI (worst-case)


15V LVCMOS 60 mV

12V LVCMOS 20 mV




46 Single-Ended IO StandardsThe follwoing sections describe the single-ended IO standards of the RTG4 FPGA devices

461 Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)LVCMOS is a widely used switching standard implemented in CMOS transistors This standard is defined byJEDEC (JESD 8-5) The LVCMOS standards supported in RTG4 FPGAs are LVCMOS12 LVCMOS15 LVCMOS18LVCMOS25 and LVCMOS33

462 33V LVCMOSLVTTLLVCMOS 33V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 33V applications

4621 Minimum and Maximum ACDC Input and Output Levels SpecificationAll edits in the following table are as per SAR 114840

Table 4-6 LVTTLLVCMOS 33V DC Voltage Specification (Applicable to MSIO IO Bank Only)

Symbol Parameters Conditions Min Typ Max Units

LVTTLLVCMOS 33V Recommended DC Operating Conditions

VDDI Supply voltage mdash 315 33 345 V

LVTTLLVCMOS 33V DC Input Voltage Specification

VIH (DC) DC input logic high mdash 20 mdash 345 V

VIL (DC) DC input logic low mdash ndash03 mdash 08 V

IIH (DC) Input leakage current high mdash mdash mdash 10 microA

IIL (DC) Input leakage current low mdash mdash mdash 10 microA

IOZ (DC) Tristate leakage current mdash mdash mdash 10 microA

LVCMOS 33V DC Output Voltage Specification1

VOH DC output logic high IOH = 100 microA VDDI ndash 02 mdash mdash V

IOH ge 2 mA 24 mdash mdash V

VOL DC output logic low IOL = 100 microA mdash mdash 02 V

IOL ge 2 mA mdash mdash 04 V

LVTTL 33V DC Output Voltage Specification

VOH DC output logic high mdash 24 mdash mdash V

VOL DC output logic low mdash mdash mdash 04 V

Note 1 The VOHVOL test points selected ensure compliance with LVCMOS 33V JESD8-B requirements

Table 4-7 LVTTLLVCMOS 33V Maximum Switching Speeds (Applicable to MSIO IO Bank Only)


Dmax Maximum data rate (for MSIO IO Bank) AC Loading 10 pF500Ω loadmaximum drive

mdash mdash 600 Mbps




Table 4-8 LVTTLLVCMOS 33V AC Test Parameter Specifications (Applicable to MSIO Bank Only)

Symbol Parameters Min Typ Max Units

Vtrip Measuringtrip point for data path mdash 14 mdash V

Rent Resistance for enable path

(tZH tZL tHZ and tLZ)

mdash 2k mdash Ω

Cent Capacitive loading for enable path


mdash 5 mdash pF

Cload Capacitive loading for data path (tDP) mdash 5 mdash pF

Table 4-9 LVTTLLVCMOS 33V Transmitter Drive Strength Specifications (Applicable to MSIO Bank Only)

Output Drive Selection VOH Min (V) VOL Max (V) IOH (mA) IOL (mA)

2 mA VDDIndash02 02 01 01

2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16

4622 AC Switching CharacteristicsWorst-case military conditions TJ = 125 degC VDD = 114V and VDDI = 315V

Table 4-10 LVTTLLVCMOS 33V Receiver Characteristics (Input Buffers)

IO Bank On-DieTermination(ODT) in Ω

tPY tPYS Units

Speed Grade ndash1 Speed GradeSTD


MSIO None 1993 2345 2122 2497 ns

Table 4-11 LVTTLLVCMOS 33V Transmitter Characteristics for MSIO IO Bank (Output and Tristate Buffers)

Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns




463 25V LVCMOSLVCMOS 25V is a general standard for 25V applications and is supported in RTG4 FPGAs in compliance to theJEDEC specification JESD8-5A

4631 Minimum and Maximum ACDC Input and Output Levels SpecificationTable 4-12 LVCMOS 25V DC Voltage Specification


LVCMOS 25V Recommended DC Operating Conditions

VDDI Supply voltage 2375 25 2625 V

LVCMOS 25V DC Input Voltage Specification

VIH (DC) DC input logic high 17 mdash 2625 V

VIL (DC) DC input logic low ndash03 mdash 07 V

IIH (DC) Input leakage current high mdash mdash 10 microA

IIL (DC) Input leakage current low mdash mdash 10 microA

IOZ (DC) Tristate leakage current mdash mdash 10 microA


VOH DC output logic high VDDI ndash 04 mdash mdash V

VOL DC output logic low mdash mdash 04 V

Note 1 The selected VOHVOL test points ensure compliance with the LVCMOS 25V JEDEC8-5A requirements

Table 4-13 LVCMOS 25V Maximum AC Switching Speeds


Dmax Maximum data rate (for DDRIOIO Bank)

AC Loading 10 pF500Ω loadmaximum drive


Dmax Maximum data rate (for MSIOIO Bank)



Dmax Maximum data rate (for MSIODIO Bank)



Table 4-14 LVCMOS 25V AC Test Parameters and Driver Impedance Specifications





mdash 2k mdash Ω



mdash 5 mdash pF





Table 4-15 LVCMOS 25V Transmitter Drive Strength Specifications

MSIO IOBank

MSIOD IOBank

DDRIO IO Bank (withSoftware Default FixedCalibration Codes)

VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)

2 mA 2 mA 2 mA VDDIndash04 04 2 2




mdash 10 mA mdash VDDIndash04 04 10 10

12 mA mdash 12 mA VDDIndash04 04 12 12

14 mA mdash mdash VDDIndash04 04 14 14

mdash mdash 16 mA VDDIndash04 04 16 16

Note For board design considerations output slew rates extraction detailed output buffer resistances and IV Curveuse the corresponding IBIS models located at wwwmicrochipcom


Table 4-16 LVCMOS 25V AC Switching Characteristics for Receiver (Input Buffers)


tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns

Table 4-17 LVCMOS 25V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

LVCMOS 25V (for DDRIO IO Bank with Fixed Code)

2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

LVCMOS 25V (for MSIO IO Bank)

2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns

LVCMOS 25V (for MSIOD IO Bank)

2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns

464 18V LVCMOSLVCMOS 18 is a general standard for 18V applications and is supported in RTG4 FPGAs in compliance to theJEDEC specification JESD8-7A

4641 Minimum and Maximum ACDC Input and Output LevelsTable 4-18 LVCMOS 18V DC Voltage Specification





VIH (DC) DC input logic high 065 times VDDI mdash 189 V

VIL (DC) DC input logic low ndash03 mdash 035 times VDDI V




LVCMOS 25V DC Output Voltage Specification





continuedSymbol Parameters Min Typ Max Units




Dmax Maximum data rate (forDDRIO IO Bank)

AC Loading 10 pF500Ω loadmaximum drive and slew





Dmax Maximum data rate (forMSIOD IO Bank)




MSIO IO Bank MSIOD IO Bank DDRIO IO Bank VOH Min (V) VOL Max (V) IOH (mA) IOL (mA)













mdash 2k mdash Ω

Cent Capacitive loading for enable path (tZH tZL tHZ and tLZ) mdash 5 mdash pF







IO Bank On-Die Termination(ODT) in Ω

tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units

DDRIO with fixedcodes

None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns


4651 Minimum and Maximum ACDC Input and Output Levels SpecificationTable 4-24 LVCMOS 15V Minimum and Maximum DC Input and Output Levels











VOH DC output logic high VDDI times 075 mdash mdash V

VOL DC output logic low mdash mdash VDDI times 025 V



Dmax Maximum data rate (for DDRIO IOBank)

AC loading 5 pF loadmaximum drivefast slew





continuedSymbol Parameters Conditions Min Typ Max Units

Dmax Maximum data rate (for MSIO IOBank)

AC loading 5 pF loadmaximum drive


Dmax Maximum data rate (for MSIOD IOBank)

AC loading 5 pFmaximumdrive





Rent Resistance for enable path (tZH tZL tHZ and tLZ) mdash 2k mdash Ω




MSIO IO Bank MSIOD IO Bank DDRIO IO Bank

(with Fixed Code)

VOH Min (V) VOL Max (V) IOH

(mA)

IOL

(mA)

2 mA 2 mA 2 mA VDDI times 075 VDDI times 025 2 2



8 mA mdash 8 mA VDDI times 075 VDDI times 025 8 8

mdash mdash 10 mA VDDI times 075 VDDI times 025 10 10





tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIOwith fixedcodes

None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns




466 12 V LVCMOSLVCMOS 12 is a general standard for 12V applications and is supported in RTG4 FPGAs in compliance to theJEDEC specification JESD8-12A

4661 Minimum and Maximum Input and Output Levels SpecificationTable 4-30 LVCMOS 12V Minimum and Maximum DC Input and Output Levels



































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns

467 33V PCIPCIXPeripheral Component Interface (PCI) for 33V standards specify support for 33 MHz and 66 MHz PCI busapplications

4671 Minimum and Maximum Input and Output Levels SpecificationTable 4-36 PCIPCI-X DC Voltage Specification (Applicable to MSIO Bank Only)


PCIPCIX Recommended DC Operating Conditions


PCIPCIX Input Voltage Specification

VI DC input voltage 0 mdash 345 V




PCIPCIX DC Output Voltage Specification

VOH DC output logic high Per PCI specification V

VOL DC output logic low Per PCI specification V

Table 4-37 PCIPCI-X AC Specifications (Applicable to MSIO Bank Only)


PCIPCI-X AC Specifications

Dmax Maximum data rate(MSIO IO Bank)

AC loading as perJEDEC specifications


PCIPCI-X AC Test Parameters Specifications

Vtrip Measuringtrip point for data path (falling edge) mdash 0615 timesVDDI

mdash V

Vtrip Measuringtrip point for data path (rising edge) mdash 0285 timesVDDI

mdash V

Rtt_test Resistance for data test path mdash 25 mdash Ω





Rent Resistance for enable path (tZH tZL tHZ and tLZ) mdash 2 k mdash Ω

Cent Capacitive loading for enable path (tZH tZL tHZand tLZ)

mdash 5 mdash pF



Table 4-38 PCIPCIX AC Switching Characteristics for Receiver (Input Buffers)


tPY tPYS Units

Speed Gradendash1 Speed GradeSTD


MSIO None 2097 2467 2226 2619 ns

Table 4-39 PCIPCIX AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns

47 Memory Interface and Voltage Reference IO StandardsThe following sections describe the memory interface and voltage reference IO standards for thr RTG4 FPGAdevices

471 High-Speed Transceiver LogicThe High-Speed Transceiver Logic (HSTL) standard is a general purpose high-speed bus standard sponsored byIBM (EIAJESD8-6) The RTG4 FPGA devices support two classes of the 15V HSTL These differential versions ofthe standard require a differential amplifier input buffer and a push-pull output buffer An RTG4 device also supports acustom 18V HSTL

4711 Minimum and Maximum Input and Output Levels SpecificationTable 4-40 HSTL18 Minimum and Maximum DC Input and Output Levels


Recommended DC Operating Conditions


VTT Termination voltage 0838 0900 0964 V

VREF1 Input reference voltage 0838 0900 0964 V

HSTL18 DC Input Voltage Specification





VIH (DC) DC input logic high VREF + 0125 mdash 189 V

VIL (DC) DC input logic low ndash03 mdash VREF ndash 0125 V




HSTL18V DC Output Voltage Specification

HSTL18 Class I

VOH DC output logic high VTT + 0603 mdash mdash V

VOL DC output logic low mdash mdash VTT ndash 0603 V

IOH at VOH Output minimum source DC current

(Applicable to MSIO Bank Only)

45 mdash mdash mA

IOL at VOL Output minimum sink current


ndash45 mdash mdash mA


(Applicable to MSIOD Bank Only)

40 mdash mdash mA





(Applicable to DDRIO Bank Only)

54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA




HSTL18V DC Differential Voltage Specifications

VID DC input differential voltage 02 mdash mdash V

Note 1 Maximum input leakage current for VREF is 10 μA




Table 4-41 HSTL18 AC Specifications


HSTL18 AC Differential Voltage Specifications

VDIFF AC input differential voltage 05 mdash mdash V

Vx AC differential cross point voltage 05 times VDDI ndash0175

mdash (05 times VDDI)+ 0175

V

HSTL18 Maximum AC Switching Speed

Dmax Maximum Data Rate

(for DDRIO IO Bank)

AC loading 3 pF50Ω load mdash mdash 500 Mbps

Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)


Rref Supported OutputDriver

Calibrated Impedance

(for DDRIO IO Bank)

Reference resistor = 150Ω mdash 20 42 mdash Ω

RTT Effective impedanceValue

(ODT)

Reference resistor = 150Ω mdash 50 75150

mdash Ω

HSTL18 AC Test Parameters Specifications


Cent Capacitive loading for enable path (tZH tZL tHZ andtLZ)

mdash 5 mdash pF

Rtt_test Reference resistance for data test path for HSTL18Class I (tDP)

mdash 50 mdash Ω

Rtt_test Reference resistance for data test path for HSTL18Class II (tDP)

mdash 25 mdash Ω





4712 AC Switching CharacteristicsTable 4-42 HSTL18 AC Switching Characteristics for Receiver (Input Buffers)

On-Die Termination(ODT) in Ω

tPY Speed Grade ndash1 tPY Speed Grade STD Units

HSTL18 (for DDRIO IO Bank with Fixed Code)

Pseudo-Differential None 0595 0701 ns

50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns

True-Differential None 0616 0725 ns

50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns

HSTL18 (for MSIO IO Bank)


50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns

HSTL18 (For MSIOD IO Bank)


50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns

NoteData corresponds to fixed PCODE and NCODE for receiver For more information see the UG0741 RTG4FPGA IO User Guide




Table 4-43 HSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns

4713 Minimum and Maximum Input and Output Levels SpecificationTable 4-44 HSTL 15V DC Voltage Specification


HSTL 15V Recommended DC Operating Conditions




HSTL 15V DC Input Voltage Specification










HSTL 15V DC Output Voltage Specification

HSTL 15V Class I

VOH DC output logic high VTT ndash 04 mdash mdash V

VOL DC output logic low mdash mdash mdash V

IOH at VOH Output minimum source DC current (forMSIO Bank)


IOL at VOL Output minimum sink current (for MSIOBank)

80 mdash mdash mA

IOH at VOH Output minimum source DC current (forMSIOD Bank)


IOL at VOL Output minimum sink current (for MSIODBank)

70 mdash mdash mA

IOH at VOH Output minimum source DC current (forDDRIO Bank)


IOL at VOL Output minimum sink current (for DDRIOBank)

80 mdash mdash mA

HSTL 15V Class II (Applicable to DDRIO Bank Only)



IOH at VOH Output minimum source DC current ndash160 mdash mdash mA

IOL at VOL Output minimum sink current 160 mdash mdash mA

HSTL 15V DC Differential Voltage Specifications



Table 4-45 HSTL 15 AC Specifications


HSTL 15 AC Differential Voltage Specifications


Vx AC differential cross point voltage 068 mdash 09 V





HSTL 15 Maximum AC Switching Speed

Dmax Maximum data rate Class I MSIObank only


Maximum data rate Class I MSIODbank only


Maximum data rate Class I DDRIObank only

AC loading per JEDECspecifications


Maximum data rate Class II DDRIObank only



HSTL 15V Impedance Specification

Rref Supported output driver calibratedimpedance

(for DDRIO IO Bank)

Reference resistor = 191Ω mdash 255478

mdash Ω

RTT Effective impedance value

(ODT for DDRIO IO Bank only)

Reference resistor = 191Ω mdash 478 mdash Ω

HSTL 15 AC Test Parameters Specifications



Rtt_test Reference resistance for data test path for HSTL15 Class I (tDP) mdash 50 mdash Ω

Rtt_test Reference resistance for data test path for HSTL15 Class II (tDP) mdash 25 mdash Ω



Table 4-46 HSTL 15V AC Switching Characteristics for Receiver (Input Buffers)

IO Bank On-Die Termination (ODT)in Ω


DDRIO with Fixed Code


478 0606 0712 ns


478 0616 0725 ns

MSIO






continuedIO Bank On-Die Termination (ODT)

in ΩtPY Speed Grade ndash1 tPY Speed Grade STD Units

MSIOD



Note Data corresponds to fixed PCODE and NCODE for receiver For more information see the UG0741 RTG4FPGA IO User Guide


tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns

472 Stub-Series Terminated LogicStub-Series Terminated Logic (SSTL) for 25V (SSTL2) 18V (SSTL18) and 15V (SSTL15) is supported in RTG4FPGAs SSTL2 is defined by JEDEC standard JESD8-9B and SSTL18 is defined by JEDEC standard JESD8-15The RTG4 SSTL IO configurations are designed to meet double data rate standards DDR23 for general purposememory buses DDR standards are designed to meet their JEDEC specifications as defined by JEDEC standard




JESD79F for DDR JEDEC standard JESD79-2F for DDR2 JEDEC standard JESD79-3D for DDR3 and JEDECstandard JESD209A for LPDDR

4721 Stub-Series Terminated Logic 25V (SSTL2)SSTL2 Class I and Class II are supported in RTG4 FPGAs and also comply with reduced and full drive of DDRstandards RTG4 FPGA IOs support both standards for single-ended signaling and differential signaling for SSTL2This standard requires a differential amplifier input buffer and a push-pull output buffer

Table 4-48 DDRSSTL2 Minimum and Maximum DC Input and Output Levels






SSTL2 DC Input Voltage SpecificationmdashApplicable to All Banks






SSTL2 DC Output Voltage Specification

SSTL2 Class I (DDR Reduced Drive)



IOH at VOH Output minimum source DC current 81 mdash mdash mA

IOL at VOL Output minimum sink current ndash81 mdash mdash mA

SSTL2 Class II (DDR Full Drive)

VOH DC output logic high VDDI + 081 mdash mdash V




SSTL2 DC Differential Voltage Specification

VID (DC) DC input differential voltage 02 mdash mdash V





Table 4-49 DDRSSTL2 AC Specifications


SSTL2 AC Differential Voltage Specifications



mdash 05 times VDDI +02

V

SSTL2 Maximum AC Switching Speeds

Dmax Maximum data rate

(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)


SSTL2 Impedance Specifications

Rref Supported outputdriver calibratedimpedance (forDDRIO IO Bank)

Reference Resistor = 150Ω mdash 20 42 mdash Ω

SSTL2 AC Test Parameters Specifications



mdash 5 mdash pF

Rtt_test Reference resistance for data test path for SSTL2Class I (tDP)

mdash 50 mdash Ω

Rtt_test Reference resistance for data test path for SSTL2Class II (tDP)

mdash 25 mdash Ω



Table 4-50 DDRSSTL2 AC Switching Characteristics for Receiver (Input Buffers)

On-Die Termination (ODT)in Ω


SSTL2 (DDRIO IO Bank)






continuedOn-Die Termination (ODT)in Ω


SSTL2 (MSIO IO Bank)



SSTL2 (MSIOD IO Bank)



Table 4-51 DDRSSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns

473 Stub-Series Terminated Logic 18V (SSTL18)SSTL18 Class I and Class II are supported in RTG4 FPGAs They also comply with the reduced and full DDR2standard The RTG4 FPGA IOs support both standards for single-ended signaling and differential signaling forSSTL18 This standard requires a differential amplifier input buffer and a push-pull output buffer

4731 Minimum and Maximum Input and Output Levels SpecificationTable 4-52 DDR2SSTL18 DC Minimum and Maximum Input and Output Levels Specification






SSTL18 DC Input Voltage Specification

VIH (DC) DC input logic high VREF +0125

mdash 189 V






SSTL18 Class I (DDR2 Reduced Drive)








(Applicable to MSIO and MSIOD banks)2

47 mdash mdash mA





(Applicable to DDRIO bank only)2

63 mdash mdash mA




SSTL18 Class II (DDR2 Full Drive)3





93 mdash mdash mA





(Applicable to DDRIO bank only)

134 mdash mdash mA






Notes 1 Maximum input leakage current for VREF is 10 μA2 MSIO and MSIOD Bank SSTL18DDR2 reduced drive does not have a standard test point This is defined to fit

within the DDR2 Reduced Drive IV curve minimums3 DDR2 full drive transmitter is used to meet the JEDEC electrical compliance4 MSIO IO Bank SSTL18DDR2 Class II does not meet the standard JEDEC test points Use provided lower

current values as specified

Table 4-53 DDR2SSTL18 AC Specifications (Applicable to DDRIO Bank Only)


SSTL18 AC Differential Voltage Specification

VDIFF

(AC)

AC input differential voltage 05 mdash mdash V





Vx (AC) AC differential cross point voltage 05 times VDDI ndash

0175

mdash 05 times VDDI +

0175

V

SSTL18 Maximum AC Switching Speed

Dmax Maximum datarate

(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)

AC loading 3 pF25Ωload


Maximum datarate

(for MSIOD IOBank)





Reference resistor =

150Ω

mdash 20 42 mdash Ω

RTT Effectiveimpedance value(ODT)


150Ω

mdash 50 75

150

mdash Ω



Cent Capacitive loading for enable path (tZH tZLtHZ and tLZ)

mdash 5 mdash pF

Rtt_test Reference resistance for data test path for

SSTL18 Class I (tDP)

mdash 50 mdash Ω


SSTL18 Class II (tDP)

mdash 25 mdash Ω






Table 4-54 DDR2SSTL18 AC Switching Characteristics for Receiver (Input Buffers)



SSTL18 (for DDRIO IO Bank with Fixed Codes)


50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns

SSTL18 (For MSIO IO Bank)


50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns

SSTL18 (For MSIOD IO Bank)


50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns

Note Data corresponds to fixed PCODE and NCODE for receiver For more information see UG0741 RTG4 FPGAIO User Guide




Table 4-55 DDR2SSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns




474 Stub-Series Terminated Logic 15V (SSTL15)SSTL15 Class I and Class II are supported in RTG4 FPGAs and also comply with the reduced and full drive doubledata rate (DDR3) standard The RTG4 FPGA IOs support both standards for single-ended signaling and differentialsignaling for SSTL18 This standard requires a differential amplifier input buffer and a push-pull output buffer

4741 Minimum and Maximum ACDC Input and Output Levels SpecificationTable 4-56 DDR3 SSTL15 DC Voltage Specification (for DDRIO IO Bank Only)













SSTL15 Class II (DDR3 Full Drive)

VOH DC output logic high 08 times VDDI mdash mdash V

VOL DC output logic low mdash mdash 02 times VDDI V

IOH atVOH

Output minimum source DC current

(Applicable to MSIO and MSIOD banks)

134 mdash mdash mA

IOL atVOL

Output minimum sink current



SSTL15 Differential Voltage Specification


Notes 1 Maximum input leakage current for VREF is 10 μA2 DDR3 full drive transmitter must be used to meet JEDEC Electrical Compliance

Table 4-57 DDR3SSTL15 AC Specifications










V

SSTL15 Maximum AC Switching Speed (for DDRIO IO Banks Only)








mdash 5 mdash pF

Rtt_test Reference resistance for data test path forSSTL18 Class I (tDP)

mdash 50 mdash Ω

Rtt_test Reference resistance for data test path forSSTL18 Class II (tDP)

mdash 25 mdash Ω



Table 4-58 DDR3STTL15 AC Switching Characteristics for Receiver (Input Buffers)

On-Die Termination (ODT) inΩ


DDR3SSTL15 (for DDRIO IO Bank)mdashCalibration Mode Only


20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

DDR3 Reduced DriveSSTL15 Class I (for DDRIO IO Bank)

Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns

DDR3 Full DriveSSTL15 Class II (for DDRIO IO Bank)

Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns

475 Low Power Double Data Rate (LPDDR)LPDDR reduced and full drive low power DDR standards are supported in the RTG4 FPGA IOs This standardrequires a differential amplifier input buffer and a push-pull output buffer This IO standard is supported in the DDRIOIO Bank only

4751 Minimum and Maximum ACDC Input and Output Levels SpecificationTable 4-60 LPDDR DC Specifications (for DDRIO IO Bank Only)






LPDDR DC Input Voltage Specification






LPDDR DC Output Voltage Specification

LPDDR Reduced Drive









LPDDR Full Drive2







Notes 1 Maximum input leakage current for LPDDR is 10 μA2 LPDDR full drive transmitter is used to meet JEDEC Electrical Compliance

Table 4-61 LPDDR Minimum and Maximum AC Switching Speeds (for DDRIO IO Bank Only)


LPDDR AC Differential Voltage Specification

VDIFF(AC)

AC input differential voltage 06 times VDDI mdash mdash V

Vx (AC) AC differential cross point voltage 04 times VDDI mdash 06 times VDDI V

LPDDR Maximum AC Switching Speed




LPDDR Impedance Specifications

Rref Supported outputdriver calibratedimpedance



Reference Resistor = 150Ω mdash 50 75 150 mdash Ω





mdash 5 mdash pF


mdash 50 mdash Ω






4752 AC Switching CharacteristicsWorst-case military conditions TJ =125 degC VDD = 114V and VDDI = 171V

Table 4-62 LPDDR AC Switching Characteristics for Receiver (Input Buffers)



LPDDR (for DDRIO IO Bank with Fixed Codes)


50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns

NoteThe data corresponds to fixed PCODE and NCODE for receiver For more information see the UG0741 RTG4FPGA IO User Guide

Table 4-63 LPDDR AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

LPDDR Reduced Drive (for DDRIO IO Bank)

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

LPDDR Full Drive (for DDRIO IO Bank)

Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns




4753 Minimum and Maximum ACDC Input and Output Levels Specification Using LPDDR-LVCMOS 18VModeTable 4-64 LPDDR-LVCMOS 18V Mode Minimum and Maximum DC Input and Output Levels (Applicable toDDRIO IO Bank Only)


LPDDR-LVCMOS 18V Recommended DC Operating Conditions


LPDDR-LVCMOS 18V Mode DC Input Voltage Specification






LPDDR-LVCMOS 18V Mode DC Output Voltage Specification



Table 4-65 LPDDR-LVCMOS 18V Maximum AC Switching Speeds (Applicable to DDRIO IO Bank Only)


LPDDR-LVCMOS 18V Maximum AC Switching Speed (for DDRIO IO Banks Only)

Dmax Maximum DataRate (for DDRIOIO Bank)



LPDDR-LVCMOS 18V AC Test Parameters Specifications





Table 4-66 LPDDR-LVCMOS 18V Mode Transmitter Drive Strength Specification (Applicable to the DDRIO IOBank Only)


2 mA VDDI ndash 045 045 2 2







continuedOutput Drive Selection VOH Min (V) VOL Max (V) IOH (mA) IOL (mA)

10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16

Note 1 16 mA drive strengths and all slews meet the LPDDR JEDEC electrical compliance




tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

Table 4-68 LPDDRmdashLVCMOS 18V AC Switching Characteristics for Transmitter DDRIO IO Bank (Output andTristate Buffers)

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns

48 Differential IO StandardsConfiguration of the IO modules as a differential pair is handled by Microchip SoC Products Group Liberoreg System-on-Chip (SoC) software when the user instantiates a differential IO macro in the design Differential IOs can also beused in conjunction with the embedded Input Register (InReg) Output Register (OutReg) Enable Register (EnReg)and Double Data Rate registers (DDR)

Figure 4-4 Differential Input Signaling Waveform Depicting VICM and VID Parameters

Note VID = | VinPndashVinN | The full amplitude range for VID is VIDmin to VIDmax or plusmnVIDmin2 to plusmnVIDmax2

481 LVDSLow-Voltage Differential Signaling (LVDS) (ANSITIAEIA-644) is a high-speed differential IO standard RTG4 LVDStransmitters are true LVDS drivers that can source and sink current

4811 Minimum and Maximum Input and Output LevelsTable 4-69 LVDS25 DC Voltage Specification (Applicable to MSIO MSIOD Banks and SerDes REFCLK Input)


LVDS25 Recommended DC Operating Conditions


LVDS25 DC Input Voltage Specification

VI DC input voltage mdash 0 mdash 2625 V








LVDS25 DC Output Voltage Specification

VOH DC output logic high mdash 125 1425 16 V

VOL DC output logic low mdash 09 1075 125 V

LVDS25 Differential Voltage Specification

VOD Differential output voltageswing

mdash 250 350 450 mV

VOCM Output common modevoltage

mdash 1125 125 1375 V

VICM1 Input common modevoltage

With On-die termination (Rt) 005 125 15 V

With external differentialtermination (Rt)

005 125 22 V

VID1 2 3 Input differential voltage mdash 200 350 2400 mV

1 VICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03V2 A 200Ω differential termination effectively doubles the differential voltage for a given drive current compared to

a 100Ω termination For example a 25 mA current produces 500 mV of differential voltage across the 200Ωtermination whereas it produces only 250 mV across a 100 Ω termination

3 Refer to Figure 4-4 for more information on VID

Table 4-70 LVDS25 AC Specifications (Applicable to MSIO MSIOD Banks and SerDes REFCLK Input)


LVDS25 Maximum AC Switching Speed


(MSIO IO Bank)

AC loading 12 pF100Ω differentialload



(for MSIOD IOBank)



LVDS25 Impedance Specification

Rt Terminationresistance

On-die termination resistance 90 100 150 Ω

External 100Ω differentialtermination2

95 100 105 Ω

External 100Ω differentialtermination1 2

190 200 210 Ω

LVDS25 AC Test Parameters Specifications





Vtrip Measuringtrip point for data path mdash Crosspoint mdash V



Notes 1 A 200Ω differential termination effectively doubles the differential voltage for a given drive current compared to

a 100Ω termination For example a 25 mA current produces 500 mV of differential voltage across the 200Ωtermination whereas it produces only 250 mV across a 100Ω termination

2 When the external termination is being used ODT must be disabled using the Libero SoC

4812 LVDS25 AC Switching CharacteristicsWorst-case military conditions TJ = 125 degC VDD = 114V and VDDI = 2375V

Table 4-71 LVDS25 Receiver Characteristics

IO Bank On-Die Termination (ODT) in Ω tPY Speed Grade ndash1 tPY Speed Grade STD Units

MSIO None 1244 1463 ns

100 1244 1463 ns

MSIOD None 1232 1448 ns

100 1232 1448 ns

Table 4-72 LVDS25 Transmitter Characteristics

IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




4813 LVDS33 AC Switching CharacteristicsWorst-case military conditions TJ = 125 degC VDD = 114 V and VDDI = 315 V

Table 4-73 LVDS33 DC Voltage Specification (Applicable to MSIO Banks and SerDes REFCLK Only)






IIH (DC) Input leakage currenthigh

mdash mdash mdash 10 microA






LVDS33 DC Differential Voltage Specification


mdash 250 350 450 mV


mdash 1125 125 1375 V

VICM1 2 3 4 Input common modevoltage

With external differentialtermination Rt

006 125 18 V

VID1 2 3 4 5 Input differential voltage With external differentialtermination Rt

500 mdash 2400 mV

Notes 1 LVDS33 receiver in VDDI = 33V supply range does not support ODT2 The termination resistance value depends on the current drive capability of the external LVDS transmitter For

example using a worst-case 25 mA current driver a 200Ω differential termination can be used to effectivelydouble the differential voltage compared to a 100Ω termination producing 500 mV of differential voltagecompared to only 250 mV across a 100Ω termination A designer must use IBIS models to simulate their circuitand determine the proper termination resistance value that will meet minimum VID and still have good signalintegrity

3 VICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03VVICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03V

4 For jitter considerations see Table 17-115 Refer to Figure 4-4 for more information on VID




Table 4-74 LVDS33 AC Specifications (Applicable to MSIO Banks and SerDes REFCLK Only)



Dmax Maximum datarate (MSIO IOBank)

AC loading for outputs 12 pF100Ω

Differential load for inputs

VID ge 500 mV



Rt1 2 Terminationresistance

External differential termination 190 200 210 Ω






example using a worst-case 25 mA current driver a 200Ω differential termination can effectively double thedifferential voltage compared to a 100Ω termination producing 500 mV of differential voltage compared to only250 mV across a 100Ω termination Designers must use IBIS models to simulate their circuit and determinethe proper termination resistance value that meets minimum VID and still has good signal integrity





IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns

482 B-LVDSBus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multipoint busapplications Multidrop and multipoint bus configurations might contain any combination of drivers receivers andtransceivers




4821 Minimum and Maximum ACDC Input and Output Levels SpecificationTable 4-77 B-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)


Bus-LVDS Recommended DC Operating Conditions


Bus-LVDS DC Input Voltage Specification





Bus-LVDS DC Output Voltage Specification (for MSIO IO Bank only)

VOH DC output logic high 125 1425 16 V

VOL DC output logic low 09 1075 125 V

Bus-LVDS Differential Voltage Specification

VOD Differential output voltage swing 65 mdash 460 mV

VOCM Output common mode voltage 11 mdash 15 V

VICM1 Input common mode voltage 005 mdash 22 V

VID1 Input differential voltage 02 mdash VDDI V

1 VICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03V

Table 4-78 B-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)


Bus-LVDS Maximum AC Switching Speed


(MSIO IO Bank)



Dmax Maximum data rate(for MSIOD IOBank)



Bus-LVDS Impedance Specifications



Bus-LVDS AC Test Parameters Specifications








Table 4-79 B-LVDS AC Switching Characteristics for Receiver (Input Buffers)




Table 4-80 B-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns

483 M-LVDSM-LVDS specifications extend the existing LVDS standard to high-performance multipoint bus applications Multidropand multipoint bus configurations might contain any combination of drivers receivers and transceivers

4831 Minimum and Maximum Input and Output LevelsTable 4-81 M-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)


M-LVDS Recommended DC Operating Conditions


M-LVDS DC Input Voltage Specification





M-LVDS DC Output Voltage Specification



M-LVDS Differential Voltage Specification




VID1 Input differential voltage 200 mdash 600 mV




Note Only M-LVDS type I is supported1 VICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03V

Table 4-82 M-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)


M-LVDS Maximum AC Switching Speed


(MSIO IO Bank)

AC loading 2 pF100Ωdifferential load


Dmax Maximum data rate(MSIOD IO Bank)



M-LVDS Impedance Specifications



M-LVDS AC Test Parameters Specifications

Vtrip Measuringtrip point for data path mdash Cross point mdash V



4832 AC Switching CharacteristicsWorst-case military conditions TJ = 125 degC VDD = 114V VDDI = 2375V

Table 4-83 M-LVDS AC Switching Characteristics for Receiver (Input Buffers)




Table 4-84 M-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns




484 Mini-LVDSMini-LVDS is a unidirectional interface from the timing controller to the column drivers and is designed according tothe Texas Instruments Standard SLDA007A

4841 Mini-LVDS Minimum and Maximum Input and Output LevelsTable 4-85 Mini-LVDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)




Mini-LVDS DC Input Voltage Specification


Mini-LVDS DC Output Voltage Specification



Mini-LVDS Differential Voltage Specification

VOD Differential output voltage swing mdash 300 mdash 600 mV

VOCM Output common mode voltage mdash 1 mdash 14 V

VICM1 Input common mode voltage With on-die termination(Rt)

005 mdash 15 V

With external differential

termination (Rt)

005 mdash 22 V

VID1 2 Input differential voltage mdash 200 mdash 600 mV

Notes 1 VICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03V2 A 200Ω differential termination effectively doubles the differential voltage for a given drive current compared to

a 100Ω termination For example a 25 mA current produces 500 mV of differential voltage across the 200Ωtermination whereas the 25 mA current produces only 250 mV across the 100Ω termination

Table 4-86 Mini-LVDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)


Mini-LVDS Maximum AC Switching Speed




Dmax Maximum DataRate (MSIOD IOBank)



Mini-LVDS Impedance Specifications








95 100 105 Ω


190 200 210 Ω

Mini-LVDS AC Test Parameters Specifications




mdash 5 mdash pF

Notes 1 When the external termination is being used ODT must be disabled using the Libero SoC2 A 200Ω differential termination effectively doubles the differential voltage for a given drive current compared to

a 100Ω termination For example a 25 mA current produces 500 mV of differential voltage across the 200Ωtermination whereas the same 25 mA current produces only 250 mV across the 100Ω termination

4842 AC Switching CharacteristicsWorst-case Military conditions TJ = 125 degC VDD = 114V and VDDI = 2375V

Table 4-87 Mini-LVDS AC Switching Characteristics for Receiver (Input Buffers)

IO Bank On-Die Termination (ODT) in Ω tPY Speed Grade ndash1 tPY Speed Grade STD Unit


100 1244 1463 ns


100 1232 1448 ns

Table 4-88 Mini-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns




485 RSDSReduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using differential signalingRSDS has a similar implementation to LVDS devices and is only intended for point-to-point applications

4851 Minimum and Maximum Input and Output LevelsTable 4-89 RSDS DC Voltage Specification (Applicable to MSIO and MSIOD Banks Only)




RSDS DC Input Voltage Specification


RSDS DC Output Voltage Specification



RSDS Differential Voltage Specification

VOD Differential outputvoltage swing

mdash 100 mdash 600 mV


mdash 05 mdash 15 V


With on-die termination (Rt) 005 mdash 15 V


005 mdash 22 V


Notes 1 VICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03V2 A 200Ω differential termination effectively doubles the differential voltage for a given drive current compared

to a 100Ω termination For example a 25 mA current produces 500 mV of differential voltage across the 20Ωtermination whereas the 25 mA current produces only 250 mV across the 100Ω termination

Table 4-90 RSDS AC Specifications (Applicable to MSIO and MSIOD Banks Only)


RSDS Maximum AC Switching Speed




Dmax Maximum datarate (MSIOD IOBank)



RSDS Impedance Specifications








95 100 105 Ω


190 200 210 Ω

RSDS AC Test Parameters Specifications




mdash 5 mdash pF




Table 4-91 RSDS AC Switching Characteristics for Receiver (Input Buffers)




100 1244 1463 ns


100 1232 1448 ns

Table 4-92 RSDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD

No pre-emphasis 1964 2309 1952 2296 1944 2287 1805 2123 1887 2220 ns

Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

486 LVPECLLow-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential IO standard It requires that one databit be carried through two signal lines Similar to LVDS two pins are needed It also requires external resistortermination RTG4 FPGAs support only LVPECL receivers and do not support LVPECL transmitters

4861 Minimum and Maximum Input LevelTable 4-93 LVPECL DC Voltage Specification (Applicable to MSIO IO Banks and SerDes REFCLK Only)




LVPECL DC Input Voltage Specification


LVPECL Differential Voltage Specification


VID1 2 Input differential voltage 600 mdash 2400 mV

Notes 1 VICM + (VID2) lt VDDI + 04V and VICM ndash (VID2) gt ndash03V2 When using LVPECL to input a clock signal see Table 17-11 and Table 13-3

Table 4-94 LVPECL Minimum and Maximum AC Switching Speeds (Applicable to MSIO IO Banks and SerDesREFCLK Only)


LVPECL Impedance Specifications


On-die terminationresistance

90 100 150 Ω

LVPECL AC Test Parameters Specifications

Fmax Maximum data rate (MSIO IO Bank) mdash mdash 700 Mbps





Table 4-95 LVPECL Receiver Characteristics



100 1204 1416 ns




49 IO Register SpecificationsThe following sections describe the input and output register specifications of the RTG4 FPGA devices

491 Input RegisterFigure 4-5 Timing Model for Input Register

Figure 4-6 IO Register Input Timing Diagram




The following table lists the input data register propagation delays in worst-case military conditions when TJ = 125 degCand VDD = 114V

Table 4-96 Input Data Register Propagation Delays

Parameter Description Measuring

Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

tICLKQ Clock-to-Q of the Input register E G 0200 0200 0235 0235 ns

tISUD Data Setup Time for the Input register A E 0652 1523 0767 1615 ns

tIHD Data Hold Time for the Input register A E ndash0209 0104 ndash0246 0148 ns

tISUE Enable Setup Time for the Input register B E 0968 1885 1138 2106 ns

tIHE Enable Hold Time for the Input register BE ndash0286 ndash0006

ndash0336 0019 ns

tISUSL Synchronous Load Setup Time for the Inputregister

D E 0828 1745 0974 1941 ns

tIHSL Synchronous Load Hold Time for the Inputregister

D E ndash0212 0067 ndash0250 0106 ns

tIALn2Q Asynchronous Clear-to-Q of the Inputregister (ADn = 1)

C G 1013 1013 1191 1191 ns

Asynchronous Preset-to-Q of the Inputregister (ADn = 0)

C G 1050 1050 1236 1236 ns

tIREMALn Asynchronous Load Removal Time for theInput register

CE ndash0500 ndash0500

ndash0588 ndash0588 ns

tIRECALn Asynchronous Load Recovery Time for theInput register

C E 0948 0948 1115 1115 ns

tIWALn Asynchronous Load Minimum Pulse Widthfor the Input register

C C 1041 1041 1225 1225 ns

tICKMPWH Clock Minimum Pulse Width High for theInput register

E E 0320 0320 0377 0377 ns

tICKMPWL Clock Minimum Pulse Width Low for theInput register

E E 0333 0333 0391 0391 ns




492 OutputEnable RegisterFigure 4-7 Timing Model for OutputEnable Register




Figure 4-8 IO Register Output Timing Diagram



Parameter Description MeasuringNodes

(from to)

SpeedGradendash1SET FilterOFF

SpeedGradendash1SET FilterON

SpeedGrade STDSET FilterOFF

SpeedGrade STDSET FilterON

Unit

tOCLKQ Clock-to-Q ofthe OutputEnableregister

E G or E I 0375 0375 0441 0441 ns

tOSUD Data Setup Timefor the OutputEnableregister

A E or J E 0622 1540 0732 1700 ns

tOHD Data Hold Time forthe OutputEnableregister

A E or J E ndash0147 0132 ndash0173 0182 ns

tOSUE Enable Setup Timefor the OutputEnableregister

B E 0972 1890 1144 2111 ns




continuedParameter Description Measuring

Nodes

(from to)





Unit

tOHE Enable Hold Timefor the OutputEnableregister

B E ndash0280 0000 ndash0329 0026 ns

tOSUSL Synchronous loadsetup time forthe OutputEnableregister

D E 0833 1750 0980 1947 ns

tOHSL Synchronous loadHold Time forthe OutputEnableregister

D E ndash0211 0069 ndash0248 0108 ns

tOALn2Q Asynchronous Clear-to-Q of the OutputEnable register

(ADn = 1)

C G or C I 1250 1250 1471 1471 ns

AsynchronousPreset-to-Q ofthe OutputEnableregister

(ADn = 0)

C G or CI 1129 1129 1329 1329 ns

tOREMALn Asynchronous LoadRemoval forthe OutputEnableregister

C E ndash0500 ndash0500 ndash0588 ndash0588 ns

tORECALn Asynchronous LoadRecovery Time forthe OutputEnableregister

C E 0918 0918 1079 1079 ns

tOWALn Asynchronous LoadMinimum Pulse widthfor the OutputEnableregister

C C 1034 1034 1216 1216 ns

tOCKMPWH Clock Minimum PulseWidth High forthe OutputEnableregister

E E 0322 0322 0379 0379 ns

tOCKMPWL Clock Minimum PulseWidth Low forthe OutputEnableregister

E E 0334 0334 0393 0393 ns




410 DDR Module SpecificationThe following sections describe input and output DDR module and timing specifications of the RTG 4FPGA devices

4101 Input DDR ModuleFigure 4-9 Input DDR Module




4102 Input DDR Timing DiagramThe following figure shows the input DDR timing diagram of the RTG4 FPGA devices

Figure 4-10 Input DDR Timing Diagram

4103 Timing CharacteristicsThe following table lists the input DDR propagation delays in worst-case military conditions when TJ = 125 degC andVDD = 114V

Table 4-98 Input DDR Propagation Delays


(from to)

SpeedGrade ndash1SET FilterOFF

SpeedGrade ndash1SET FilterON



Units

tDDRICLKQ1 Clock-to-Out Out_QRfor Input DDR

B C 0200 0200 0235 0235 ns

tDDRICLKQ2 Clock-to-Out Out_QFfor Input DDR

B D 0197 0197 0232 0232 ns

tDDRISUD Data Setup for InputDDR

A B 0652 1523 0767 1615 ns

tDDRIHD Data Hold for InputDDR

A B ndash0077 0104 ndash0091 0148 ns

tDDRISUE Enable Setup forInput DDR

E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units

tDDRIHE Enable Hold for InputDDR

E B ndash0286 ndash0006 ndash0336 0019 ns

tDDRISUSLn Synchronous LoadSetup for Input DDR

G B 0828 1745 0974 1941 ns

tDDRIHSLn Synchronous LoadHold for Input DDR

G B ndash0212 0067 ndash0250 0106 ns

tDDRIAL2Q1 Asynchronous Clear-to-Out QR for InputDDR

(ADn = 1)

F C 1013 1013 1191 1191 ns

AsynchronousPreset-to-Out QR forInput DDR

(ADn = 0)

F C 1050 1050 1236 1236 ns

tDDRIAL2Q2 Asynchronous Clear-to-Out QF for InputDDR

(ADn=1)

F D 1003 1003 1180 1180 ns

AsynchronousPreset-to-Out QF forInput DDR

(ADn=0)

F D 1044 1044 1228 1228 ns

tDDRIREMAL Asynchronous LoadRemoval Time forInput DDR

F B ndash0500 ndash0500 ndash0588 ndash0588 ns

tDDRIRECAL Asynchronous LoadRecovery Time forInput DDR

F B 0948 0948 1115 1115 ns

tDDRIWAL Asynchronous LoadMinimum Pulse Widthfor Input DDR

F F 1041 1041 1225 1225 ns

tDDRICKMPWH Clock Minimum PulseWidth High for InputDDR

B B 0334 0320 0392 0377 ns

tDDRICKMPWL Clock Minimum PulseWidth Low for InputDDR

B B 0333 0333 0391 0391 ns




4104 Output DDR ModuleThe following figure shows the output DDR module

Figure 4-11 Output DDR Module




4105 Output DDR Timing DiagramThe following figure shows the output DDR timing diagram

Figure 4-12 Output DDR Timing Diagram


Table 4-99 Output DDR Propagation Delays


(from to)





Units

tDDROCLKQ 1 Clock-to-Out of DDRfor Output DDR

E G 0375 0375 0441 0441 ns

tDDROSUDF DF Data Setup forOutput DDR

F E 0560 1478 0659 1627 ns

tDDROSUDR DR Data Setup forOutput DDR

A E 0622 1540 0732 1700 ns

tDDROHDF DF Data Hold forOutput DDR

F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units

tDDROHDR DR Data Hold forOutput DDR

A E ndash0147 0132 ndash0173 0182 ns

tDDROSUE Enable setup forOutput DDR

B E 0973 1890 1145 2112 ns

tDDROHE Enable hold for OutputDDR

B E ndash0280 0000 ndash0329 0026 ns

tDDROSUSLn Synchronous LoadSetup for Output DDR

D E 0833 1750 0980 1947 ns

tDDROHSLn Synchronous LoadHold for Output DDR

D E ndash0209 0071 ndash0246 0110 ns

tDDROAL2Q Asynchronous Clear-to-Out for Output DDR

(ADn = 1)

C G 1235 1235 1453 1453 ns

Asynchronous Preset-to-Out for Output DDR

(ADn = 0)

C G 1118 1118 1315 1315 ns

tDDROREMAL Asynchronous LoadRemoval Time forOutput DDR


tDDRORECAL Asynchronous LoadRecovery Time forOutput DDR

C E 0948 0948 1115 1115 ns

tDDROWAL Asynchronous LoadMinimum Pulse Widthfor Output DDR

C C 1034 1034 1216 1216 ns

tDDROCKMPWH Clock minimum Pulsewidth high for theOutput DDR

E E 0335 0322 0394 0379 ns

tDDROCKMPWL Clock Minimum PulseWidth Low for theOutput DDR

E E 0334 0334 0393 0393 ns

Note 1 TDDROCLKQ listed in the datasheet is the worst-case delay For specific propagation delay values in rising

versus falling clock edge analysis see the SmartTime Expanded Path Reports with the number of parallelpaths reported increased from the default value of 1




5 Logic Element SpecificationsThe following sections describe the logic element specifications of the RTG4 FPGA devices

51 LUT4The RTG4 FPGAs offer a fully permutable 4-input LUT In this section timing characteristics are presented for asample of the library For more details see the RTG4 Macro Library Guide

Figure 5-1 LUT4

511 Timing CharacteristicsThe following table lists the combinatorial cell propagation delays in worst-case military conditions when TJ = 125 degCand VDD = 114V

Table 5-1 Combinatorial Cell Propagation Delays

Combinatorial Cell Equation Parameter Speed Grade ndash1 Speed Grade STD Units

BUFD Y = A tPD 0061 0072 ns

INV Y = A tPD 0061 0072 ns

INVD Y = A tPD 0061 0072 ns

AND2 Y = A middot B tPD 0156 0183 ns

Logic Element Specifications



continuedCombinatorial Cell Equation Parameter Speed Grade ndash1 Speed Grade STD Units

NAND2 Y = (A middot B) tPD 0131 0154 ns

OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns

XOR2 Y = A oplus B tPD 0156 0183 ns

XOR3 Y = A oplus B oplus C tPD 0299 0352 ns

AND3 Y = A middot B middot C tPD 0299 0352 ns

AND4 Y = A middot B middot C middot D tPD 0418 0492 ns

52 Sequential ModuleRTG4 FPGAs offer a separate flip-flop which can be used independently from the LUT The flip-flop has a data inputand optional enable synchronous load (clear or preset) and asynchronous load (clear or preset)

Figure 5-2 Sequential Module

Figure 5-3 shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous clear) for a flip-flop




Figure 5-3 Sequential Module Timing Diagram

521 Timing CharacteristicsThe following table lists register delays in worst-case military conditions when TJ = 125 degC and VDD = 114V

Table 5-2 Register Delays

Parameter Description SpeedGradendash1SET FilterOFF




Units

TCLKQ Clock-to-Q of the core register 0207 0207 0243 0243 ns

TSUD Data setup time for the coreregister

0429 1300 0505 13 ns

THD Data hold time for the coreregister

ndash0005 0275 ndash0005 035 ns

TSUE Enable setup time for the coreregister

1098 1968 1291 2096 ns

THE Enable hold time for the inputregister

ndash0435 ndash0155 ndash0512 ndash0156 ns

TSUSL Synchronous load setup time forthe core Register

0872 1789 1025 1993 ns

THSL Synchronous load hold time forthe Core register

ndash0144 0136 ndash0169 0187 ns




continuedParameter Description Speed

Gradendash1SET FilterOFF




Units

TALN2Q Asynchronous Clear-to-Q of theCore register (ADn = 1)

1037 1037 1220 122 ns

Asynchronous Preset-to-Q ofthe core register (ADn = 0)

1066 1066 1255 1255 ns

TREMALN Asynchronous load removaltime for the core register


TRECALN Asynchronous load recoverytime for the Core register

0879 0879 1034 1034 ns

TWALN Asynchronous load minimumpulse width for the core register

0129 0129 0152 0152 ns

TCKMPWH Clock minimum pulse width highfor the core register

0142 0142 0167 0167 ns

TCKMPWL Clock minimum pulse width lowfor the core register

0201 0201 0237 0237 ns

Note This timing data represents worst-case path delays See the SmartTime Static Timing Analysis ExpandedPath Reports for propagation delays with respect to various combinations of rising or falling data and clock




6 Global Resource CharacteristicsThe RTG4 FPGA devices offer a powerful low skew global routing network which provides an effective clockdistribution throughout the FPGA fabric See the RTG4 FPGA Fabric User Guide for the positions of various globalrouting resources

The following table lists the RTG4 150 device global resources in worst-case military conditions when TJ = 125 degCand VDD = 114V

Table 6-1 RT4G150 Device Global Resource

Parameter Description Speed Grade ndash1 Speed Grade STD Units

Min Max Min Max

TRCKL Input Low Delay for Global Clock 326 3649 3836 4291 ns

TRCKH Input High Delay for Global Clock 3721 4161 4377 4895 ns

TRCKSW Maximum Skew for Global Clock mdash 044 mdash 0518 ns

Global Resource Characteristics



7 FPGA Fabric SRAMThe following sections describe the FPGA Fabric SRAM of the RTG4 FPGA devices See the UG0574 RTG4 FPGAFabric User Guide for more information

71 FPGA Fabric Large SRAM (LSRAM)The following table lists the RAM1K18mdashdual-port mode for depth times width configuration 1K times 18 in worst-case militaryconditions when TJ = 125 degC and VDD = 114V

Table 7-1 RAM1K18mdashDual-Port Mode for Depth times Width Configuration 1Kx18

Parameter Description Speed

Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TCY Clock Period with all pipelines enabled 4000 4762 4717 5616 ns

TCLKMPWH Clock Minimum Pulse Width High 0600 0600 0600 0600 ns

TCLKMPWL Clock Minimum pulse Width Low 0600 0600 0600 0600 ns

TADDRSU Address Setup Time (ECC = OFF) 1996 2345 2349 2759 ns

Address Setup Time (ECC = BYPASS)1 mdash 2345 mdash 2759 ns

Address Setup Time (ECC = PIPELINE) 1760 1894 2070 2228 ns

TADDRHD Address Hold Time (ECC = OFF) ndash0006 ndash0255 ndash0007 ndash0299 ns

Address Hold Time (ECC = BYPASS)1 mdash ndash0255 mdash ndash0299 ns

Address Hold Time (ECC = PIPELINE) ndash0123 0129 ndash0145 0152 ns

TDSU Data Setup Time 2127 2159 2502 2539 ns

TDHD Data Hold Time ndash0218 0036 ndash0257 0042 ns

TBLKSU Block Select Setup Time (ECC = OFF) 1934 1948 2286 2291 ns

Block Select Setup Time (ECC = BYPASS)1 mdash 1948 mdash 2291 ns

Block Select Setup Time (ECC = PIPELINE) 1725 1831 2029 2154 ns

TBLKHD Block Select Hold Time (ECC = OFF) ndash0375 ndash0022 ndash0441 ndash0026 ns

Block Select Hold Time (ECC = BYPASS)1 mdash ndash0022 mdash ndash0026 ns

Block Select Hold Time (ECC = PIPELINE) ndash0319 ndash0078 ndash0375 ndash0092 ns

TRDENPIPESU Pipelined Read Enable Setup Time(A_DOUT_EN B_DOUT_EN)

2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TRDENPIPEHD Pipelined Read Enable Hold Time (A_DOUT_ENB_DOUT_EN)


TRSTREM Asynchronous Reset Removal Time 1118 1118 1315 1315 ns

TRSTREC Asynchronous Reset Recovery Time ndash0801 ndash0801 ndash0942 ndash0942 ns

TRSTMPW Asynchronous Reset Minimum Pulse Width 0587 0587 0587 0587 ns

TSRSTSU Synchronous Reset Setup Time 2292 2212 2696 2602 ns

TSRSTHD Synchronous Reset Hold Time ndash0615 ndash0250 ndash0724 ndash0294 ns

TRDESU Read Enable Setup Time 1479 1863 1740 2191 ns

TRDEHD Read Enable Hold Time 0029 ndash0207 0034 ndash0244 ns

TWESU Write Enable Setup Time with Simple write mode(ECC = OFF)

1505 2005 1771 2358 ns

Write Enable Setup Time with Simple write mode(ECC = BYPASS)1

2005 2358 ns

Write Enable Setup Time with ECC = PIPELINE 4015 4121 4723 4848 ns

TWEHD Write Enable Hold Time with Simple write mode(ECC = OFF)

0131 ndash0105 0154 ndash0124 ns

Write Enable Hold Time with Simple write mode(ECC = BYPASS)1

mdash ndash0105 ndash0124 ns

Write Enable Hold Time with ECC = PIPELINE ndash0176 0076 ndash0207 0089 ns

TCLK2Q Read Access Time with OUTPUT=PIPELINE 2090 2090 2458 2458 ns

Read Access Time with ECC=OFFOUTPUT=BYPASS

5694 5694 6698 6698 ns

Read Access Time with ECC=BYPASSOUTPUT=BYPASS1

mdash 6607 mdash 7773 ns

Read Access Time with ECC=PIPELINEOUTPUT=BYPASS

4204 4204 4946 4946 ns

TR2Q Asynchronous Reset to Output PropagationDelay

1373 1373 1615 1615 ns

FMAX Maximum Frequency with all pipelines enabled 250 210 212 178 MHz

FPGA Fabric SRAM



Note 1 ECC = BYPASS mode also known as non-pipelined ECC mode is not supported with SET filter OFF

The following table lists the RAM1K18mdashtwo-port mode for depth times width configuration 512 times 36 in worst-case militaryconditions when TJ = 125 degC and VDD = 114V

Table 7-2 RAM1K18mdashTwo-Port Mode for Depth x Width Configuration 512 x 36


Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


















TRDPLESU Pipelined Read Enable Setup Time(A_DOUT_EN

B_DOUT_EN)

2136 2635 2513 3100 ns

TRDPLEHD Pipelined Read Enable Hold Time(A_DOUT_EN B_DOUT_EN)




FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




TRDESU Read Enable Setup Time without ECC pipeline 1479 1861 1740 2189 ns

TRDEHD Read Enable Hold Time without ECC pipeline 0029 ndash0207 0034 ndash0244 ns

TWESU Write Enable Setup Time (ECC = OFF) 1508 2007 1774 2361 ns

Write Enable Setup Time (ECC = BYPASS)1 2007 2361 ns

Write Enable Setup Time (ECC = PIPELINE) 3976 4082 4678 4802 ns

TWEHD Write Enable Hold Time (ECC = OFF) 0131 ndash0105 0154 ndash0124 ns

Write Enable Hold Time (ECC = BYPASS)1 mdash ndash0105 mdash ndash0124 ns

Write Enable Hold Time (ECC = PIPELINE) ndash0176 0076 ndash0207 0089 ns



5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM



72 FPGA Fabric Micro SRAM (microSRAM)The following table lists the microSRAM in 64 times 18 mode in worst-case military conditions when TJ = 125 degC and VDD =114V



Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




TADDRSU Read Address Setup Time with INPUT =PIPELINE

1828 2384 2150 2805 ns

Read Address Setup Time with INPUT =BYPASS

ECC = PIPELINE

4262 4262 5013 5013 ns


ECC = OFF OUTPUT = PIPELINE

4642 5254 5461 6181 ns


ECC = BYPASS OUTPUT = PIPELINE

6929 7541 8151 8871 ns

TADDRHD Read Address Hold Time with INPUT =PIPELINE


Read Address Hold Time with INPUT =BYPASS

ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TBLKSU Read Block Select Setup Time with INPUT= PIPELINE

2032 2483 2390 2922 ns

Read Block Select Setup Time with INPUT= BYPASS

ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns

TBLKHD Read Block Select Hold Time with INPUT =PIPELINE


Read Block Select Hold Time with INPUT =BYPASS

ECC = PIPELINE








TBLKMPW Read Block Select Minimum Pulse WidthLow

0350 0350 0350 0350 ns

TRSTREM Read Asynchronous Reset Removal Time 0987 0987 1161 1161 ns

TRSTREC Read Asynchronous Reset Recovery Time ndash0566 ndash0566 ndash0666 ndash0666 ns


TRDENADDRSU Read Address Read Enable Setup Time

(A_ADDR_EN B_ADDR_EN)

1538 1977 1810 2326 ns

TRDENADDRHD Read Address Read Enable Hold Time


ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TRDSRSTADDRSU Read Address Synchronous Reset SetupTime

(A_ADDR_SRST_N B_ADDR_SRST_N)

1566 2005 1842 2358 ns

TRDSRSTADDRHD Read Address Synchronous Reset HoldTime


ndash0183 0061 ndash0216 0072 ns

TRDENPIPESU Pipelined Read Enable Setup Time

(A_DOUT_EN B_DOUT_EN)

1503 1941 1768 2284 ns

TRDENPIPEHD Pipelined Read Enable Hold Time


ndash0152 0092 ndash0178 0109 ns

TRDSRSTPIPESU Pipelined Read Synchronous Reset SetupTime

(A_DOUT_SRST_N B_DOUT_SRST_N)

1837 2337 2161 2750 ns

TRDSRSTPIPEHD Pipelined Read Synchronous Reset HoldTime



TCCY Write Clock Period all pipeline enabled 3922 3922 4630 4630 ns

TCCLKMPWH Write Clock Minimum Pulse Width High 0526 0526 0526 0526 ns

TCCLKMPWL Write Clock Minimum Pulse Width Low 0526 0526 0526 0526 ns

TBLKCSU Write Block Setup Time (ECC = OFF orECC = BYPASS)

1575 2083 1853 2451 ns

Write Block Setup Time (ECC = PIPELINE) 1305 1908 1535 2245 ns

TBLKCHD Write Block Hold Time (ECC = OFF or ECC= BYPASS)


Write Block Hold Time (ECC = PIPELINE) ndash0320 ndash0629 ndash0376 ndash0740 ns

TDINCSU Write Input Data setup Time 1238 1960 1456 2306 ns

TDINCHD Write Input Data hold Time 0100 ndash0321 0118 ndash0377 ns

TADDRCSU Write Address Setup Time (ECC = OFF orECC = BYPASS)

1591 2017 1872 2373 ns

Write Address Setup Time (ECC =PIPELINE)

1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TADDRCHD Write Address Hold Time (ECC = OFF orECC = BYPASS)


Write Address Hold Time (ECC =PIPELINE)

0028 ndash0281 0033 ndash0331 ns

TWECSU Write Enable Setup Time (ECC = OFF orECC = BYPASS)

1437 1945 1690 2288 ns

Write Enable Setup Time (ECC =PIPELINE)

1158 1760 1363 2070 ns

TWECHD Write Enable Hold Time (ECC = OFF orECC = BYPASS)


Write Enable Hold Time (ECC = PIPELINE) ndash0054 ndash0313 ndash0063 ndash0369 ns

TCLK2Q Read Access Time with OUTPUT =PIPELINE

1726 1726 2030 2030 ns

Read Access Time with ECC = PIPELINE

OUTPUT = BYPASS

4557 4557 5361 5361 ns

Read Access Time with INPUT =PIPELINE ECC = OFF

OUTPUT = BYPASS

4371 4371 5142 5142 ns

Read Access Time with INPUT =PIPELINE

ECC = BYPASS OUTPUT = BYPASS

6767 6767 7960 7960 ns

TADDR2Q Read Address to Out Data Access timewith

INPUT = BYPASS ECC = OFF OUPUT =BYPASS

6257 6257 7360 7360 ns

Read Address to Out Data Access Timewith

INPUT = BYPASS ECC = BYPASSOUPUT = BYPASS

8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TBLK2Q Read Block Select to Out Disable Time with


3569 3569 4199 4199 ns

Read Block Select to Out Disable Time with


5899 5899 6940 6940 ns

TR2Q Read Asynchronous Reset to OutputPropagation Delay

1237 1237 1456 1456 ns

FMAX Maximum Frequency with all pipelinesenabled

255 255 216 216 MHz

The following table lists the μSRAM in 128 times 12 mode in worst-case military conditions when TJ = 125 degC and VDD =114V

Table 7-4 μSRAM (RAM64 x 18) in 128 x 12 Mode


Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TCY Read Clock Period with all pipelinesenabled

3922 3922 4630 4630 ns

TCLKMPWH Read Clock Minimum Pulse Width High 0526 0526 0526 0526 ns

TCLKMPWL Read Clock Minimum pulse Width Low 0526 0526 0526 0526 ns


1828 2384 2150 2805 ns

Read Address Setup Time with

INPUT = BYPASS OUTPUT =PIPELINE

4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



Read Address Hold Time with



TBLKSU Read Block Select Setup Time INPUT =PIPELINE

2032 2483 2390 2922 ns

Read Block Select Setup Time


1996 2608 2348 3068 ns

TBLKHD Read Block Select Hold Time withINPUT = PIPELINE


Read Block Select Hold Time with




0350 0350 0350 0350 ns

TRSTREM Read Asynchronous Reset RemovalTime

0987 0987 1161 1161 ns

TRSTREC Read Asynchronous Reset RecoveryTime


TRSTMPW Asynchronous Reset Minimum PulseWidth

1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

TRDSRSTADDRSU Read Address Synchronous ResetSetup Time

(A_ADDR_SRST_NB_ADDR_SRST_N)

1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns

TRDSRSTPIPESU Pipelined Read Synchronous ResetSetup Time

(A_DOUT_SRST_NB_DOUT_SRST_N)

1837 2337 2161 2750 ns







TBLKCSU Write Block Setup Time 1575 2083 1853 2451 ns

TBLKCHD Write Block Hold Time ndash0190 ndash0427 ndash0224 ndash0502 ns


TDINCHD Write Input Data hold Time ndash0033 ndash0404 ndash0039 ndash0475 ns

TADDRCSU Write Address Setup Time 1591 2017 1872 2373 ns

TADDRCHD Write Address Hold Time ndash0110 ndash0453 ndash0129 ndash0533 ns

TWECSU Write Enable Setup Time 1437 1945 1690 2288 ns

TWECHD Write Enable Hold Time ndash0139 ndash0376 ndash0164 ndash0442 ns


1725 1725 2029 2029 ns

Read Access Time with INPUT =PIPELINE OUTPUT = BYPASS

4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units

TADDR2Q Read Address to Out Data Accesstime with INPUT = BYPASS OUPUT =BYPASS

6180 6180 7270 7270 ns

TBLK2Q Read Block Select to Out Disable Timewith INPUT = BYPASS OUPUT =BYPASS

3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns

Read Address Setup Time with INPUT =BYPASS OUTPUT = PIPELINE

4642 5254 5461 6181 ns



Read Address Hold Time with INPUT =BYPASS OUTPUT = PIPELINE


FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns

Read Block Select Setup Time INPUT =BYPASS OUTPUT = PIPELINE

1996 2608 2348 3068 ns

TBLKHD Read Block Select Hold Time with INPUT= PIPELINE


Read Block Select Hold Time with INPUT= BYPASS OUTPUT = PIPELINE



0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM



8 FPGA Fabric Micro PROM (μPROM)The following table lists the μPROM in worst-case military conditions when TJ = 125 degC and VDD = 114V

Table 8-1 μPROM


TCY Read Clock Period 20 20 ns

TCLKMPWH Read Clock Minimum Pulse Width High 0153 018 ns

TCLKMPWL Read Clock Minimum Pulse Width Low 014 0164 ns

TADDRSU Read Address Setup Time 474 5576 ns

TADDRHD Read Address Hold Time 0513 0604 ns

TRSTREC Read Asynchronous Reset Recovery Time 7064 831 ns

TRSTREM Read Asynchronous Reset Removal Time 0 0 ns

TRSTMPW Asynchronous Reset Minimum Pulse Width 7034 8274 ns

TCLK2Q Read Access Time 1094 1287 ns


5526 6501 ns

FPGA Fabric Micro PROM (μPROM)



9 JTAGThe following table lists the JTAG timing characteristics in worst-case military conditions when TJ = 125 degC and VDD= 114V

Table 9-1 JTAGIEEE-1532 Timing Characteristics


TTCK2Q Clock to Q (data out) 131 1541 ns

TRSTB2Q Reset to Q (data out) 327 3847 ns

TDISU Test Data Input Setup Time 636 748 ns

TDIHD Test Data Input Hold Time 206 243 ns

TTMSSU Test Mode Select Setup Time ndash118 ndash097 ns

TTMDHD Test Mode Select Hold Time 267 314 ns

TTRSTREM ResetB Removal Time 1709 201 ns

TTRSTREC ResetB Recovery Time 1708 201 ns

FTCKMAX TCK maximum frequency 25 2125 MHz

91 Live ProbeThe following table lists the Live Probe in worst-case military conditions when TJ = 125 degC and VDD = 114V

Table 9-2 Live Probe

Symbol Description Speed Grade ndash1 Speed Grade STD Units

FLPROBE Live probe maximum frequency 100 85 MHz

JTAG



10 Power-up to Functional TimesThe following table lists the power-up to functional times in worst-case military conditions when TJ = 125 degC and VDD= 114V

Table 10-1 Power-up to Functional Times

Parameter From To Maximum Power-up to FunctionalTime

Units

TNoGRST2OUT Flipflops without GRESET orRGRESET

Output available 702 micros

TRGRST2OUT Flipflops with RGRESET active Output available 702 micros

TRGRST2GRST Flipflops with RGRESET active Flipflops with GRESET active 741 micros

TRGRST2POR Flipflops with RGRESET active POWER_ON_RESET_N 73 micros

TPOR2GRST POWER_ON_RESET_N Flipflops with GRESET 007 micros

TVDD2OUT VDD Output Available 7344 ms

TVDD2WPU VDD WPU (weak pull-up) 7166 ms

TVDD2RGRST VDD Flipflops without GRESET orRGRESET

7351 ms

Flipflops with RGRESET active

TVDD2GRST VDD Flipflops with GRESET active 7352 ms

TVDD2POR VDD POWER_ON_RESET_N 7352 ms

TOUT2POR Output available POWER_ON_RESET_N 0286 micros

Power-up to Functional Times



Figure 10-1 Power-up to Functional Times




11 Device Reset DEVRST_NThe following table lists the DEVRST_N in worst-case military conditions when TJ = 125 degC and VDD = 114 V

Table 11-1 DEVRST_N Characteristics

Symbol Description Min Typ Max Units

TRAMPDEVRSTN DEVRST_N ramp time (10 to 90) mdash mdash 1 μs

FMAXPDEVRSTN DEVRST_N cycling rate mdash mdash 100 kHz

MPWDEVRSTN DEVRST_N pulse width 1 mdash mdash μs

Table 11-2 DEVRST_N to Functional Times

Parameter From To MaximumDEVRST_N toFunctional Time

Units

TNoGRST2OUT Flipflops without GRESETor RGRESET


TRGRST2OUT Flipflops with RGRESETactive


TRGRST2GRST Flipflops with RGRESETactive

Flipflops with GRESET active 741 micros

TRGRST2POR Flipflops with RGRESETactive

POWER_ON_RESET_N 73 micros


TDEVRST2OUT DEVRST_N Output Available 1936 micros

TDEVRST2WPU DEVRST_N WPU (weak pull-up) 407 micros

TDEVRST2RGRST DEVRST_N Flipflops without GRESET orRGRESET

1929 micros

TDEVRST2RGRST DEVRST_N Flipflops with RGRESET active 1929 micros

TDEVRST2GRST DEVRST_N Flipflops with GRESET active 193636 micros

TDEVRST2POR DEVRST_N POWER_ON_RESET_N 193629 micros


Device Reset DEVRST_N



Figure 11-1 DEVRST_N to Functional Timing Diagram for RTG4

VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N

FlipFlops with No GRESET or RGRESET

SetReset User Control

LowHigh

FlipFlops with GRESET

TD EVR ST2R GR ST

User Control

Tri-stateWeak pullup

User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T




12 On-Chip OscillatorThe following table describes the electrical characteristics of the available on-chip oscillators in the RTG4 FPGAsWorst-case military conditions TJ = 125 degC and VDD = 114V

Table 12-1 Electrical Characteristics of the 50 MHz RC Oscillator

Parameter Description Condition Min Typ Max Units

F50RC Operatingfrequency

mdash 4625 50 5375 MHz

ACC50RC Accuracy mdash mdash 1 75

CYC50RC Output duty cycle mdash 46 mdash 54

JIT50RC Output jitter

(peak to peak)

Period Jitter mdash 100 200 ps

Cycle-to-Cycle jitter mdash 80 160 ps

Output jitter

(peak to peak)

with FPGA fabric

switching noise1

Period jitter mdash 250 350 ps


IDYN50RC Operating current mdash mdash 85 mdash mA

Note 1 Noise is generated by 32 of fabric registers with a switching rate of 25 driven by a 100 MHz clock

On-Chip Oscillator



13 Clock Conditioning Circuits (CCC)The following table lists the CCCPLL specifications in worst-case military conditions when TJ = 125 degC and VDD =114 V

Table 13-1 RTG4 FPGAs CCCPLL Specification

Parameter Conditions Min Typ Max Units

Clock conditioning circuitryinput frequency fIN_CCC

PLL is bypassed or PLL referencedivider value is high enough to limitPLL input frequency to within the rangeof 10 MHz to 200 MHz at PLL Phaseand Frequency Detector (PFD)

10 mdash 400 MHz

Clock conditioning circuitryoutput frequency fOUT_CCC 1

mdash 0078 mdash 425 MHz

PLL input frequency fIN_PLL At the PLL PFD input after the CCCreference divider

10 200 MHz

PLL VCO frequency2 mdash 500 mdash 1000 MHz

Delay increments inprogrammable delay blocks

mdash mdash 100 150 ps

Number of programmable

values in eachprogrammable delay block

mdash mdash mdash 64 mdash

Acquisition time mdash mdash mdash 500 micros

Output duty cycle fOUT_CCC le 185 MHz 48 mdash 54

185 MHz lt fOUT_CCC le 300 MHz 48 mdash 56


PLL_ARST_N pulse width mdash 1 mdash mdash micros

Loop Bandwidth3 mdash fPFD8 mdash fPFD6 MHz

Output Clock Jitter Period jitter (peak-to-peak) mdash mdash See Table13-2

ps

Notes 1 The minimum output clock frequency is limited by the PLL For more information see the Fabric PLL Circuitry

section in the RTG4 FPGA Clocking Resources User Guide2 The PLL is used in conjunction with the Clock Conditioning Circuitry Performance will be limited by the CCC

output3 fPFD is equivalent to the Input Frequency (fIN) divided by the input reference divider

Clock Conditioning Circuits (CCC)



Table 13-2 Fabric PLL Output Clock Jitter Specification

Ref Clock

IO Standard

Input Voltage Condition Operating

Temperature (degC)

Max Output Clock Jitter

(Peak-To-Peak Period Jitter)

Unit

Single-endedand VoltageReferenced

NA ndash55 le Tj le 125 Max (80 ps 2 times (1fIN)) + (145 timesInput jitter)

ps

LVDS25HCSL RSDSBLVDS M-LVDSMiniLVDS

VID and VICM See tables

bull LVDS25 DCVoltage Specification(Applicable to MSIOMSIOD Banks andSerDes REFCLK Input)

bull B-LVDS DCVoltage Specification(Applicable to MSIOand MSIOD BanksOnly)

bull M-LVDS DCVoltage Specification(Applicable to MSIOand MSIOD BanksOnly)

bull Mini-LVDS DCVoltage Specification(Applicable to MSIOand MSIOD BanksOnly)

bull RSDS DCVoltage Specification(Applicable to MSIOand MSIOD BanksOnly)

bull HCSL DCVoltage Specification(Applicable to SerDesREFCLK Only)

ndash55 le Tj le 125 Max (80 ps 2 times (1fIN)) + (145 timesInput jitter)

ps

Differential33V MSIOinput LVPECLLVDS33

VID ge VICM ndash55 le Tj le 125 Max (80 ps 2 times (1fIN)) + (145 timesInput jitter)

ps


bull LVDS33 DCVoltage Specification(Applicable to MSIOBanks and SerDesREFCLK Only)

bull LVPECL DCVoltage Specification(Applicable to MSIOIO Banks and SerDesREFCLK Only)

ndash55 le Tj le 125 Max (140 ps 2 times (1fIN)) + (145times Input jitter)

ps

25 le Tj le 125 Max (80 ps 2 times (1fIN)) + (145 timesInput jitter)

ps




Note For additional worst-case jitter specifications see Table 17-12 The clock jitter equations apply down to 10 MHzFIN

Table 13-3 Maximum MSIO Input Buffer Jitter Added to Input Clocks Directly Driving Globals

Ref Clock

IO Standard

Input Voltage Condition Operating Temperature(degC)

Max Output Clock Jitter(Peak-To-Peak PeriodJitter)

Unit

Single-endedand voltagereferenced

NA ndash55 le Tj le 125 Max (100 ps 2 times (1fIN)) ps

LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS


bull LVDS25 DCVoltage Specification(Applicable to MSIOMSIOD Banks andSerDes REFCLKInput)






ndash55 le Tj le 125 Max (100 ps 2 xtimes (1fIN)) ps




continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33

VID ge VICM ndash55 le Tj le 125 Max (150 ps 4 times (1fIN)) ps




ndash55 le Tj le 125 Max (300 ps 8 times (1fIN)) ps

25 le Tj le 125 Max (100 ps 2 times (1fIN)) ps

1 fIN is frequency of the external input clock which can enter the FPGA fabric through the global input bufferswithout passing through a CCCPLL or through the input buffers going into a CCC for division only (bypassingPLL) before being promoted to global buffers See jitter specifications in Table 13-2 if the input clock passesthrough a PLL

2 The clock jitter equations apply down to 10 MHz fIN




14 System Controller SPI CharacteristicsThe following table lists the system controller SPI characteristics in worst-case military conditions when TJ = 125 degCand VDD = 114V

Table 14-1 System Controller SPI Characteristics (All DevicesSpeed Grades)

Symbol Description Conditions Min Typ Max Units

sp1 SC_SPI_SCK minimumperiod

mdash 25 mdash mdash ns

sp2 SC_SPI_SCK minimumpulse width

high


sp3 SC_SPI_SCK minimumpulse width low


sp41 SC_SPI_SCKSC_SPI_SDOSC_SPI_SS rise time(10ndash90)

IO Configuration LVTTL 33Vndash16mA AC Loading 35 pF TestConditions Typical Voltage 25 degC

mdash 143 mdash ns

sp51 SC_SPI_SCKSC_SPI_SDOSC_SPI_SS fall time(10ndash90)


mdash 145 mdash ns

sp6 SC_SPI_SDI setup time mdash 2 mdash mdash ns

sp7 SC_SPI_SDI hold time mdash 2 mdash mdash ns

Note For specific risefall times board design considerations and detailed output buffer resistances use thecorresponding IBIS models at wwwmicrochipcom The supported IO configurations must be used for the systemcontroller SPI as shown in Table 11-2

Table 14-2 Supported IO Configurations for System Controller SPI (for MSIO Bank Only)

Voltage Supply IO Drive Configuration Units

33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA

The following table provides timing information for the APB configuration interface of dynamic CCC FDDR memorycontroller and High-Speed Serial Interface (SerDes) components It is an embedded APB slave interface within theFPGA fabric that does not use FPGA resources

Table 14-3 APB Configuration Interface Timing Characteristics

Parameter Symbol Max Unit

APB clock frequency APB_S_PCLK 5375 MHz

System Controller SPI Characteristics



15 Mathblock Timing CharacteristicsThe fundamental building block in any digital signal processing algorithm is the multiply-accumulate functionEach RTG4 mathblock supports 18 x 18 signed multiplication dot product and built-in addition subtraction andaccumulation units to combine multiplication results efficiently The following table lists the math blocks with allregisters used in worst-case military conditions for TJ = 125 degC and VDD = 114V

Table 15-1 Mathblocks With All Registers Used

Speed Grade ndash1 Speed Grade STD

Parameter Description SET FilterOFF

SET FilterON

SET FilterOFF

SET FilterON

Units

TMISU Input Control Register Setuptime

0073 1007 0086 0956 ns

TMIHD Input Control Register Holdtime

0456 0618 0536 0730 ns

TMOCDINSU CDIN Input Setup time 1514 2532 1782 2749 ns

TMOCDINHD CDIN Input Hold time 0026 0156 0031 0186 ns

TMSRSTENSU Synchronous ResetEnableSetup time

1234 2105 1452 2247 ns

TMSRSTENHD Synchronous ResetEnableHold time

0228 0358 0268 0424 ns

TMARSTREM Asynchronous Reset Removaltime

-0456 -0456 -0536 -0536 ns

TMARSTREC Asynchronous Reset Recoverytime

0601 0601 0707 0707 ns

TMOCQ Output Register Clock to Outdelay

0961 0961 1131 1131 ns

TMCLKMP CLK Minimum period 3333 4000 3333 4000 ns

The following table lists the mathblock with input bypassed and output registers used in worst-case militaryconditions when TJ = 125 degC and VDD = 114V

Table 15-2 Mathblock With Input Bypassed and Output Registers Used



SET FilterON

SET FilterOFF

SET FilterON

Units

TMOSU Output Register Setup time 2383 3368 2804 3732 ns

TMOHD Output Register Hold time ndash0232 ndash0069 ndash0273 ndash0079 ns




1234 2105 1452 2247 ns

Mathblock Timing Characteristics



continuedSpeed Grade ndash1 Speed Grade STD


SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns


The following table lists the mathblock with input register used and output in bypass mode in worst-case militaryconditions when TJ = 125 degC and VDD = 114V

Table 15-3 Mathblock with Input Register Used and Output in Bypass Mode



SET FilterON

SET FilterOFF

SET FilterON

Units

TMISU Input Register Setup time 0073 1007 0086 0956 ns

TMIHD Input Register Hold time 0456 0618 0536 0730 ns


1229 2100 1446 2241 ns


0205 0334 0241 0396 ns

TMARSTREM Asynchronous ResetRemoval time


TMARSTREC Asynchronous ResetRecovery time

0601 0601 0707 0707 ns

TMICQ Input Register Clock toOutput delay

3171 3171 3731 3731 ns

TMCDIN2Q CDIN to Output delay 2852 2852 3355 3355 ns




The following table lists the mathblock with input and output in bypass mode in worst-case military conditions whenTJ = 125 degC and VDD = 114V

Table 15-4 Mathblock with Input and Output in Bypass Mode



SET Filter ON SET Filter OFF SET Filter ON Units

TMIQ Input to outputdelay

2912 2912 3426 3426 ns

TMCDIN2Q CDIN to outputdelay

2040 2040 2400 2400 ns




16 IO Delay Block CharacteristicsThe following table lists the IO programmable delay block timing characteristics in worst-case military conditionswhen TJ = 125 degC and VDD = 114V

Table 16-1 IO Programmable Delay Block Timing Characteristics

Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns

IO Delay Block Characteristics



continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns




17 SerDes Electrical and Timing CharacteristicsThe RTG4 FPGAs have up to four hard high-speed serial interface blocks Each SerDes block contains a PCIesystem block The PCIe system is connected to the SerDes block Worst-case military conditions TJ = 125 degC andVDD = 114V The SerDes can also be used for XAUI and generic EPCS interfaces For more information aboutSerDes electrical and timing AC and DC characteristics see the CR0028 RTG4 FPGA Characterization Report forXAUI and the CR0031 RTG4 PCIe Characterization Report

Table 17-1 Transmitter Parameters

Parameter Description Min Typ Max Units

VTXCM Output common mode voltage mdash mdash 20 mV

TRISE-TIME Tx rise time (20ndash80) 0125 mdash mdash UI

TFALL-TIME Tx fall time (20ndash80) 0125 mdash mdash UI

ROUT Differential output impedance 80 mdash 120 Ω

TLLSKEW Lane-to-lane Tx skew within a SerDes block mdash mdash 500 ps + 2 UI ps

RLTX-DIFF Return loss differential mode mdash mdash ndash10 dB

RLTX-CM Return loss common mode mdash mdash ndash6 dB

TRESET-LOCK Transmit PLL lock time from reset mdash mdash 10 micros

FSPLL-VCO1 SPLL VCO frequency range 500 mdash 1000 MHz

FTXPLL-VCO 1 Tx PLL VCO frequency range 2000 mdash 5000 MHz

FTXRate Transmitter serial data rate 10 mdash FMAXCvR2 Gbps

Notes 1 Follow valid frequency range setting in the Libero SoC software2 For FMAXCvR see Table 17-9

Note See protocol-specific tables Table 17-3 and Table 17-8 for PCIe Gen1 XAUI and SRIO additionalcharacteristics

Table 17-2 Receiver Parameters


VRXCM Input common mode voltage (AC coupled) mdash mdash 150 mV

RIN Differential input termination 80 100 120 Ω

REXT External calibration resistor 1188 1200 1212 Ω

TCDRRESET-Lock CDR relock time from reset mdash mdash 15 micros

CID1 CID limit mdash mdash 200 UI

VRXIDLEDET Electrical Idle detect threshold (differential peak-to-peak) 65 mdash 75 mV

FRXRate Receiver serial data rate 10 mdash FMAXCvR2 Gbps

SerDes Electrical and Timing Characteristics



Notes 1 AC-coupled BER = e-12

2 For FMAXCvR see Table 17-9

Note See the protocol-specific tables for PCIe Gen1 XAUI and SRIO additional characteristics

Table 17-3 Transmitter (PCIE Gen1)


VTX-DIFF-PP Differential swing 08 mdash 12 V

TJ (1E-12) Total jitter mdash mdash 025 UI

Note PCIe compliance pattern used for jitter

Table 17-4 Receiver (PCIE Gen1)


VRX-DIFF-PP-CC Differential input

peak-to-peak sensitivity

0238 12 V

RX-JTOL Receiver jitter tolerance 04 mdash mdash UI

RLRX-DIFF Return loss differential mode mdash mdash ndash10 dB

RLRX-CM Return loss common mode mdash mdash ndash6 dB

Notes bull With add-in card as specified in the PCI Express CEM Rev 20bull PCIe compliance pattern used for JTOLbull BER error criteria for JTOL is 10ndash12

Table 17-5 SRIO Transmitter

Parameter Description Condition Min Max Units

TSRIO-RISE-TIME Rise time 20 to 80 60 mdash ps

TSRIO-FALL-TIME Fall time 80 to 20 60 mdash ps

VTX-SRIO-VOD Output amplitude Short reach 05 1 V

TJTX-SRIO Total transmit jitter Far end mdash 065 UI

Note CJPAT pattern is used

Table 17-6 SRIO Receiver


JTOLRX-SRIO Receive jitter tolerance 10ndash12 BER 065 Ulp-p

RLRX-SRIO-DIFF Return loss differential mode mdash mdash ndash8 dB

RLRX-SRIO-CM Return loss differential mode mdash mdash ndash6 dB

Note CJPAT pattern is used for JTOL




Table 17-7 XAUI Transmitter


TXAUI-RISE-TIME Rise time 20 to 80 60 130 ps

TXAUI-FALL-TIME Fall time 80 to 20 60 130 ps

VTX-XAUI-VOD Output amplitude Short reach 02 12 V

TJTX-XAUI Total transmit jitter Far end mdash 055 UI

DJTX-XAUI Deterministic jitter Far end mdash 037 UI


Table 17-8 XAUI Receiver


JTOLRX-XAUI Receive jitter tolerance 10ndash12 BER 065 mdash Ulp-p

RLRX-XAUI-DIFF Return loss differential mode mdash mdash ndash101 dB

RLRX-XAUI-CM Return loss differential mode mdash mdash ndash62 dB

Notes 1 With regard to 100Ω2 With regard to 25Ω


Table 17-9 SerDes Protocol Compliance

Protocol Maximum Data Rate (FMAXCVR) Speed Grade ndash1 Speed Grade STD

PCIe Gen 1 25 Gbps Yes Yes

Generic EPCS 3125 Gbps Yes No

Generic EPCS 25 Gbps Yes Yes

SRIO 3125 Gbps Yes No

SRIO 25 Gbps Yes Yes

XAUI 3125 (x4 lanes) Yes No

Note For more information see the UG0567 RTG4 FPGA High-Speed Serial Interfaces User Guide

Table 17-10 SerDes Reference Clock AC Specifications

Symbols Description Min Typ Max Units

FREFCLK Reference Clock Frequency 100 mdash 160 MHz

TRISE Reference Clock Rise Time 06 mdash 4 Vns

TFALL Reference Clock Fall Time 06 mdash 4 Vns

TCYC Reference Clock Duty Cycle 40 mdash 60

MmREFCLK1 Reference Clock Mismatch ndash300 mdash 300 ppm




continuedSymbols Description Min Typ Max Units

SSCref Reference Spread Spectrum Clock 0 mdash 5000 ppm

Note 1 MmREFCLK is the ppm difference between REFCLKs in systems using independent reference clocks

Table 17-11 Worst-Case SerDes Transmit Jitter Per REFCLK IO Standard

LVPECL1 LVDS331 LVDS25 HCSLLVCMOS25

TJ Range (degC) ndash55

to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125

Worst CaseTotal TransmitJitter (ps)

360 80 107 360 80 107 100

VICM2 (V) 06 ndash 18 06 ndash 18 06 ndash183

06 ndash18

06 ndash 18 06 ndash183

See tables

bull LVCMOS 25 V DCVoltage Specification


bull HCSL DCVoltage Specification(Applicable to SerDesREFCLK only)

VID2 5 (V) 06 ndash 24 06 ndash 24 06 ndash243

05 ndash24


Restriction None4 RestrictedOperatingTempRange

VID geVICM

None4 RestrictedOperatingTempRange

VID geVICM

Notes 1 For the lowest possible jitter on SerDes TX outputs running at 3125 Gbps across the full Mil-Temp range use

LVDS25 differential inputs for the SerDes REFCLK receiver with SERDES_VDDI set to 25 V and design theinterface to meet a minimum VICM of 600 mV

2 VICM + (VID2) lt VDDI + 04 V and VICM ndash (VID2) gt ndash03 V3 VID ge VICM4 If no measures are taken such as limiting operating temperature range or meeting VID ge VICM relationship

then the SerDes will still start-up at ndash55 degC to 25 degC range but the maximum total transmit jitter could exceedthe TX jitter limits of the serial protocol in use until TJ rises to ge25 degC


For additional worst-case jitter specifications see Table 17-12




Table 17-12 RTG4 Global NetworkmdashMax Period Jitter

Global Net Jitter (Peak-to-Peak) Unit

FF Used (of Total FFs in Device)1 2 15 25 50

Average Toggle Rate4 30 30 30

Effective FF Toggle Percentage3 45 75 150

ndash1 plusmn200 plusmn250 plusmn400 ps

ndash1 400 500 800 ps

STD plusmn300 plusmn400 plusmn650 ps

STD 600 800 1300 ps

Notes 1 Flip-Flop (FF) used is defined as the percentage of total device FFs (out of 151824 total) that are switching

in a given clock domain2 The 50 FF used per clock domain is only shown to illustrate the impact of high utilization on a global clock

netrsquos jitter Typical designs are expected to have less than 25 FF used per clock domain (as defined in thepreceeding note)

3 Effective FF toggle percentage is the product of FF used and average toggle rate In the table above jitter isspecified for an average toggle rate of 30 To determine jitter for a given combination multiply FF used andaverage toggle rate then use linear interpolation as shown in Figure 17-1

4 Measured jitter is generated at varying FF used levels with a switching rate of 305 For a clock from an input buffer (except 33V differential inputs) feeding a global network use jitter value as

specified in Table 17-126 For a clock from an LVDS33LVPECL input buffer feeding a global network use maximum jitter of Table 17-12

or Table 13-37 For a PLL reference clock from input buffer output of PLL feeding a global net use maximum jitter of Table

17-12 or Table 13-28 For a PLL reference clock from global net output of PLL feeding a global net use maximum jitter of Table

17-12 or Table 13-29 For a PLL reference clock from global output of PLL feeding output buffer use maximum jitter of Table 17-12

or Table 13-210 All measurements were taken by observing the clock from the FPGA output pin11 For further details see UG0586 RTG4 FPGA Clocking Resources User Guide (section Global Net Clock

Jitter)

bull Example 1 If FF used is 18 and the average toggle rate is 25 the effective toggle percentage is 45The corresponding peak-to-peak jitter is 400 ps (ndash1) and 600 ps (ndashSTD)

bull Example 2 If FF used is 50 and the average toggle rate is 20 the effective toggle percentage is 10The corresponding peak-to-peak jitter can be determined by performing linear interpolation among the 3 datapoints as shown in Figure 17-1 The resulting peak-to-peak jitter in this case would be 605 ps (ndash1) and 966 ps(ndashSTD)




Figure 17-1 Peak-to-Peak Jitter vs Effective Toggle Percentage

Table 17-13 SerDes Reference Clock Phase Noise

Parameter Phase Noise Data Rate TxRefClk Max Units

FTxRefPN 10 KHz 25 Gbps 125 MHz ndash118 dBcHz

100 KHz 25 Gbps 125 MHz ndash117 dBcHz

1 MHz 25 Gbps 125 MHz ndash140 dBcHz




Note The phase noise requirements must be met to achieve jitter specifications in worst-case military conditions Ifthe desired reference clock frequency (TxRefClk) is not listed the phase noise requirements should be adjusted by20 times log10 (TxRefClk15625 MHz)

Table 17-14 HCSL DC Voltage Specification (Applicable to SerDes REFCLK only)

Symbols Parameters Min Typ Max Units



HCSL DC Input Voltage Specification


HCSL Differential Voltage Specification

VICM1 With on-die termination (Rt) 005 mdash 15 V

With external differential termination (Rt) 005 mdash 22 V




continuedSymbols Parameters Min Typ Max Units

VID1 2 3 Input differential voltage 200 mdash 1100 mV

Notes 1 VICM + (VID2) lt VDDI + 04 V and VICM ndash (VID2) gt ndash03V2 A 200Ω differential termination effectively doubles the differential voltage for a given drive current compared to


3 VID = | VinP ndash VinN |

The SerDes REFCLK input also supports LVDS25 and LVDS33 standards For DC specification see Table 4-69 andTable 4-73

Table 17-15 HCSL AC Specifications (Applicable to SerDes REFCLK only)


HCSL Maximum AC Switching Speed

Fmax Maximum data rate mdash mdash 350 Mbps

HCSL Impedance Specifications

Rt On-die termination resistance 90 100 150 Ω

External 100Ω differential termination1 95 100 105 Ω

External 200Ω differential termination1 2 190 200 210 Ω






18 SpaceWire Clock and Data RecoveryTable 18-1 SpaceWire Clock and Data Recovery Characteristics

Symbol Description Conditions Min Typ Max(ndash1)

Max(STD)

Units

FSWCLK Recoveredclockfrequency

Bank MSIOMSIOD SETMitigation OFF

No of available channels 14

1 mdash 100 90 MHz

Bank DDRIO SET MitigationOFF


1 mdash 66 58 MHz

Bank MSIOMSIOD SETMitigation ON


1 mdash 75 66 MHz

Bank DDRIO SET MitigationON


1 mdash 66 58 MHz

DSW Recovereddata rate



2 mdash 200 180 Mbps










TSWCLKCYC Recoveredclock dutycycle

mdash mdash 50 mdash mdash

TSWDSS3 Rx input datato strobeseparation

mdash mdash 500 times

(1FSWCLK)

mdash mdash ns

JITSWIN1 Jittertolerance onData orStrobe inputs

mdash mdash mdash 200 200 ps

JITSWCLK2 RecoveredClock Jitter

Period Jitter (peak to peak) mdash 200 500 500 ps

SpaceWire Clock and Data Recovery



continuedSymbol Description Conditions Min Typ Max

(ndash1)Max(STD)

Units

SupportedReceiver IOStandards

LVTTL See the 4621 Minimum and Maximum ACDCInput and Output Levels Specification section forACDC specifications

LVDS See the 481 LVDS section for ACDCspecifications

Notes 1 Input Jitter Tolerance (JITSWIN) includes jitter on strobe and data inputs and any deviation of strobe and

data from their ideal timing Deviation from this specification degrades timing performance and may requirecompensation using the programmable delay cell available in the IO For more information see AC444Implementing SpaceWire Clock and Data Recovery in RTG4 FPGA Application Note

2 Represents Recovered Clock jitter when Strobe and Data Input jitter are negligible (lt15 ps RMS) As theSpaceWire clock recovery circuit does not include a jitter filtering mechanism additional jitter on the Strobeand Data inputs is passed to the recovered clock in addition to the inherent jitter of the recovery circuit itselfTherefore the input jitter on the Strobe and Data inputs should be minimized as much as possible Assumingthat the input jitter follows a Gaussian distribution around the ideal input edge the following formula can beused to calculate the impact of the input jitter for a given system Effective Recovered Clock jitter = (05 timesData Input jitter) + (05 times Strobe Input jitter) + JITSWCLK The Recovered Clock jitter represents a jitter windowaround the ideal recovered clock edge position and therefore can be used with SmartTime Static TimingAnalysis as plusmn(05 times Effective Recovered Clock jitter)

3 The unit for the referenced FSWCLK is MHz

Figure 18-1 Spacewire Timing Diagram




19 Temperature Sensing DiodeThe following table lists the temperature diode maximum current

Table 19-1 Temperature Diode Maximum Current

Symbol Parameter Conditions Min Typ Max Units

Idiode Diode current mdash mdash mdash 10 mA

The following table lists two ways of calculating temperature sensing diode accuracy based on sample data obtainedduring characterization

Table 19-2 Temperature Sensing DiodemdashSample Data 1 and Calculation

Temperature

forced on

package

VBE when Idiode = 200 microA (V) m calculated

using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517

ndash5500 degC 000 degC

ndash40 degC 0875 ndash4002 degC 002 degC

0 degC 0824 ndash184 degC 184 degC

25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC

125 degC 0653 12621 degC ndash121 degC


Temperature

forced on

package

VBE when Idiode = 200microA (V)

m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC

TJ calculated using mand T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234

ndash5190 degC ndash310 degC

ndash40 degC 0875 ndash3728 degC ndash272 degC

0 degC 0824 000 degC 000 degC

25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC

Temperature Sensing Diode



20 Revision HistoryRevision Date Description

B 092021 bull Updated RT4G150 FCGFC1657 device status to ldquoProductionrdquo (SAR120390)

bull Updated list of RTG4 FPGA Technical Briefs and Pin Descriptionsbull Corrected units from ldquoMbpsrdquo to ldquoMHzrdquo in Table 4-2 Maximum IO

Frequency Summary for Worst-Case Military Conditionsbull Updated Table 1-3 Operating Limits with in-flight programming

information (SAR 120023) and table notes with RTG4 μPROM readcycle endurance (SAR 111814)

bull Clarified full amplitude range for VID inndash Note 3 under Table 4-69 LVDS25 DC Voltage Specification

(Applicable to MSIO MSIOD Banks and SerDes REFCLK Input)(SAR 117013)

ndash Note 5 under Table 4-73 LVDS33 DC Voltage Specification(Applicable to MSIO Banks and SerDes REFCLK Only) (SAR119167)

ndash Note 5 under Table 17-11 Worst-Case SerDes Transmit Jitter PerREFCLK IO Standard (SAR 119167)

bull Added ldquoDEVRST_N pulse widthrdquo information to Table 11-1 DEVRST_NCharacteristics (SAR 110457 and SAR 118784)

bull Added ldquoLoop Bandwidthrdquo information and note 3 to Table 13-1 RTG4FPGAs CCCPLL Specification (SAR 87429)

bull Updated ldquoMax Output Clock Jitter (Peak-to-Peak Period Jitter)rdquo column(SAR 116796) and added note (SAR 118045) in

ndash Table 13-2 Fabric PLL Output Clock Jitter Specificationndash Table 13-3 Maximum MSIO Input Buffer Jitter Added to Input

Clocks Directly Driving Globalsbull Updated Max APB Clock Frequency to 5375 MHz in Table 14-3 APB

Configuration Interface Timing Characteristics (SAR 118080)bull Updated Table 17-12 RTG4 Global NetworkmdashMax Period Jitter along

with table notes examples and graph (SAR 117259)bull Added footnote 3 to clarify the unit for TSWDSS in Table 18-1

SpaceWire Clock and Data Recovery Characteristics (SAR 120388)

A 092020 Following is the summary of changesbull The document was updated as per Microchip standardsbull Document ID was changed from DS0131 to DS00003669Abull Added FCGFC1657 package to Table 1bull Added references in the 2 Technical Briefs and Pin Descriptions

sectionbull Added FCGFC1657 package to the 113 Thermal Characteristics

sectionbull Updated table title of Table 4-2 Replaced IO Frequency with IO Data

Ratebull Added miminmum data values which were incorrectly placed in the

Conditions column of Table 4-6bull Added clear Figure 11-1

Revision History



continuedRevision Date Description

70 072020 Following is a summary of changesbull Corrected HSTL15 to SSTL18 in Table 4-55bull Added table note 3 to Table 4-69bull Added table note 5 to Table 4-73bull Added Note to Table 5-2bull Added + (145 x Input Jitter) to Table 13-2bull Corrected units from μs to ms in rows TVDD2OUT through TVDD2POR

in Table 10-1bull Added Table 14-3bull Removed protocol-specific parameters from Table 17-1 and Table 17-2bull Added Table 17-3 and Table 17-4bull Added Table 17-5 and Table 17-6bull Added Table 17-7 and Table 17-8bull Added SRIO parameters to Table 17-9bull Added Table 17-12

60 082019 Following is a summary of changesbull Table 1 was updated and note was addedbull Recommended Operating Conditions was updated with a notebull Operating Limits table and notes were updatedbull Power-Up Sequence section was updated with referencesbull Table 1-5 was updated with ΘJA information and table notesbull Table 2-2 was updated with IDC Low Power parameterbull Table 4-73 note was updatedbull Table 4-74 note was updatedbull Table 4-99 was updated with a notebull Table 13-1 was updated with PLL_ARST_N informationbull Table 17-1 was updated with rows for SPLL VCO frequency range and

Tx PLL VCO frequency rangebull Table 17-9 was updated with XAUI informationbull Table 17-13 was addedbull Table 19-1 was added

Revision History



Revision Date Description

50 082018 Following is the summary of changesbull Information about RTG4 device status was updatedbull Information about maximum input buffer jitter was addedbull Differential Input signaling waveform diagram was addedbull Information about RAM1K18 - Dual-Port Mode for Depth x Width

Configuration 1Kx18 was updatedbull Information about fabric PLL output clock jitter specification was addedbull A footnote about input leakage current of VREF was addedbull Information about FPGA operating limits was updatedbull Information about receiver parameters was updatedbull A footnote about AC transient limit of VDD and VDDI was addedbull Timing diagram of Spacewire characteristics was addedbull Information about tristate leakage current (IOZ) was addedbull Information about combinatorial cell propagation delays was updatedbull Replaced ramp rate with ramp time for DEVRST_N characteristicsbull Information about JTAG AC timing was addedbull DEVRSTN to functional timing waveform diagram was updated

40 072018 Following is the summary of changesbull Information about worst-case SerDes transmit jitter per REFCLK IO

standard was addedbull Information about LVDS33 AC and DC voltage specification was

updated to clarify these specifications are applicable to MSIO Banksand SerDes REFCLK only

bull A footnote is added for VID in the LVDS33 DC Voltage Specification(Applicable to MSIO Banks and SerDes REFCLK Only) table

bull A footnote is added for VID in the LVPECL DC Voltage Specification(Applicable to MSIO IO Banks and SerDes REFCLK Only) table

bull Tables were updated to state that non-pipelined ECC mode is notsupported with SET Filter OFF

30 112017 Following is the summary of changesbull Information about AC FPGA core supply voltage was addedbull Information about IDC was added as a footnotebull Updated IO buffer tristate timing figurebull Information about VIH max specification for IO standards was updatedbull Information about DC input differential voltage (VID) was updatedbull Information about RAM1K18 ndash Dual-Port Mode for Depth times Width

Configuration 2Kx12 and 2Kx9 was removed from section FPGA FabricLarge SRAM (LSRAM)

bull Information about MSIO HCSL Fmax was addedbull Information about DC supply voltage for LVDS25 and LVDS33

differential IO Banks was addedbull Updated section Power-Up and Power-Down Sequencebull Information about stand-alone verify was added as a note to FPGA

Operating Limits table

Revision History




30 112017 bull Information about Clock conditioning circuitry output frequencyfOUT_CCC was updated

bull Information about VOH and VOL is updated in LVCMOS 5V DC outputvoltage and transmitter drive strength specifications

bull Information about Reference Clock Mismatch (MmREFCLK) is added asa footnote to SerDes Reference Clock AC Specifications table

bull Information about limitation associated with DDRIO when used forSpaceWire was added

bull Reference of CR0028 RTG4 FPGA Characterization Report for XAUIand CR0031 RTG4 PCIe Characterization Report was added to sectionSerDes Electrical and Timing AC and DC Characteristics

bull Information about IO programmable delay block timing characteristicswas added

bull Information about SLE DDR IO and MATH interface register data wasupdated

bull Information about LVDS25 VID specification was updated

Footnotes are added for VICM and VID in the Mini-LVDS DC VoltageSpecification (Applicable to

MSIO and MSIOD Banks Only)bull The Fmax of LVPECL and LVDS33 is updatedbull Information about LPDDRLVCMOS speed was correctedbull Information about programming current was addedbull Information about Quiescent Supply Current was updatedbull Information about package thermal resistance for LG1657 and

CQFP352 devices was added and for CCGA1657 was updatedbull Information about SerDes IO absolute maximum voltage was addedbull Information about power supply grouping requirements was added as a

note to Recommended Operating Conditions tablebull Removed reference to RT4G075 device from this documentbull A table and a figure are added for high temperature data retentionbull In differential IO MSIO is updated for LVPECL (input only) and LVDS 3

Vbull HSTL 5V DC Output Voltage Specification is updated for IOH at VOH

and IOL at VOLbull Values and a footnote are updated for LVDS25 DC Differential Voltage

Specification in the LVDS25 DC Voltage Specification (Applicable toMSIO and MSIOD Banks Only)

bull Values and a footnote are updated for LVDS25 Impedance Specificationin the LVDS25 AC Specifications (Applicable to MSIO and MSIODBanks Only)

bull A footnote is added for VICM in the LVDS33 DC Voltage Specification(Applicable to MSIO Banks Only) table

bull A footnote is added for VICM in the B-LVDS DC Voltage Specification(Applicable to MSIO and MSIOD Banks Only) table

Revision History




30 112017 bull A footnote is added for VICM and VID in the M-LVDS DC VoltageSpecification (Applicable to MSIO and MSIOD Banks Only) table

bull Footnotes are added for VICM and VID in the RSDS DC VoltageSpecification (Applicable to MSIO and MSIOD Banks Only) table

bull Footnotes are added for VICM and VID in the RSDS AC Specifications(Applicable to MSIO and MSIOD Banks Only) table

bull Footnotes are added for VICM and VID in the Mini-LVDS DC VoltageSpecification (Applicable to MSIO and MSIOD Banks Only) table

bull Footnotes are added for Rt in the Mini-LVDS AC Specifications(Applicable to MSIO and MSIOD Banks Only) table

bull A footnote is added for VICM and VID in the LVPECL DC VoltageSpecification (Applicable to MSIO IO Banks Only) table

bull A note is added for Input Jitter Tolerance in the SpaceWire Clock andData Recovery Characteristics table

bull The Temperature Sensing Diode section is addedbull Values of Maximum DEVRST_N to Functional Time are updated for

TDEVRST2GRST and TVDD2PORbull Values are updated for Rt and footnotes are added in the HCSL AC

Specifications (Applicable to SerDes REFCLK only) tablebull The Power-Up and Power-Down Sequence section is updated for

SERDES_x_Lyz_VDDAIO Requirementsbull Values about Input Data Register Propagation Delays OutputEnable

Data Register Propagation Delays Input DDR Propagation DelaysOutput DDR Propagation Delays and Register Delays are updated

bull Information about FPGA operating limits was updatedbull Information about Input capacitance was updatedbull Information about IO Weak Pull-UpPull-Down Resistance Values for

DDRIO MSIO and MSIOD Banks was updated (SAR 75909)bull Updated minimum parameter values for IOH at VOH and IOL at VOLbull Information about LVDS25 DC Voltage Specification (Applicable to

MSIO and MSIOD Banks Only) was updatedbull Information about LVDS25 AC Voltage Specification (Applicable to

MSIO and MSIOD Banks Only) was updatedbull Information about LVDS33 DC Voltage Specification (Applicable to

MSIO Banks Only) and LVDS33 AC Voltage Specification (Applicableto MSIO Banks Only) was added

bull Information about LVDS33 Receiver Characteristics was updatedbull Information about B-LVDS AC and DC Voltage Specification was

updatedbull Information about B-LVDS AC Switching Characteristics for Receiver

was updatedbull Information about M-LVDS AC and DC Voltage Specification was

updatedbull Information about M-LVDS AC Switching Characteristics for Receiver

was updatedbull Information about RSDS AC and DC Voltage Specification was updatedbull Information about Mini-LVDS AC and DC Voltage Specification was

updatedbull Information about LVPECL DC Voltage Specification was updated

Revision History




30 112017 bull Updated TWESU TWEHD and F Max parametersbull Information about Spacewire Clock and Data Recovery Characteristics

was updatedbull Information about CCCPLL Specification was updatedbull Information about Electrical Characteristics of the 50 MHz RC Oscillator

was updatedbull Information about Live Probe was addedbull Information about Power-up to Functional Times was addedbull Information about DEVRST_N to Functional Times was addedbull Information about DEVRST_N Characteristics was updatedbull Information about System Controller SPI Characteristics was updatedbull Information about SerDes Electrical and Timing AC and DC

Characteristics was updatedbull Information about SerDes Protocol Compliance was added

20 Updated section Power-Up and Power-Down Sequence

10 This was the initial release of the document

Revision History



The Microchip WebsiteMicrochip provides online support via our website at wwwmicrochipcom This website is used to make files andinformation easily available to customers Some of the content available includes

bull Product Support ndash Data sheets and errata application notes and sample programs design resources userrsquosguides and hardware support documents latest software releases and archived software

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bull Business of Microchip ndash Product selector and ordering guides latest Microchip press releases listing ofseminars and events listings of Microchip sales offices distributors and factory representatives

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Customer SupportUsers of Microchip products can receive assistance through several channels

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Customers should contact their distributor representative or ESE for support Local sales offices are also available tohelp customers A listing of sales offices and locations is included in this document

Technical support is available through the website at wwwmicrochipcomsupport

Microchip Devices Code Protection FeatureNote the following details of the code protection feature on Microchip products

bull Microchip products meet the specifications contained in their particular Microchip Data Sheetbull Microchip believes that its family of products is secure when used in the intended manner within operating

specifications and under normal conditionsbull Microchip values and aggressively protects its intellectual property rights Attempts to breach the code

protection features of Microchip product is strictly prohibited and may violate the Digital Millennium CopyrightAct

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code Codeprotection does not mean that we are guaranteeing the product is ldquounbreakablerdquo Code protection is constantlyevolving Microchip is committed to continuously improving the code protection features of our products

Legal NoticeThis publication and the information herein may be used only with Microchip products including to design testand integrate Microchip products with your application Use of this information in any other manner violates theseterms Information regarding device applications is provided only for your convenience and may be supersededby updates It is your responsibility to ensure that your application meets with your specifications Contact yourlocal Microchip sales office for additional support or obtain additional support at wwwmicrochipcomen-ussupportdesign-helpclient-support-services



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All other trademarks mentioned herein are property of their respective companiescopy 2021 Microchip Technology Incorporated and its subsidiaries All Rights Reserved

ISBN



Quality Management SystemFor information regarding Microchiprsquos Quality Management Systems please visit wwwmicrochipcomquality



AMERICAS ASIAPACIFIC ASIAPACIFIC EUROPECorporate Office2355 West Chandler BlvdChandler AZ 85224-6199Tel 480-792-7200Fax 480-792-7277Technical SupportwwwmicrochipcomsupportWeb AddresswwwmicrochipcomAtlantaDuluth GATel 678-957-9614Fax 678-957-1455Austin TXTel 512-257-3370BostonWestborough MATel 774-760-0087Fax 774-760-0088ChicagoItasca ILTel 630-285-0071Fax 630-285-0075DallasAddison TXTel 972-818-7423Fax 972-818-2924DetroitNovi MITel 248-848-4000Houston TXTel 281-894-5983IndianapolisNoblesville INTel 317-773-8323Fax 317-773-5453Tel 317-536-2380Los AngelesMission Viejo CATel 949-462-9523Fax 949-462-9608Tel 951-273-7800Raleigh NCTel 919-844-7510New York NYTel 631-435-6000San Jose CATel 408-735-9110Tel 408-436-4270Canada - TorontoTel 905-695-1980Fax 905-695-2078

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Worldwide Sales and Service



Introduction

1 Device Status

2 Technical Briefs and Pin Descriptions

Table of Contents

1 General Specifications

11 Operating Conditions

111 OvershootUndershoot Limits

112 Power-Up and Power-Down Sequence

1121 Power-Up Sequence

1122 Power-Down Sequence

113 Thermal Characteristics

1131 Theta-JB

1132 Theta-JC

2 Power Consumption

21 Quiescent Supply Current

211 Programming Currents

3 Junction Temperature and Derating Factors

4 User IO Characteristics

41 Input Buffer

42 Output Buffer and AC Loading

43 Tristate Buffer and AC Loading

44 IO Speeds

45 Detailed IO Characteristics

46 Single-Ended IO Standards

461 Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)

462 33V LVCMOSLVTTL

4621 Minimum and Maximum ACDC Input and Output Levels Specification

4622 AC Switching Characteristics

463 25V LVCMOS



464 18V LVCMOS

4641 Minimum and Maximum ACDC Input and Output Levels


465 15V LVCMOS



466 12 V LVCMOS

4661 Minimum and Maximum Input and Output Levels Specification


467 33V PCIPCIX



47 Memory Interface and Voltage Reference IO Standards

471 High-Speed Transceiver Logic





472 Stub-Series Terminated Logic

4721 Stub-Series Terminated Logic 25V (SSTL2)








475 Low Power Double Data Rate (LPDDR)



4753 Minimum and Maximum ACDC Input and Output Levels Specification Using LPDDR-LVCMOS 18V Mode


48 Differential IO Standards

481 LVDS

4811 Minimum and Maximum Input and Output Levels

4812 LVDS25 AC Switching Characteristics


482 B-LVDS



483 M-LVDS



484 Mini-LVDS

4841 Mini-LVDS Minimum and Maximum Input and Output Levels


485 RSDS



486 LVPECL

4861 Minimum and Maximum Input Level


49 IO Register Specifications

491 Input Register

492 OutputEnable Register

410 DDR Module Specification

4101 Input DDR Module

4102 Input DDR Timing Diagram

4103 Timing Characteristics

4104 Output DDR Module

4105 Output DDR Timing Diagram


5 Logic Element Specifications

51 LUT4


52 Sequential Module


6 Global Resource Characteristics

7 FPGA Fabric SRAM

71 FPGA Fabric Large SRAM (LSRAM)

72 FPGA Fabric Micro SRAM (microSRAM)

8 FPGA Fabric Micro PROM (μPROM)

9 JTAG

91 Live Probe

10 Power-up to Functional Times

11 Device Reset DEVRST_N

12 On-Chip Oscillator

13 Clock Conditioning Circuits (CCC)

14 System Controller SPI Characteristics

15 Mathblock Timing Characteristics

16 IO Delay Block Characteristics

17 SerDes Electrical and Timing Characteristics

18 SpaceWire Clock and Data Recovery

19 Temperature Sensing Diode

20 Revision History

The Microchip Website

Product Change Notification Service

Customer Support

Microchip Devices Code Protection Feature

Legal Notice

Trademarks

Quality Management System


Table of Contents

Introduction1

1 Device Status 12 Technical Briefs and Pin Descriptions 1

1 General Specifications 4

11 Operating Conditions4

2 Power Consumption 11

21 Quiescent Supply Current 11

3 Junction Temperature and Derating Factors 13

4 User IO Characteristics 14

41 Input Buffer1442 Output Buffer and AC Loading 1543 Tristate Buffer and AC Loading 1644 IO Speeds 1745 Detailed IO Characteristics1946 Single-Ended IO Standards2047 Memory Interface and Voltage Reference IO Standards3348 Differential IO Standards 5649 IO Register Specifications70410 DDR Module Specification 75

5 Logic Element Specifications 81

51 LUT48152 Sequential Module82

6 Global Resource Characteristics85

7 FPGA Fabric SRAM 86

71 FPGA Fabric Large SRAM (LSRAM) 8672 FPGA Fabric Micro SRAM (microSRAM)90

8 FPGA Fabric Micro PROM (μPROM)100

9 JTAG 101

91 Live Probe 101

10 Power-up to Functional Times102

11 Device Reset DEVRST_N104

12 On-Chip Oscillator106

13 Clock Conditioning Circuits (CCC) 107

14 System Controller SPI Characteristics111

15 Mathblock Timing Characteristics112












Legal Notice 134

Trademarks 135











ndash03 136 V



ndash03 363 V


ndash03 363 V


ndash03 132 V


ndash03 275 V


ndash03 363 V


ndash03 363 V


ndash03 375 V


ndash03 275 V


ndash03 285 V



ndash03 275 V

















114 12 126 V


315 33 345 V


315 33 345 V

SERDES_x_Lyz_VDDAIO


114 12 126 V



2375 25 2625 V


171 18 189 V


2375 25 2625 V


315 33 345 V


049 times

SERDES_VDDI

05 times

SERDES_VDDI

051 times

SERDES_VDDI

V






114 12 126 V


1425 15 1575 V


171 18 189 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V





Programming

Temperature

Operating

Temperature

Programming

Cycles

Verify Cyclesper

Program Cycle


Retention1

(BiasedUnbiased)

Min TJ = 0 degC

Max TJ = 85 degC


Max TJ = 125 degC

200 200 50 Krad 10 years

Notes














90 20

95 20

100 20

105 20

110 20

115 20

120 14

125 10

130 72

135 53

140 39

145 28

150 21

























ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where














CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW












FPGA Core VDD On

VPP On

VDDPLL 0V



VDDIx2 3 On

VREF0 VREF94 On













VDD 114 756

VDDI 2375 41

Power Consumption




VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2


Power Consumption





Core Voltage

VDD (V)


114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090






































HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps



















LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz







HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz



















Note




R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)

at VOH KΩ






25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191








15V LVCMOS 60 mV

12V LVCMOS 20 mV







































mdash 2k mdash Ω



mdash 5 mdash pF





2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16




tPY tPYS Units



MSIO None 1993 2345 2122 2497 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns



































mdash 2k mdash Ω



mdash 5 mdash pF






MSIO IOBank

MSIOD IOBank


VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)













tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns


2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns












































mdash 2k mdash Ω









tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns






































(with Fixed Code)


(mA)

IOL

(mA)










tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units


None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns








































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns






















mdash V


mdash V








mdash 5 mdash pF





tPY tPYS Units



MSIO None 2097 2467 2226 2619 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns




















HSTL18 Class I





45 mdash mdash mA






40 mdash mdash mA






54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA
















V



(for DDRIO IO Bank)


Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)




(for DDRIO IO Bank)



(ODT)


mdash Ω




mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω










50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns


















HSTL 15V Class I






80 mdash mdash mA




70 mdash mdash mA




80 mdash mdash mA































(for DDRIO IO Bank)


mdash Ω
















478 0606 0712 ns


478 0616 0725 ns

MSIO








MSIOD





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns










































V



(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)








mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω





















tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns










mdash 189 V















47 mdash mdash mA






63 mdash mdash mA









93 mdash mdash mA






134 mdash mdash mA












VDIFF

(AC)







0175


0175

V



(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)



Maximum datarate

(for MSIOD IOBank)






150Ω




150Ω

mdash 50 75

150

mdash Ω




mdash 5 mdash pF



mdash 50 mdash Ω



mdash 25 mdash Ω











50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns





















IOH atVOH



134 mdash mdash mA

IOL atVOL

















V









mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω








20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns


Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns















LPDDR Reduced Drive









LPDDR Full Drive2











VDIFF(AC)
















mdash 5 mdash pF


mdash 50 mdash Ω












50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns



tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns


Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns






































10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16





tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns


tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns























mdash 250 350 450 mV


mdash 1125 125 1375 V




005 125 22 V









(MSIO IO Bank)




(for MSIOD IOBank)







95 100 105 Ω


190 200 210 Ω
















100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




















mdash 250 350 450 mV


mdash 1125 125 1375 V



006 125 18 V


500 mdash 2400 mV














VID ge 500 mV















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns



























(MSIO IO Bank)






















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns



























(MSIO IO Bank)



















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns


















005 mdash 15 V


termination (Rt)

005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF







100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns


















mdash 05 mdash 15 V




005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF








100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD


Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

















90 100 150 Ω










100 1204 1416 ns













Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units






ndash0336 0019 ns


D E 0828 1745 0974 1941 ns


D E ndash0212 0067 ndash0250 0106 ns


C G 1013 1013 1191 1191 ns


C G 1050 1050 1236 1236 ns





C E 0948 0948 1115 1115 ns


C C 1041 1041 1225 1225 ns


E E 0320 0320 0377 0377 ns


E E 0333 0333 0391 0391 ns












(from to)





Unit


E G or E I 0375 0375 0441 0441 ns


A E or J E 0622 1540 0732 1700 ns




B E 0972 1890 1144 2111 ns





Nodes

(from to)





Unit


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0211 0069 ndash0248 0108 ns


(ADn = 1)

C G or C I 1250 1250 1471 1471 ns


(ADn = 0)

C G or CI 1129 1129 1329 1329 ns




C E 0918 0918 1079 1079 ns


C C 1034 1034 1216 1216 ns


E E 0322 0322 0379 0379 ns


E E 0334 0334 0393 0393 ns














(from to)





Units


B C 0200 0200 0235 0235 ns


B D 0197 0197 0232 0232 ns


A B 0652 1523 0767 1615 ns


A B ndash0077 0104 ndash0091 0148 ns


E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units




G B 0828 1745 0974 1941 ns


G B ndash0212 0067 ndash0250 0106 ns


(ADn = 1)

F C 1013 1013 1191 1191 ns


(ADn = 0)

F C 1050 1050 1236 1236 ns


(ADn=1)

F D 1003 1003 1180 1180 ns


(ADn=0)

F D 1044 1044 1228 1228 ns




F B 0948 0948 1115 1115 ns


F F 1041 1041 1225 1225 ns


B B 0334 0320 0392 0377 ns


B B 0333 0333 0391 0391 ns














(from to)





Units


E G 0375 0375 0441 0441 ns


F E 0560 1478 0659 1627 ns


A E 0622 1540 0732 1700 ns


F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units


A E ndash0147 0132 ndash0173 0182 ns


B E 0973 1890 1145 2112 ns


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0209 0071 ndash0246 0110 ns


(ADn = 1)

C G 1235 1235 1453 1453 ns


(ADn = 0)

C G 1118 1118 1315 1315 ns




C E 0948 0948 1115 1115 ns


C C 1034 1034 1216 1216 ns


E E 0335 0322 0394 0379 ns


E E 0334 0334 0393 0393 ns








Figure 5-1 LUT4





INV Y = A tPD 0061 0072 ns








OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns


















Units



0429 1300 0505 13 ns


ndash0005 0275 ndash0005 035 ns


1098 1968 1291 2096 ns




0872 1789 1025 1993 ns


ndash0144 0136 ndash0169 0187 ns









Units


1037 1037 1220 122 ns


1066 1066 1255 1255 ns




0879 0879 1034 1034 ns


0129 0129 0152 0152 ns


0142 0142 0167 0167 ns


0201 0201 0237 0237 ns









Min Max Min Max











Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units











1505 2005 1771 2358 ns


2005 2358 ns



0131 ndash0105 0154 ndash0124 ns






5694 5694 6698 6698 ns




4204 4204 4946 4946 ns


1373 1373 1615 1615 ns


FPGA Fabric SRAM







Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















B_DOUT_EN)

2136 2635 2513 3100 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units














5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM






Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units





1828 2384 2150 2805 ns


ECC = PIPELINE

4262 4262 5013 5013 ns



4642 5254 5461 6181 ns



6929 7541 8151 8871 ns




ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns




ECC = PIPELINE









0350 0350 0350 0350 ns






1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns








1575 2083 1853 2451 ns








1591 2017 1872 2373 ns


1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




0028 ndash0281 0033 ndash0331 ns


1437 1945 1690 2288 ns


1158 1760 1363 2070 ns





1726 1726 2030 2030 ns


OUTPUT = BYPASS

4557 4557 5361 5361 ns


OUTPUT = BYPASS

4371 4371 5142 5142 ns



6767 6767 7960 7960 ns



6257 6257 7360 7360 ns



8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



3569 3569 4199 4199 ns



5899 5899 6940 6940 ns


1237 1237 1456 1456 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns



4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units







2032 2483 2390 2922 ns



1996 2608 2348 3068 ns







0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns
















1725 1725 2029 2029 ns


4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


6180 6180 7270 7270 ns


3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns


4642 5254 5461 6181 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


1996 2608 2348 3068 ns






0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM




Table 8-1 μPROM












5526 6501 ns




















JTAG






Units










7351 ms




















Units













1929 micros









VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N



LowHigh


TD EVR ST2R GR ST

User Control


User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T








mdash 4625 50 5375 MHz




(peak to peak)



Output jitter

(peak to peak)

with FPGA fabric

switching noise1





On-Chip Oscillator








10 mdash 400 MHz




10 200 MHz














ps








Ref Clock

IO Standard


Temperature (degC)



Unit



ps










ps



ps





ps


ps






Ref Clock

IO Standard



Unit



LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS












continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33


















high






mdash 143 mdash ns



mdash 145 mdash ns






33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA












SET FilterON

SET FilterOFF

SET FilterON

Units


0073 1007 0086 0956 ns


0456 0618 0536 0730 ns




1234 2105 1452 2247 ns


0228 0358 0268 0424 ns


-0456 -0456 -0536 -0536 ns


0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units






1234 2105 1452 2247 ns






SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units




1229 2100 1446 2241 ns


0205 0334 0241 0396 ns




0601 0601 0707 0707 ns


3171 3171 3731 3731 ns











2912 2912 3426 3426 ns


2040 2040 2400 2400 ns






Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns












































0238 12 V





























































to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125


360 80 107 360 80 107 100


06 ndash18


See tables





05 ndash24



VID geVICM


VID geVICM
















ndash1 400 500 800 ps


STD 600 800 1300 ps











Jitter)

















































Max(STD)

Units




1 mdash 100 90 MHz



1 mdash 66 58 MHz



1 mdash 75 66 MHz



1 mdash 66 58 MHz


















(1FSWCLK)

mdash mdash ns









(ndash1)Max(STD)

Units


















Temperature

forced on

package


using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517




25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC



Temperature

forced on

package


m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC


Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234




25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC


























Revision History








Revision History

















Revision History






















Revision History



























Revision History










Revision History































ISBN













Introduction

1 Device Status


Table of Contents








1131 Theta-JB

1132 Theta-JC

2 Power Consumption





41 Input Buffer



44 IO Speeds




462 33V LVCMOSLVTTL



463 25V LVCMOS



464 18V LVCMOS



465 15V LVCMOS



466 12 V LVCMOS



467 33V PCIPCIX
























481 LVDS




482 B-LVDS



483 M-LVDS



484 Mini-LVDS



485 RSDS



486 LVPECL




491 Input Register










51 LUT4





7 FPGA Fabric SRAM




9 JTAG

91 Live Probe











20 Revision History



Customer Support


Legal Notice

Trademarks












Legal Notice 134

Trademarks 135











ndash03 136 V



ndash03 363 V


ndash03 363 V


ndash03 132 V


ndash03 275 V


ndash03 363 V


ndash03 363 V


ndash03 375 V


ndash03 275 V


ndash03 285 V



ndash03 275 V

















114 12 126 V


315 33 345 V


315 33 345 V

SERDES_x_Lyz_VDDAIO


114 12 126 V



2375 25 2625 V


171 18 189 V


2375 25 2625 V


315 33 345 V


049 times

SERDES_VDDI

05 times

SERDES_VDDI

051 times

SERDES_VDDI

V






114 12 126 V


1425 15 1575 V


171 18 189 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V





Programming

Temperature

Operating

Temperature

Programming

Cycles

Verify Cyclesper

Program Cycle


Retention1

(BiasedUnbiased)

Min TJ = 0 degC

Max TJ = 85 degC


Max TJ = 125 degC

200 200 50 Krad 10 years

Notes














90 20

95 20

100 20

105 20

110 20

115 20

120 14

125 10

130 72

135 53

140 39

145 28

150 21

























ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where














CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW












FPGA Core VDD On

VPP On

VDDPLL 0V



VDDIx2 3 On

VREF0 VREF94 On













VDD 114 756

VDDI 2375 41

Power Consumption




VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2


Power Consumption





Core Voltage

VDD (V)


114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090






































HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps



















LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz







HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz



















Note




R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)

at VOH KΩ






25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191








15V LVCMOS 60 mV

12V LVCMOS 20 mV







































mdash 2k mdash Ω



mdash 5 mdash pF





2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16




tPY tPYS Units



MSIO None 1993 2345 2122 2497 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns



































mdash 2k mdash Ω



mdash 5 mdash pF






MSIO IOBank

MSIOD IOBank


VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)













tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns


2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns












































mdash 2k mdash Ω









tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns






































(with Fixed Code)


(mA)

IOL

(mA)










tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units


None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns








































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns






















mdash V


mdash V








mdash 5 mdash pF





tPY tPYS Units



MSIO None 2097 2467 2226 2619 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns




















HSTL18 Class I





45 mdash mdash mA






40 mdash mdash mA






54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA
















V



(for DDRIO IO Bank)


Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)




(for DDRIO IO Bank)



(ODT)


mdash Ω




mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω










50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns


















HSTL 15V Class I






80 mdash mdash mA




70 mdash mdash mA




80 mdash mdash mA































(for DDRIO IO Bank)


mdash Ω
















478 0606 0712 ns


478 0616 0725 ns

MSIO








MSIOD





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns










































V



(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)








mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω





















tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns










mdash 189 V















47 mdash mdash mA






63 mdash mdash mA









93 mdash mdash mA






134 mdash mdash mA












VDIFF

(AC)







0175


0175

V



(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)



Maximum datarate

(for MSIOD IOBank)






150Ω




150Ω

mdash 50 75

150

mdash Ω




mdash 5 mdash pF



mdash 50 mdash Ω



mdash 25 mdash Ω











50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns





















IOH atVOH



134 mdash mdash mA

IOL atVOL

















V









mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω








20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns


Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns















LPDDR Reduced Drive









LPDDR Full Drive2











VDIFF(AC)
















mdash 5 mdash pF


mdash 50 mdash Ω












50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns



tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns


Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns






































10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16





tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns


tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns























mdash 250 350 450 mV


mdash 1125 125 1375 V




005 125 22 V









(MSIO IO Bank)




(for MSIOD IOBank)







95 100 105 Ω


190 200 210 Ω
















100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




















mdash 250 350 450 mV


mdash 1125 125 1375 V



006 125 18 V


500 mdash 2400 mV














VID ge 500 mV















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns



























(MSIO IO Bank)






















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns



























(MSIO IO Bank)



















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns


















005 mdash 15 V


termination (Rt)

005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF







100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns


















mdash 05 mdash 15 V




005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF








100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD


Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

















90 100 150 Ω










100 1204 1416 ns













Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units






ndash0336 0019 ns


D E 0828 1745 0974 1941 ns


D E ndash0212 0067 ndash0250 0106 ns


C G 1013 1013 1191 1191 ns


C G 1050 1050 1236 1236 ns





C E 0948 0948 1115 1115 ns


C C 1041 1041 1225 1225 ns


E E 0320 0320 0377 0377 ns


E E 0333 0333 0391 0391 ns












(from to)





Unit


E G or E I 0375 0375 0441 0441 ns


A E or J E 0622 1540 0732 1700 ns




B E 0972 1890 1144 2111 ns





Nodes

(from to)





Unit


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0211 0069 ndash0248 0108 ns


(ADn = 1)

C G or C I 1250 1250 1471 1471 ns


(ADn = 0)

C G or CI 1129 1129 1329 1329 ns




C E 0918 0918 1079 1079 ns


C C 1034 1034 1216 1216 ns


E E 0322 0322 0379 0379 ns


E E 0334 0334 0393 0393 ns














(from to)





Units


B C 0200 0200 0235 0235 ns


B D 0197 0197 0232 0232 ns


A B 0652 1523 0767 1615 ns


A B ndash0077 0104 ndash0091 0148 ns


E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units




G B 0828 1745 0974 1941 ns


G B ndash0212 0067 ndash0250 0106 ns


(ADn = 1)

F C 1013 1013 1191 1191 ns


(ADn = 0)

F C 1050 1050 1236 1236 ns


(ADn=1)

F D 1003 1003 1180 1180 ns


(ADn=0)

F D 1044 1044 1228 1228 ns




F B 0948 0948 1115 1115 ns


F F 1041 1041 1225 1225 ns


B B 0334 0320 0392 0377 ns


B B 0333 0333 0391 0391 ns














(from to)





Units


E G 0375 0375 0441 0441 ns


F E 0560 1478 0659 1627 ns


A E 0622 1540 0732 1700 ns


F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units


A E ndash0147 0132 ndash0173 0182 ns


B E 0973 1890 1145 2112 ns


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0209 0071 ndash0246 0110 ns


(ADn = 1)

C G 1235 1235 1453 1453 ns


(ADn = 0)

C G 1118 1118 1315 1315 ns




C E 0948 0948 1115 1115 ns


C C 1034 1034 1216 1216 ns


E E 0335 0322 0394 0379 ns


E E 0334 0334 0393 0393 ns








Figure 5-1 LUT4





INV Y = A tPD 0061 0072 ns








OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns


















Units



0429 1300 0505 13 ns


ndash0005 0275 ndash0005 035 ns


1098 1968 1291 2096 ns




0872 1789 1025 1993 ns


ndash0144 0136 ndash0169 0187 ns









Units


1037 1037 1220 122 ns


1066 1066 1255 1255 ns




0879 0879 1034 1034 ns


0129 0129 0152 0152 ns


0142 0142 0167 0167 ns


0201 0201 0237 0237 ns









Min Max Min Max











Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units











1505 2005 1771 2358 ns


2005 2358 ns



0131 ndash0105 0154 ndash0124 ns






5694 5694 6698 6698 ns




4204 4204 4946 4946 ns


1373 1373 1615 1615 ns


FPGA Fabric SRAM







Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















B_DOUT_EN)

2136 2635 2513 3100 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units














5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM






Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units





1828 2384 2150 2805 ns


ECC = PIPELINE

4262 4262 5013 5013 ns



4642 5254 5461 6181 ns



6929 7541 8151 8871 ns




ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns




ECC = PIPELINE









0350 0350 0350 0350 ns






1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns








1575 2083 1853 2451 ns








1591 2017 1872 2373 ns


1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




0028 ndash0281 0033 ndash0331 ns


1437 1945 1690 2288 ns


1158 1760 1363 2070 ns





1726 1726 2030 2030 ns


OUTPUT = BYPASS

4557 4557 5361 5361 ns


OUTPUT = BYPASS

4371 4371 5142 5142 ns



6767 6767 7960 7960 ns



6257 6257 7360 7360 ns



8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



3569 3569 4199 4199 ns



5899 5899 6940 6940 ns


1237 1237 1456 1456 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns



4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units







2032 2483 2390 2922 ns



1996 2608 2348 3068 ns







0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns
















1725 1725 2029 2029 ns


4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


6180 6180 7270 7270 ns


3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns


4642 5254 5461 6181 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


1996 2608 2348 3068 ns






0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM




Table 8-1 μPROM












5526 6501 ns




















JTAG






Units










7351 ms




















Units













1929 micros









VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N



LowHigh


TD EVR ST2R GR ST

User Control


User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T








mdash 4625 50 5375 MHz




(peak to peak)



Output jitter

(peak to peak)

with FPGA fabric

switching noise1





On-Chip Oscillator








10 mdash 400 MHz




10 200 MHz














ps








Ref Clock

IO Standard


Temperature (degC)



Unit



ps










ps



ps





ps


ps






Ref Clock

IO Standard



Unit



LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS












continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33


















high






mdash 143 mdash ns



mdash 145 mdash ns






33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA












SET FilterON

SET FilterOFF

SET FilterON

Units


0073 1007 0086 0956 ns


0456 0618 0536 0730 ns




1234 2105 1452 2247 ns


0228 0358 0268 0424 ns


-0456 -0456 -0536 -0536 ns


0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units






1234 2105 1452 2247 ns






SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units




1229 2100 1446 2241 ns


0205 0334 0241 0396 ns




0601 0601 0707 0707 ns


3171 3171 3731 3731 ns











2912 2912 3426 3426 ns


2040 2040 2400 2400 ns






Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns












































0238 12 V





























































to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125


360 80 107 360 80 107 100


06 ndash18


See tables





05 ndash24



VID geVICM


VID geVICM
















ndash1 400 500 800 ps


STD 600 800 1300 ps











Jitter)

















































Max(STD)

Units




1 mdash 100 90 MHz



1 mdash 66 58 MHz



1 mdash 75 66 MHz



1 mdash 66 58 MHz


















(1FSWCLK)

mdash mdash ns









(ndash1)Max(STD)

Units


















Temperature

forced on

package


using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517




25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC



Temperature

forced on

package


m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC


Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234




25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC


























Revision History








Revision History

















Revision History






















Revision History



























Revision History










Revision History































ISBN













Introduction

1 Device Status


Table of Contents








1131 Theta-JB

1132 Theta-JC

2 Power Consumption





41 Input Buffer



44 IO Speeds




462 33V LVCMOSLVTTL



463 25V LVCMOS



464 18V LVCMOS



465 15V LVCMOS



466 12 V LVCMOS



467 33V PCIPCIX
























481 LVDS




482 B-LVDS



483 M-LVDS



484 Mini-LVDS



485 RSDS



486 LVPECL




491 Input Register










51 LUT4





7 FPGA Fabric SRAM




9 JTAG

91 Live Probe











20 Revision History



Customer Support


Legal Notice

Trademarks









ndash03 136 V



ndash03 363 V


ndash03 363 V


ndash03 132 V


ndash03 275 V


ndash03 363 V


ndash03 363 V


ndash03 375 V


ndash03 275 V


ndash03 285 V



ndash03 275 V

















114 12 126 V


315 33 345 V


315 33 345 V

SERDES_x_Lyz_VDDAIO


114 12 126 V



2375 25 2625 V


171 18 189 V


2375 25 2625 V


315 33 345 V


049 times

SERDES_VDDI

05 times

SERDES_VDDI

051 times

SERDES_VDDI

V






114 12 126 V


1425 15 1575 V


171 18 189 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V





Programming

Temperature

Operating

Temperature

Programming

Cycles

Verify Cyclesper

Program Cycle


Retention1

(BiasedUnbiased)

Min TJ = 0 degC

Max TJ = 85 degC


Max TJ = 125 degC

200 200 50 Krad 10 years

Notes














90 20

95 20

100 20

105 20

110 20

115 20

120 14

125 10

130 72

135 53

140 39

145 28

150 21

























ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where














CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW












FPGA Core VDD On

VPP On

VDDPLL 0V



VDDIx2 3 On

VREF0 VREF94 On













VDD 114 756

VDDI 2375 41

Power Consumption




VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2


Power Consumption





Core Voltage

VDD (V)


114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090






































HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps



















LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz







HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz



















Note




R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)

at VOH KΩ






25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191








15V LVCMOS 60 mV

12V LVCMOS 20 mV







































mdash 2k mdash Ω



mdash 5 mdash pF





2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16




tPY tPYS Units



MSIO None 1993 2345 2122 2497 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns



































mdash 2k mdash Ω



mdash 5 mdash pF






MSIO IOBank

MSIOD IOBank


VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)













tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns


2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns












































mdash 2k mdash Ω









tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns






































(with Fixed Code)


(mA)

IOL

(mA)










tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units


None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns








































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns






















mdash V


mdash V








mdash 5 mdash pF





tPY tPYS Units



MSIO None 2097 2467 2226 2619 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns




















HSTL18 Class I





45 mdash mdash mA






40 mdash mdash mA






54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA
















V



(for DDRIO IO Bank)


Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)




(for DDRIO IO Bank)



(ODT)


mdash Ω




mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω










50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns


















HSTL 15V Class I






80 mdash mdash mA




70 mdash mdash mA




80 mdash mdash mA































(for DDRIO IO Bank)


mdash Ω
















478 0606 0712 ns


478 0616 0725 ns

MSIO








MSIOD





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns










































V



(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)








mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω





















tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns










mdash 189 V















47 mdash mdash mA






63 mdash mdash mA









93 mdash mdash mA






134 mdash mdash mA












VDIFF

(AC)







0175


0175

V



(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)



Maximum datarate

(for MSIOD IOBank)






150Ω




150Ω

mdash 50 75

150

mdash Ω




mdash 5 mdash pF



mdash 50 mdash Ω



mdash 25 mdash Ω











50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns





















IOH atVOH



134 mdash mdash mA

IOL atVOL

















V









mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω








20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns


Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns















LPDDR Reduced Drive









LPDDR Full Drive2











VDIFF(AC)
















mdash 5 mdash pF


mdash 50 mdash Ω












50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns



tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns


Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns






































10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16





tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns


tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns























mdash 250 350 450 mV


mdash 1125 125 1375 V




005 125 22 V









(MSIO IO Bank)




(for MSIOD IOBank)







95 100 105 Ω


190 200 210 Ω
















100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




















mdash 250 350 450 mV


mdash 1125 125 1375 V



006 125 18 V


500 mdash 2400 mV














VID ge 500 mV















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns



























(MSIO IO Bank)






















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns



























(MSIO IO Bank)



















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns


















005 mdash 15 V


termination (Rt)

005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF







100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns


















mdash 05 mdash 15 V




005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF








100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD


Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

















90 100 150 Ω










100 1204 1416 ns













Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units






ndash0336 0019 ns


D E 0828 1745 0974 1941 ns


D E ndash0212 0067 ndash0250 0106 ns


C G 1013 1013 1191 1191 ns


C G 1050 1050 1236 1236 ns





C E 0948 0948 1115 1115 ns


C C 1041 1041 1225 1225 ns


E E 0320 0320 0377 0377 ns


E E 0333 0333 0391 0391 ns












(from to)





Unit


E G or E I 0375 0375 0441 0441 ns


A E or J E 0622 1540 0732 1700 ns




B E 0972 1890 1144 2111 ns





Nodes

(from to)





Unit


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0211 0069 ndash0248 0108 ns


(ADn = 1)

C G or C I 1250 1250 1471 1471 ns


(ADn = 0)

C G or CI 1129 1129 1329 1329 ns




C E 0918 0918 1079 1079 ns


C C 1034 1034 1216 1216 ns


E E 0322 0322 0379 0379 ns


E E 0334 0334 0393 0393 ns














(from to)





Units


B C 0200 0200 0235 0235 ns


B D 0197 0197 0232 0232 ns


A B 0652 1523 0767 1615 ns


A B ndash0077 0104 ndash0091 0148 ns


E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units




G B 0828 1745 0974 1941 ns


G B ndash0212 0067 ndash0250 0106 ns


(ADn = 1)

F C 1013 1013 1191 1191 ns


(ADn = 0)

F C 1050 1050 1236 1236 ns


(ADn=1)

F D 1003 1003 1180 1180 ns


(ADn=0)

F D 1044 1044 1228 1228 ns




F B 0948 0948 1115 1115 ns


F F 1041 1041 1225 1225 ns


B B 0334 0320 0392 0377 ns


B B 0333 0333 0391 0391 ns














(from to)





Units


E G 0375 0375 0441 0441 ns


F E 0560 1478 0659 1627 ns


A E 0622 1540 0732 1700 ns


F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units


A E ndash0147 0132 ndash0173 0182 ns


B E 0973 1890 1145 2112 ns


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0209 0071 ndash0246 0110 ns


(ADn = 1)

C G 1235 1235 1453 1453 ns


(ADn = 0)

C G 1118 1118 1315 1315 ns




C E 0948 0948 1115 1115 ns


C C 1034 1034 1216 1216 ns


E E 0335 0322 0394 0379 ns


E E 0334 0334 0393 0393 ns








Figure 5-1 LUT4





INV Y = A tPD 0061 0072 ns








OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns


















Units



0429 1300 0505 13 ns


ndash0005 0275 ndash0005 035 ns


1098 1968 1291 2096 ns




0872 1789 1025 1993 ns


ndash0144 0136 ndash0169 0187 ns









Units


1037 1037 1220 122 ns


1066 1066 1255 1255 ns




0879 0879 1034 1034 ns


0129 0129 0152 0152 ns


0142 0142 0167 0167 ns


0201 0201 0237 0237 ns









Min Max Min Max











Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units











1505 2005 1771 2358 ns


2005 2358 ns



0131 ndash0105 0154 ndash0124 ns






5694 5694 6698 6698 ns




4204 4204 4946 4946 ns


1373 1373 1615 1615 ns


FPGA Fabric SRAM







Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















B_DOUT_EN)

2136 2635 2513 3100 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units














5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM






Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units





1828 2384 2150 2805 ns


ECC = PIPELINE

4262 4262 5013 5013 ns



4642 5254 5461 6181 ns



6929 7541 8151 8871 ns




ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns




ECC = PIPELINE









0350 0350 0350 0350 ns






1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns








1575 2083 1853 2451 ns








1591 2017 1872 2373 ns


1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




0028 ndash0281 0033 ndash0331 ns


1437 1945 1690 2288 ns


1158 1760 1363 2070 ns





1726 1726 2030 2030 ns


OUTPUT = BYPASS

4557 4557 5361 5361 ns


OUTPUT = BYPASS

4371 4371 5142 5142 ns



6767 6767 7960 7960 ns



6257 6257 7360 7360 ns



8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



3569 3569 4199 4199 ns



5899 5899 6940 6940 ns


1237 1237 1456 1456 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns



4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units







2032 2483 2390 2922 ns



1996 2608 2348 3068 ns







0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns
















1725 1725 2029 2029 ns


4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


6180 6180 7270 7270 ns


3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns


4642 5254 5461 6181 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


1996 2608 2348 3068 ns






0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM




Table 8-1 μPROM












5526 6501 ns




















JTAG






Units










7351 ms




















Units













1929 micros









VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N



LowHigh


TD EVR ST2R GR ST

User Control


User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T








mdash 4625 50 5375 MHz




(peak to peak)



Output jitter

(peak to peak)

with FPGA fabric

switching noise1





On-Chip Oscillator








10 mdash 400 MHz




10 200 MHz














ps








Ref Clock

IO Standard


Temperature (degC)



Unit



ps










ps



ps





ps


ps






Ref Clock

IO Standard



Unit



LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS












continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33


















high






mdash 143 mdash ns



mdash 145 mdash ns






33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA












SET FilterON

SET FilterOFF

SET FilterON

Units


0073 1007 0086 0956 ns


0456 0618 0536 0730 ns




1234 2105 1452 2247 ns


0228 0358 0268 0424 ns


-0456 -0456 -0536 -0536 ns


0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units






1234 2105 1452 2247 ns






SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units




1229 2100 1446 2241 ns


0205 0334 0241 0396 ns




0601 0601 0707 0707 ns


3171 3171 3731 3731 ns











2912 2912 3426 3426 ns


2040 2040 2400 2400 ns






Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns












































0238 12 V





























































to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125


360 80 107 360 80 107 100


06 ndash18


See tables





05 ndash24



VID geVICM


VID geVICM
















ndash1 400 500 800 ps


STD 600 800 1300 ps











Jitter)

















































Max(STD)

Units




1 mdash 100 90 MHz



1 mdash 66 58 MHz



1 mdash 75 66 MHz



1 mdash 66 58 MHz


















(1FSWCLK)

mdash mdash ns









(ndash1)Max(STD)

Units


















Temperature

forced on

package


using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517




25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC



Temperature

forced on

package


m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC


Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234




25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC


























Revision History








Revision History

















Revision History






















Revision History



























Revision History










Revision History































ISBN













Introduction

1 Device Status


Table of Contents








1131 Theta-JB

1132 Theta-JC

2 Power Consumption





41 Input Buffer



44 IO Speeds




462 33V LVCMOSLVTTL



463 25V LVCMOS



464 18V LVCMOS



465 15V LVCMOS



466 12 V LVCMOS



467 33V PCIPCIX
























481 LVDS




482 B-LVDS



483 M-LVDS



484 Mini-LVDS



485 RSDS



486 LVPECL




491 Input Register










51 LUT4





7 FPGA Fabric SRAM




9 JTAG

91 Live Probe











20 Revision History



Customer Support


Legal Notice

Trademarks














114 12 126 V


315 33 345 V


315 33 345 V

SERDES_x_Lyz_VDDAIO


114 12 126 V



2375 25 2625 V


171 18 189 V


2375 25 2625 V


315 33 345 V


049 times

SERDES_VDDI

05 times

SERDES_VDDI

051 times

SERDES_VDDI

V






114 12 126 V


1425 15 1575 V


171 18 189 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V





Programming

Temperature

Operating

Temperature

Programming

Cycles

Verify Cyclesper

Program Cycle


Retention1

(BiasedUnbiased)

Min TJ = 0 degC

Max TJ = 85 degC


Max TJ = 125 degC

200 200 50 Krad 10 years

Notes














90 20

95 20

100 20

105 20

110 20

115 20

120 14

125 10

130 72

135 53

140 39

145 28

150 21

























ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where














CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW












FPGA Core VDD On

VPP On

VDDPLL 0V



VDDIx2 3 On

VREF0 VREF94 On













VDD 114 756

VDDI 2375 41

Power Consumption




VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2


Power Consumption





Core Voltage

VDD (V)


114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090






































HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps



















LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz







HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz



















Note




R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)

at VOH KΩ






25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191








15V LVCMOS 60 mV

12V LVCMOS 20 mV







































mdash 2k mdash Ω



mdash 5 mdash pF





2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16




tPY tPYS Units



MSIO None 1993 2345 2122 2497 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns



































mdash 2k mdash Ω



mdash 5 mdash pF






MSIO IOBank

MSIOD IOBank


VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)













tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns


2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns












































mdash 2k mdash Ω









tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns






































(with Fixed Code)


(mA)

IOL

(mA)










tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units


None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns








































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns






















mdash V


mdash V








mdash 5 mdash pF





tPY tPYS Units



MSIO None 2097 2467 2226 2619 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns




















HSTL18 Class I





45 mdash mdash mA






40 mdash mdash mA






54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA
















V



(for DDRIO IO Bank)


Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)




(for DDRIO IO Bank)



(ODT)


mdash Ω




mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω










50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns


















HSTL 15V Class I






80 mdash mdash mA




70 mdash mdash mA




80 mdash mdash mA































(for DDRIO IO Bank)


mdash Ω
















478 0606 0712 ns


478 0616 0725 ns

MSIO








MSIOD





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns










































V



(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)








mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω





















tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns










mdash 189 V















47 mdash mdash mA






63 mdash mdash mA









93 mdash mdash mA






134 mdash mdash mA












VDIFF

(AC)







0175


0175

V



(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)



Maximum datarate

(for MSIOD IOBank)






150Ω




150Ω

mdash 50 75

150

mdash Ω




mdash 5 mdash pF



mdash 50 mdash Ω



mdash 25 mdash Ω











50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns





















IOH atVOH



134 mdash mdash mA

IOL atVOL

















V









mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω








20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns


Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns















LPDDR Reduced Drive









LPDDR Full Drive2











VDIFF(AC)
















mdash 5 mdash pF


mdash 50 mdash Ω












50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns



tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns


Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns






































10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16





tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns


tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns























mdash 250 350 450 mV


mdash 1125 125 1375 V




005 125 22 V









(MSIO IO Bank)




(for MSIOD IOBank)







95 100 105 Ω


190 200 210 Ω
















100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




















mdash 250 350 450 mV


mdash 1125 125 1375 V



006 125 18 V


500 mdash 2400 mV














VID ge 500 mV















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns



























(MSIO IO Bank)






















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns



























(MSIO IO Bank)



















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns


















005 mdash 15 V


termination (Rt)

005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF







100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns


















mdash 05 mdash 15 V




005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF








100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD


Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

















90 100 150 Ω










100 1204 1416 ns













Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units






ndash0336 0019 ns


D E 0828 1745 0974 1941 ns


D E ndash0212 0067 ndash0250 0106 ns


C G 1013 1013 1191 1191 ns


C G 1050 1050 1236 1236 ns





C E 0948 0948 1115 1115 ns


C C 1041 1041 1225 1225 ns


E E 0320 0320 0377 0377 ns


E E 0333 0333 0391 0391 ns












(from to)





Unit


E G or E I 0375 0375 0441 0441 ns


A E or J E 0622 1540 0732 1700 ns




B E 0972 1890 1144 2111 ns





Nodes

(from to)





Unit


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0211 0069 ndash0248 0108 ns


(ADn = 1)

C G or C I 1250 1250 1471 1471 ns


(ADn = 0)

C G or CI 1129 1129 1329 1329 ns




C E 0918 0918 1079 1079 ns


C C 1034 1034 1216 1216 ns


E E 0322 0322 0379 0379 ns


E E 0334 0334 0393 0393 ns














(from to)





Units


B C 0200 0200 0235 0235 ns


B D 0197 0197 0232 0232 ns


A B 0652 1523 0767 1615 ns


A B ndash0077 0104 ndash0091 0148 ns


E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units




G B 0828 1745 0974 1941 ns


G B ndash0212 0067 ndash0250 0106 ns


(ADn = 1)

F C 1013 1013 1191 1191 ns


(ADn = 0)

F C 1050 1050 1236 1236 ns


(ADn=1)

F D 1003 1003 1180 1180 ns


(ADn=0)

F D 1044 1044 1228 1228 ns




F B 0948 0948 1115 1115 ns


F F 1041 1041 1225 1225 ns


B B 0334 0320 0392 0377 ns


B B 0333 0333 0391 0391 ns














(from to)





Units


E G 0375 0375 0441 0441 ns


F E 0560 1478 0659 1627 ns


A E 0622 1540 0732 1700 ns


F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units


A E ndash0147 0132 ndash0173 0182 ns


B E 0973 1890 1145 2112 ns


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0209 0071 ndash0246 0110 ns


(ADn = 1)

C G 1235 1235 1453 1453 ns


(ADn = 0)

C G 1118 1118 1315 1315 ns




C E 0948 0948 1115 1115 ns


C C 1034 1034 1216 1216 ns


E E 0335 0322 0394 0379 ns


E E 0334 0334 0393 0393 ns








Figure 5-1 LUT4





INV Y = A tPD 0061 0072 ns








OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns


















Units



0429 1300 0505 13 ns


ndash0005 0275 ndash0005 035 ns


1098 1968 1291 2096 ns




0872 1789 1025 1993 ns


ndash0144 0136 ndash0169 0187 ns









Units


1037 1037 1220 122 ns


1066 1066 1255 1255 ns




0879 0879 1034 1034 ns


0129 0129 0152 0152 ns


0142 0142 0167 0167 ns


0201 0201 0237 0237 ns









Min Max Min Max











Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units











1505 2005 1771 2358 ns


2005 2358 ns



0131 ndash0105 0154 ndash0124 ns






5694 5694 6698 6698 ns




4204 4204 4946 4946 ns


1373 1373 1615 1615 ns


FPGA Fabric SRAM







Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















B_DOUT_EN)

2136 2635 2513 3100 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units














5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM






Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units





1828 2384 2150 2805 ns


ECC = PIPELINE

4262 4262 5013 5013 ns



4642 5254 5461 6181 ns



6929 7541 8151 8871 ns




ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns




ECC = PIPELINE









0350 0350 0350 0350 ns






1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns








1575 2083 1853 2451 ns








1591 2017 1872 2373 ns


1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




0028 ndash0281 0033 ndash0331 ns


1437 1945 1690 2288 ns


1158 1760 1363 2070 ns





1726 1726 2030 2030 ns


OUTPUT = BYPASS

4557 4557 5361 5361 ns


OUTPUT = BYPASS

4371 4371 5142 5142 ns



6767 6767 7960 7960 ns



6257 6257 7360 7360 ns



8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



3569 3569 4199 4199 ns



5899 5899 6940 6940 ns


1237 1237 1456 1456 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns



4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units







2032 2483 2390 2922 ns



1996 2608 2348 3068 ns







0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns
















1725 1725 2029 2029 ns


4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


6180 6180 7270 7270 ns


3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns


4642 5254 5461 6181 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


1996 2608 2348 3068 ns






0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM




Table 8-1 μPROM












5526 6501 ns




















JTAG






Units










7351 ms




















Units













1929 micros









VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N



LowHigh


TD EVR ST2R GR ST

User Control


User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T








mdash 4625 50 5375 MHz




(peak to peak)



Output jitter

(peak to peak)

with FPGA fabric

switching noise1





On-Chip Oscillator








10 mdash 400 MHz




10 200 MHz














ps








Ref Clock

IO Standard


Temperature (degC)



Unit



ps










ps



ps





ps


ps






Ref Clock

IO Standard



Unit



LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS












continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33


















high






mdash 143 mdash ns



mdash 145 mdash ns






33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA












SET FilterON

SET FilterOFF

SET FilterON

Units


0073 1007 0086 0956 ns


0456 0618 0536 0730 ns




1234 2105 1452 2247 ns


0228 0358 0268 0424 ns


-0456 -0456 -0536 -0536 ns


0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units






1234 2105 1452 2247 ns






SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units




1229 2100 1446 2241 ns


0205 0334 0241 0396 ns




0601 0601 0707 0707 ns


3171 3171 3731 3731 ns











2912 2912 3426 3426 ns


2040 2040 2400 2400 ns






Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns












































0238 12 V





























































to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125


360 80 107 360 80 107 100


06 ndash18


See tables





05 ndash24



VID geVICM


VID geVICM
















ndash1 400 500 800 ps


STD 600 800 1300 ps











Jitter)

















































Max(STD)

Units




1 mdash 100 90 MHz



1 mdash 66 58 MHz



1 mdash 75 66 MHz



1 mdash 66 58 MHz


















(1FSWCLK)

mdash mdash ns









(ndash1)Max(STD)

Units


















Temperature

forced on

package


using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517




25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC



Temperature

forced on

package


m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC


Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234




25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC


























Revision History








Revision History

















Revision History






















Revision History



























Revision History










Revision History































ISBN













Introduction

1 Device Status


Table of Contents








1131 Theta-JB

1132 Theta-JC

2 Power Consumption





41 Input Buffer



44 IO Speeds




462 33V LVCMOSLVTTL



463 25V LVCMOS



464 18V LVCMOS



465 15V LVCMOS



466 12 V LVCMOS



467 33V PCIPCIX
























481 LVDS




482 B-LVDS



483 M-LVDS



484 Mini-LVDS



485 RSDS



486 LVPECL




491 Input Register










51 LUT4





7 FPGA Fabric SRAM




9 JTAG

91 Live Probe











20 Revision History



Customer Support


Legal Notice

Trademarks





114 12 126 V


1425 15 1575 V


171 18 189 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V


2375 25 2625 V


315 33 345 V





Programming

Temperature

Operating

Temperature

Programming

Cycles

Verify Cyclesper

Program Cycle


Retention1

(BiasedUnbiased)

Min TJ = 0 degC

Max TJ = 85 degC


Max TJ = 125 degC

200 200 50 Krad 10 years

Notes














90 20

95 20

100 20

105 20

110 20

115 20

120 14

125 10

130 72

135 53

140 39

145 28

150 21

























ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where














CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW












FPGA Core VDD On

VPP On

VDDPLL 0V



VDDIx2 3 On

VREF0 VREF94 On













VDD 114 756

VDDI 2375 41

Power Consumption




VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2


Power Consumption





Core Voltage

VDD (V)


114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090






































HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps



















LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz







HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz



















Note




R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)

at VOH KΩ






25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191








15V LVCMOS 60 mV

12V LVCMOS 20 mV







































mdash 2k mdash Ω



mdash 5 mdash pF





2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16




tPY tPYS Units



MSIO None 1993 2345 2122 2497 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns



































mdash 2k mdash Ω



mdash 5 mdash pF






MSIO IOBank

MSIOD IOBank


VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)













tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns


2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns












































mdash 2k mdash Ω









tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns






































(with Fixed Code)


(mA)

IOL

(mA)










tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units


None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns








































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns






















mdash V


mdash V








mdash 5 mdash pF





tPY tPYS Units



MSIO None 2097 2467 2226 2619 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns




















HSTL18 Class I





45 mdash mdash mA






40 mdash mdash mA






54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA
















V



(for DDRIO IO Bank)


Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)




(for DDRIO IO Bank)



(ODT)


mdash Ω




mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω










50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns


















HSTL 15V Class I






80 mdash mdash mA




70 mdash mdash mA




80 mdash mdash mA































(for DDRIO IO Bank)


mdash Ω
















478 0606 0712 ns


478 0616 0725 ns

MSIO








MSIOD





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns










































V



(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)








mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω





















tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns










mdash 189 V















47 mdash mdash mA






63 mdash mdash mA









93 mdash mdash mA






134 mdash mdash mA












VDIFF

(AC)







0175


0175

V



(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)



Maximum datarate

(for MSIOD IOBank)






150Ω




150Ω

mdash 50 75

150

mdash Ω




mdash 5 mdash pF



mdash 50 mdash Ω



mdash 25 mdash Ω











50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns





















IOH atVOH



134 mdash mdash mA

IOL atVOL

















V









mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω








20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns


Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns















LPDDR Reduced Drive









LPDDR Full Drive2











VDIFF(AC)
















mdash 5 mdash pF


mdash 50 mdash Ω












50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns



tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns


Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns






































10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16





tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns


tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns























mdash 250 350 450 mV


mdash 1125 125 1375 V




005 125 22 V









(MSIO IO Bank)




(for MSIOD IOBank)







95 100 105 Ω


190 200 210 Ω
















100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




















mdash 250 350 450 mV


mdash 1125 125 1375 V



006 125 18 V


500 mdash 2400 mV














VID ge 500 mV















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns



























(MSIO IO Bank)






















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns



























(MSIO IO Bank)



















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns


















005 mdash 15 V


termination (Rt)

005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF







100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns


















mdash 05 mdash 15 V




005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF








100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD


Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

















90 100 150 Ω










100 1204 1416 ns













Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units






ndash0336 0019 ns


D E 0828 1745 0974 1941 ns


D E ndash0212 0067 ndash0250 0106 ns


C G 1013 1013 1191 1191 ns


C G 1050 1050 1236 1236 ns





C E 0948 0948 1115 1115 ns


C C 1041 1041 1225 1225 ns


E E 0320 0320 0377 0377 ns


E E 0333 0333 0391 0391 ns












(from to)





Unit


E G or E I 0375 0375 0441 0441 ns


A E or J E 0622 1540 0732 1700 ns




B E 0972 1890 1144 2111 ns





Nodes

(from to)





Unit


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0211 0069 ndash0248 0108 ns


(ADn = 1)

C G or C I 1250 1250 1471 1471 ns


(ADn = 0)

C G or CI 1129 1129 1329 1329 ns




C E 0918 0918 1079 1079 ns


C C 1034 1034 1216 1216 ns


E E 0322 0322 0379 0379 ns


E E 0334 0334 0393 0393 ns














(from to)





Units


B C 0200 0200 0235 0235 ns


B D 0197 0197 0232 0232 ns


A B 0652 1523 0767 1615 ns


A B ndash0077 0104 ndash0091 0148 ns


E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units




G B 0828 1745 0974 1941 ns


G B ndash0212 0067 ndash0250 0106 ns


(ADn = 1)

F C 1013 1013 1191 1191 ns


(ADn = 0)

F C 1050 1050 1236 1236 ns


(ADn=1)

F D 1003 1003 1180 1180 ns


(ADn=0)

F D 1044 1044 1228 1228 ns




F B 0948 0948 1115 1115 ns


F F 1041 1041 1225 1225 ns


B B 0334 0320 0392 0377 ns


B B 0333 0333 0391 0391 ns














(from to)





Units


E G 0375 0375 0441 0441 ns


F E 0560 1478 0659 1627 ns


A E 0622 1540 0732 1700 ns


F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units


A E ndash0147 0132 ndash0173 0182 ns


B E 0973 1890 1145 2112 ns


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0209 0071 ndash0246 0110 ns


(ADn = 1)

C G 1235 1235 1453 1453 ns


(ADn = 0)

C G 1118 1118 1315 1315 ns




C E 0948 0948 1115 1115 ns


C C 1034 1034 1216 1216 ns


E E 0335 0322 0394 0379 ns


E E 0334 0334 0393 0393 ns








Figure 5-1 LUT4





INV Y = A tPD 0061 0072 ns








OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns


















Units



0429 1300 0505 13 ns


ndash0005 0275 ndash0005 035 ns


1098 1968 1291 2096 ns




0872 1789 1025 1993 ns


ndash0144 0136 ndash0169 0187 ns









Units


1037 1037 1220 122 ns


1066 1066 1255 1255 ns




0879 0879 1034 1034 ns


0129 0129 0152 0152 ns


0142 0142 0167 0167 ns


0201 0201 0237 0237 ns









Min Max Min Max











Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units











1505 2005 1771 2358 ns


2005 2358 ns



0131 ndash0105 0154 ndash0124 ns






5694 5694 6698 6698 ns




4204 4204 4946 4946 ns


1373 1373 1615 1615 ns


FPGA Fabric SRAM







Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















B_DOUT_EN)

2136 2635 2513 3100 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units














5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM






Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units





1828 2384 2150 2805 ns


ECC = PIPELINE

4262 4262 5013 5013 ns



4642 5254 5461 6181 ns



6929 7541 8151 8871 ns




ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns




ECC = PIPELINE









0350 0350 0350 0350 ns






1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns








1575 2083 1853 2451 ns








1591 2017 1872 2373 ns


1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




0028 ndash0281 0033 ndash0331 ns


1437 1945 1690 2288 ns


1158 1760 1363 2070 ns





1726 1726 2030 2030 ns


OUTPUT = BYPASS

4557 4557 5361 5361 ns


OUTPUT = BYPASS

4371 4371 5142 5142 ns



6767 6767 7960 7960 ns



6257 6257 7360 7360 ns



8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



3569 3569 4199 4199 ns



5899 5899 6940 6940 ns


1237 1237 1456 1456 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns



4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units







2032 2483 2390 2922 ns



1996 2608 2348 3068 ns







0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns
















1725 1725 2029 2029 ns


4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


6180 6180 7270 7270 ns


3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns


4642 5254 5461 6181 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


1996 2608 2348 3068 ns






0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM




Table 8-1 μPROM












5526 6501 ns




















JTAG






Units










7351 ms




















Units













1929 micros









VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N



LowHigh


TD EVR ST2R GR ST

User Control


User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T








mdash 4625 50 5375 MHz




(peak to peak)



Output jitter

(peak to peak)

with FPGA fabric

switching noise1





On-Chip Oscillator








10 mdash 400 MHz




10 200 MHz














ps








Ref Clock

IO Standard


Temperature (degC)



Unit



ps










ps



ps





ps


ps






Ref Clock

IO Standard



Unit



LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS












continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33


















high






mdash 143 mdash ns



mdash 145 mdash ns






33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA












SET FilterON

SET FilterOFF

SET FilterON

Units


0073 1007 0086 0956 ns


0456 0618 0536 0730 ns




1234 2105 1452 2247 ns


0228 0358 0268 0424 ns


-0456 -0456 -0536 -0536 ns


0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units






1234 2105 1452 2247 ns






SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units




1229 2100 1446 2241 ns


0205 0334 0241 0396 ns




0601 0601 0707 0707 ns


3171 3171 3731 3731 ns











2912 2912 3426 3426 ns


2040 2040 2400 2400 ns






Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns












































0238 12 V





























































to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125


360 80 107 360 80 107 100


06 ndash18


See tables





05 ndash24



VID geVICM


VID geVICM
















ndash1 400 500 800 ps


STD 600 800 1300 ps











Jitter)

















































Max(STD)

Units




1 mdash 100 90 MHz



1 mdash 66 58 MHz



1 mdash 75 66 MHz



1 mdash 66 58 MHz


















(1FSWCLK)

mdash mdash ns









(ndash1)Max(STD)

Units


















Temperature

forced on

package


using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517




25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC



Temperature

forced on

package


m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC


Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234




25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC


























Revision History








Revision History

















Revision History






















Revision History



























Revision History










Revision History































ISBN













Introduction

1 Device Status


Table of Contents








1131 Theta-JB

1132 Theta-JC

2 Power Consumption





41 Input Buffer



44 IO Speeds




462 33V LVCMOSLVTTL



463 25V LVCMOS



464 18V LVCMOS



465 15V LVCMOS



466 12 V LVCMOS



467 33V PCIPCIX
























481 LVDS




482 B-LVDS



483 M-LVDS



484 Mini-LVDS



485 RSDS



486 LVPECL




491 Input Register










51 LUT4





7 FPGA Fabric SRAM




9 JTAG

91 Live Probe











20 Revision History



Customer Support


Legal Notice

Trademarks











90 20

95 20

100 20

105 20

110 20

115 20

120 14

125 10

130 72

135 53

140 39

145 28

150 21

























ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where














CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW












FPGA Core VDD On

VPP On

VDDPLL 0V



VDDIx2 3 On

VREF0 VREF94 On













VDD 114 756

VDDI 2375 41

Power Consumption




VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2


Power Consumption





Core Voltage

VDD (V)


114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090






































HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps



















LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz







HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz



















Note




R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)

at VOH KΩ






25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191








15V LVCMOS 60 mV

12V LVCMOS 20 mV







































mdash 2k mdash Ω



mdash 5 mdash pF





2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16




tPY tPYS Units



MSIO None 1993 2345 2122 2497 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns



































mdash 2k mdash Ω



mdash 5 mdash pF






MSIO IOBank

MSIOD IOBank


VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)













tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns


2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns












































mdash 2k mdash Ω









tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns






































(with Fixed Code)


(mA)

IOL

(mA)










tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units


None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns








































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns






















mdash V


mdash V








mdash 5 mdash pF





tPY tPYS Units



MSIO None 2097 2467 2226 2619 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns




















HSTL18 Class I





45 mdash mdash mA






40 mdash mdash mA






54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA
















V



(for DDRIO IO Bank)


Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)




(for DDRIO IO Bank)



(ODT)


mdash Ω




mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω










50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns


















HSTL 15V Class I






80 mdash mdash mA




70 mdash mdash mA




80 mdash mdash mA































(for DDRIO IO Bank)


mdash Ω
















478 0606 0712 ns


478 0616 0725 ns

MSIO








MSIOD





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns










































V



(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)








mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω





















tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns










mdash 189 V















47 mdash mdash mA






63 mdash mdash mA









93 mdash mdash mA






134 mdash mdash mA












VDIFF

(AC)







0175


0175

V



(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)



Maximum datarate

(for MSIOD IOBank)






150Ω




150Ω

mdash 50 75

150

mdash Ω




mdash 5 mdash pF



mdash 50 mdash Ω



mdash 25 mdash Ω











50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns





















IOH atVOH



134 mdash mdash mA

IOL atVOL

















V









mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω








20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns


Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns















LPDDR Reduced Drive









LPDDR Full Drive2











VDIFF(AC)
















mdash 5 mdash pF


mdash 50 mdash Ω












50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns



tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns


Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns






































10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16





tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns


tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns























mdash 250 350 450 mV


mdash 1125 125 1375 V




005 125 22 V









(MSIO IO Bank)




(for MSIOD IOBank)







95 100 105 Ω


190 200 210 Ω
















100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




















mdash 250 350 450 mV


mdash 1125 125 1375 V



006 125 18 V


500 mdash 2400 mV














VID ge 500 mV















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns



























(MSIO IO Bank)






















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns



























(MSIO IO Bank)



















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns


















005 mdash 15 V


termination (Rt)

005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF







100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns


















mdash 05 mdash 15 V




005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF








100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD


Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

















90 100 150 Ω










100 1204 1416 ns













Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units






ndash0336 0019 ns


D E 0828 1745 0974 1941 ns


D E ndash0212 0067 ndash0250 0106 ns


C G 1013 1013 1191 1191 ns


C G 1050 1050 1236 1236 ns





C E 0948 0948 1115 1115 ns


C C 1041 1041 1225 1225 ns


E E 0320 0320 0377 0377 ns


E E 0333 0333 0391 0391 ns












(from to)





Unit


E G or E I 0375 0375 0441 0441 ns


A E or J E 0622 1540 0732 1700 ns




B E 0972 1890 1144 2111 ns





Nodes

(from to)





Unit


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0211 0069 ndash0248 0108 ns


(ADn = 1)

C G or C I 1250 1250 1471 1471 ns


(ADn = 0)

C G or CI 1129 1129 1329 1329 ns




C E 0918 0918 1079 1079 ns


C C 1034 1034 1216 1216 ns


E E 0322 0322 0379 0379 ns


E E 0334 0334 0393 0393 ns














(from to)





Units


B C 0200 0200 0235 0235 ns


B D 0197 0197 0232 0232 ns


A B 0652 1523 0767 1615 ns


A B ndash0077 0104 ndash0091 0148 ns


E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units




G B 0828 1745 0974 1941 ns


G B ndash0212 0067 ndash0250 0106 ns


(ADn = 1)

F C 1013 1013 1191 1191 ns


(ADn = 0)

F C 1050 1050 1236 1236 ns


(ADn=1)

F D 1003 1003 1180 1180 ns


(ADn=0)

F D 1044 1044 1228 1228 ns




F B 0948 0948 1115 1115 ns


F F 1041 1041 1225 1225 ns


B B 0334 0320 0392 0377 ns


B B 0333 0333 0391 0391 ns














(from to)





Units


E G 0375 0375 0441 0441 ns


F E 0560 1478 0659 1627 ns


A E 0622 1540 0732 1700 ns


F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units


A E ndash0147 0132 ndash0173 0182 ns


B E 0973 1890 1145 2112 ns


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0209 0071 ndash0246 0110 ns


(ADn = 1)

C G 1235 1235 1453 1453 ns


(ADn = 0)

C G 1118 1118 1315 1315 ns




C E 0948 0948 1115 1115 ns


C C 1034 1034 1216 1216 ns


E E 0335 0322 0394 0379 ns


E E 0334 0334 0393 0393 ns








Figure 5-1 LUT4





INV Y = A tPD 0061 0072 ns








OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns


















Units



0429 1300 0505 13 ns


ndash0005 0275 ndash0005 035 ns


1098 1968 1291 2096 ns




0872 1789 1025 1993 ns


ndash0144 0136 ndash0169 0187 ns









Units


1037 1037 1220 122 ns


1066 1066 1255 1255 ns




0879 0879 1034 1034 ns


0129 0129 0152 0152 ns


0142 0142 0167 0167 ns


0201 0201 0237 0237 ns









Min Max Min Max











Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units











1505 2005 1771 2358 ns


2005 2358 ns



0131 ndash0105 0154 ndash0124 ns






5694 5694 6698 6698 ns




4204 4204 4946 4946 ns


1373 1373 1615 1615 ns


FPGA Fabric SRAM







Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















B_DOUT_EN)

2136 2635 2513 3100 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units














5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM






Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units





1828 2384 2150 2805 ns


ECC = PIPELINE

4262 4262 5013 5013 ns



4642 5254 5461 6181 ns



6929 7541 8151 8871 ns




ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns




ECC = PIPELINE









0350 0350 0350 0350 ns






1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns








1575 2083 1853 2451 ns








1591 2017 1872 2373 ns


1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




0028 ndash0281 0033 ndash0331 ns


1437 1945 1690 2288 ns


1158 1760 1363 2070 ns





1726 1726 2030 2030 ns


OUTPUT = BYPASS

4557 4557 5361 5361 ns


OUTPUT = BYPASS

4371 4371 5142 5142 ns



6767 6767 7960 7960 ns



6257 6257 7360 7360 ns



8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



3569 3569 4199 4199 ns



5899 5899 6940 6940 ns


1237 1237 1456 1456 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns



4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units







2032 2483 2390 2922 ns



1996 2608 2348 3068 ns







0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns
















1725 1725 2029 2029 ns


4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


6180 6180 7270 7270 ns


3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns


4642 5254 5461 6181 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


1996 2608 2348 3068 ns






0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM




Table 8-1 μPROM












5526 6501 ns




















JTAG






Units










7351 ms




















Units













1929 micros









VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N



LowHigh


TD EVR ST2R GR ST

User Control


User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T








mdash 4625 50 5375 MHz




(peak to peak)



Output jitter

(peak to peak)

with FPGA fabric

switching noise1





On-Chip Oscillator








10 mdash 400 MHz




10 200 MHz














ps








Ref Clock

IO Standard


Temperature (degC)



Unit



ps










ps



ps





ps


ps






Ref Clock

IO Standard



Unit



LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS












continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33


















high






mdash 143 mdash ns



mdash 145 mdash ns






33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA












SET FilterON

SET FilterOFF

SET FilterON

Units


0073 1007 0086 0956 ns


0456 0618 0536 0730 ns




1234 2105 1452 2247 ns


0228 0358 0268 0424 ns


-0456 -0456 -0536 -0536 ns


0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units






1234 2105 1452 2247 ns






SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units




1229 2100 1446 2241 ns


0205 0334 0241 0396 ns




0601 0601 0707 0707 ns


3171 3171 3731 3731 ns











2912 2912 3426 3426 ns


2040 2040 2400 2400 ns






Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns












































0238 12 V





























































to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125


360 80 107 360 80 107 100


06 ndash18


See tables





05 ndash24



VID geVICM


VID geVICM
















ndash1 400 500 800 ps


STD 600 800 1300 ps











Jitter)

















































Max(STD)

Units




1 mdash 100 90 MHz



1 mdash 66 58 MHz



1 mdash 75 66 MHz



1 mdash 66 58 MHz


















(1FSWCLK)

mdash mdash ns









(ndash1)Max(STD)

Units


















Temperature

forced on

package


using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517




25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC



Temperature

forced on

package


m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC


Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234




25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC


























Revision History








Revision History

















Revision History






















Revision History



























Revision History










Revision History































ISBN













Introduction

1 Device Status


Table of Contents








1131 Theta-JB

1132 Theta-JC

2 Power Consumption





41 Input Buffer



44 IO Speeds




462 33V LVCMOSLVTTL



463 25V LVCMOS



464 18V LVCMOS



465 15V LVCMOS



466 12 V LVCMOS



467 33V PCIPCIX
























481 LVDS




482 B-LVDS



483 M-LVDS



484 Mini-LVDS



485 RSDS



486 LVPECL




491 Input Register










51 LUT4





7 FPGA Fabric SRAM




9 JTAG

91 Live Probe











20 Revision History



Customer Support


Legal Notice

Trademarks





















ΘJB = (TJndashTB)P

ΘJC = (TJndashTc)P

where














CCGA16571 2 4 775 250 033 degCW

LGA16571 3 4 777 022 033 degCW

CQFP3521 3 4 785 026 312 degCW

FCGFC16571 2 4 752 131 0075 degCW












FPGA Core VDD On

VPP On

VDDPLL 0V



VDDIx2 3 On

VREF0 VREF94 On













VDD 114 756

VDDI 2375 41

Power Consumption




VDDPLL 315 1

VPP 315 6

SerDes VDDAIO 114 5

SerDes VDDI 2375 2


Power Consumption





Core Voltage

VDD (V)


114 083 084 089 091 093 097 097 100

12 079 080 084 086 088 091 092 095

126 075 076 080 082 084 087 088 090






































HSTL 18V 432 432 500 Mbps

SSTL 25V 575 700 800 Mbps

SSTL 18V 432 430 800 Mbps



















LVCMOS 25V 205 210 350 MHz

LVCMOS 18V 1475 160 350 MHz

LVCMOS 15V 100 100 200 MHz







HSTL 18V 216 216 250 MHz

SSTL 25V 2875 350 400 MHz

SSTL 18V 216 215 400 MHz



















Note




R(WEAK PULL-UP)

at VOH KΩ


R(WEAK PULL-UP)

at VOH KΩ






25V 998 178 10 18 10 176 101 184 96 166 95 164

18V 111 191 112 195 104 191 104 204 97 173 97 171

15V 10 202 999 211 107 204 108 222 99 18 98 176

12V 103 227 103 246 113 232 115 267 103 196 10 191








15V LVCMOS 60 mV

12V LVCMOS 20 mV







































mdash 2k mdash Ω



mdash 5 mdash pF





2 mA 24 04 2 2

4 mA 24 04 4 4

8 mA 24 04 8 8

12 mA 24 04 12 12

16 mA 24 04 16 16




tPY tPYS Units



MSIO None 1993 2345 2122 2497 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

1

tLZ

Speed

Grade

STD

Units

2 mA 4324 5086 4456 5242 3633 4274 3157 3714 2872 3379 ns

4 mA 3199 3763 3264 3840 2904 3417 3255 3828 2895 3405 ns

8 mA 2653 3120 2682 3156 2548 2998 3408 4008 2975 3499 ns

12 mA 2505 2946 2491 2931 2438 2868 3510 4129 2999 3528 ns

16 mA 2461 2894 2399 2823 2388 2809 3525 4147 3107 3655 ns



































mdash 2k mdash Ω



mdash 5 mdash pF






MSIO IOBank

MSIOD IOBank


VOH Min(V)

VOL Max(V)

IOH(mA)

IOL (mA)













tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units

DDRIO None 0877 1032 0877 1032 ns

MSIO None 1951 2296 2000 2353 ns

MSIOD None 1721 2025 1785 2100 ns


Output

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 3574 4205 3521 4141 3394 3992 3279 3857 3129 3680 ns

4 mA 3052 3590 2958 3479 2929 3446 3367 3961 3140 3693 ns

6 mA 2894 3405 2779 3269 2781 3271 3483 4098 3260 3835 ns

8 mA 2853 3357 2729 3210 2739 3221 3531 4154 3297 3879 ns

12 mA 2747 3232 2615 3076 2631 3094 3535 4158 3292 3872 ns

16 mA 2692 3167 2545 2993 2569 3021 3611 4248 3350 3941 ns




continuedOutput

Drive

Selection

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


2 mA 4752 5590 4867 5726 4582 5391 3600 4235 3253 3827 ns

4 mA 3232 3802 3257 3832 3217 3786 3704 4358 3338 3927 ns

6 mA 3050 3588 3060 3600 3054 3593 3807 4479 3361 3954 ns

8 mA 2944 3463 2945 3465 2961 3483 3835 4512 3370 3965 ns

12 mA 2897 3407 2815 3312 2854 3358 3886 4572 3385 3982 ns

16 mA 2884 3392 2776 3266 2824 3322 3912 4602 3427 4031 ns


2 mA 2613 3074 3356 3949 3295 3876 2754 3239 2513 2956 ns

4 mA 2129 2504 2772 3261 2776 3266 2751 3236 2515 2959 ns

6 mA 1831 2153 2409 2834 2461 2896 2778 3268 2535 2982 ns

8 mA 1789 2104 2262 2661 2330 2741 2817 3313 2557 3008 ns

10 mA 1807 2125 2246 2642 2317 2727 2838 3338 2563 3015 ns












































mdash 2k mdash Ω









tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns

MSIO None 2261 2660 2253 2650 ns

MSIOD None 1966 2314 1961 2308 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns


2 mA Default 4936 5808 5003 5885 4975 5852 4761 5601 4308 5068 ns

4 mA Default 4457 5244 4467 5254 4472 5261 4803 5650 4351 5118 ns

6 mA Default 4219 4964 4201 4941 4230 4975 4878 5737 4379 5151 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

8 mA Default 4049 4764 3942 4637 3995 4699 4897 5760 4374 5145 ns

10 mA Default 4030 4742 3869 4550 3932 4625 4946 5818 4391 5165 ns

12 mA Default 4017 4727 3817 4489 3888 4573 4964 5839 4367 5137 ns


2 mA Default 3287 3867 4112 4837 4358 5127 3301 3884 3007 3538 ns

4 mA Default 2407 2831 3218 3785 3421 4024 3344 3934 3032 3567 ns

6 mA Default 2245 2641 2936 3454 3128 3679 3385 3982 3054 3593 ns

8 mA Default 2227 2620 2806 3300 2999 3527 3384 3981 3056 3595 ns






































(with Fixed Code)


(mA)

IOL

(mA)










tPY

Speed Grade ndash1

tPY

Speed GradeSTD

tPYS

Speed Grade ndash1

tPYS

Speed GradeSTD

Units


None 1155 1359 1155 1359 ns

MSIO None 2523 2968 2500 2941 ns

MSIOD None 2130 2505 2117 2490 ns





Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 4823 5673 4774 5617 4851 5707 4357 5125 4086 4808 ns

Med 4283 5040 4274 5028 4285 5042 3672 4320 3450 4058 ns

Fast 4027 4738 4016 4725 3981 4683 3208 3774 3076 3618 ns

4 mA Slow 4180 4917 4101 4825 4185 4924 4533 5333 4212 4955 ns

Med 3693 4345 3654 4299 3672 4320 3764 4428 3476 4090 ns

Fast 3453 4063 3415 4018 3390 3989 3253 3828 3094 3640 ns

6 mA Slow 3980 4682 3887 4573 3977 4679 4669 5493 4363 5133 ns

Med 3505 4124 3457 4067 3483 4098 3831 4508 3554 4182 ns

Fast 3267 3844 3222 3791 3207 3773 3285 3864 3135 3688 ns

8 mA Slow 3813 4486 3734 4394 3806 4478 4675 5500 4355 5123 ns

Med 3392 3990 3341 3931 3340 3929 3828 4504 3546 4172 ns

Fast 3171 3731 3124 3675 3078 3621 3293 3875 3140 3694 ns

10 mA Slow 3755 4417 3667 4315 3743 4403 4799 5646 4421 5202 ns

Med 3338 3928 3282 3862 3289 3869 3901 4590 3597 4232 ns

Fast 3119 3669 3067 3609 3031 3566 3326 3913 3170 3730 ns

12 mA Slow 3698 4350 3612 4250 3685 4336 4862 5720 4445 5229 ns

Med 3297 3880 3238 3809 3245 3817 3921 4613 3595 4230 ns

Fast 3082 3627 3028 3563 2994 3523 3316 3902 3186 3748 ns


2 mA Default 5870 6905 5836 6867 5797 6820 6009 7068 5494 6463 ns

4 mA Default 5356 6301 5268 6198 5291 6225 6091 7165 5543 6521 ns

6 mA Default 5287 6220 5029 5917 5078 5974 6134 7215 5562 6542 ns

8 mA Default 5270 6200 4958 5833 5021 5907 6175 7264 5559 6539 ns


2 mA Default 3262 3837 4134 4864 4495 5289 3920 4612 3567 4197 ns

4 mA Default 2771 3259 3578 4209 3861 4542 4011 4718 3622 4261 ns

6 mA Default 2799 3292 3394 3993 3673 4321 4029 4740 3641 4283 ns








































(with Fixed Code)


(mA)

IOL

(mA)







tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1347 1585 1347 1585 ns

MSIO None 3228 3797 3193 3756 ns

MSIOD None 2555 3007 2531 2978 ns


Output

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Slow 5841 6871 5837 6868 5832 6862 5628 6621 5248 6174 ns

Medium 5105 6006 5094 5993 5066 5960 4752 5590 4431 5212 ns

Fast 4710 5540 4695 5524 4641 5461 4137 4867 3938 4633 ns

4 mA Slow 5241 6165 5205 6124 5264 6193 5957 7008 5414 6369 ns

Medium 4598 5409 4565 5371 4536 5337 4928 5797 4491 5283 ns

Fast 4247 4996 4211 4955 4121 4848 4200 4941 3977 4679 ns

6 mA Slow 5065 5959 5029 5917 5063 5957 6080 7153 5604 6593 ns

Medium 4450 5235 4411 5190 4379 5152 4980 5858 4577 5385 ns

Fast 4106 4830 4063 4780 3982 4685 4235 4982 4018 4727 ns


2 mA Default 8666 10194 8512 10013 8403 9886 8824 10380 8132 9567 ns

4 mA Default 8182 9625 7642 8990 7670 9023 8954 10534 8173 9615 ns




continuedOutput

Drive

Selection

Slew

Control

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit


2 mA Default 3996 4701 5094 5992 5644 6639 5408 6362 4884 5745 ns

4 mA Default 4029 4739 4757 5596 5255 6182 5510 6482 4937 5808 ns






















mdash V


mdash V








mdash 5 mdash pF





tPY tPYS Units



MSIO None 2097 2467 2226 2619 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2446 2878 2456 2889 2395 2817 3387 3985 3040 3576 ns




















HSTL18 Class I





45 mdash mdash mA






40 mdash mdash mA






54 mdash mdash mA




HSTL18 Class II





100 mdash mdash mA
















V



(for DDRIO IO Bank)


Maximum Data Rate

(for MSIO IO Bank)


Maximum Data Rate

(for MSIOD IO Bank)




(for DDRIO IO Bank)



(ODT)


mdash Ω




mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω










50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

HSTL18 Class I

For DDRIO IO Bank

Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns

For MSIO IO Bank

Single

ended

3787 4454 3428 4032 3534 4157 4378 5150 4051 4765 ns

Differential 4022 4731 3682 4332 3677 4326 4047 4761 4390 5165 ns

For MSIOD IO Bank

Single

ended

2045 2406 2173 2556 2331 2742 3134 3687 2894 3405 ns

Differential 2257 2655 2666 3136 2666 3137 2888 3398 3141 3695 ns

HSTL18 Class II

For DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2901 3413 3840 4517 3913 4603 ns


















HSTL 15V Class I






80 mdash mdash mA




70 mdash mdash mA




80 mdash mdash mA































(for DDRIO IO Bank)


mdash Ω
















478 0606 0712 ns


478 0616 0725 ns

MSIO








MSIOD





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

HSTL15 Class I

For DDRIO IO Bank

Single

Ended

3619 4257 3304 3888 3338 3927 4315 5077 4513 5310 ns

Differential 3612 4249 3567 4197 3550 4176 4306 5066 4509 5304 ns

For MSIO IO Bank

Single

Ended

4888 5751 4442 5226 4554 5358 5577 6560 5166 6077 ns

Differential 5108 6009 4743 5580 4737 5572 5593 6580 5175 6088 ns

For MSIOD IO Bank

Single

Ended

2481 2919 2631 3095 2840 3341 3769 4434 3463 4074 ns

Differential 2670 3141 3223 3793 3223 3792 3778 4445 3470 4082 ns

HSTL15 Class II

For DDRIO IO Bank

Single

Ended

3525 4147 3261 3837 3300 3882 4536 5337 4602 5415 ns

Differential 3513 4133 3471 4083 3454 4064 4529 5328 4598 5409 ns










































V



(for DDRIO IOBank)



Maximum data rate

(for MSIO IO Bank)


Maximum data rate

(for MSIOD IOBank)








mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω





















tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

SSTL2 Class I

DDRIO IO Bank

Single

Ended

2736 3219 2376 2795 2393 2815 3179 3740 3258 3832 ns

Differential 2672 3143 2551 3001 2565 3019 3173 3732 3247 3819 ns

MSIO IO Bank

Single

Ended

2731 3214 2532 2979 2616 3077 3276 3853 3037 3573 ns

Differential 2977 3503 2802 3296 2799 3293 3288 3868 3044 3581 ns

MSIOD IO Bank

Single

Ended

1523 1792 1846 2171 1940 2282 2559 3011 2391 2813 ns

Differential 1745 2053 2262 2662 2263 2662 2572 3026 2396 2819 ns

SSTL2 Class II

DDRIO IO Bank

Single

Ended

2625 3088 2325 2735 2328 2738 3183 3745 3256 3831 ns

Differential 2558 3010 2432 2861 2409 2834 3264 3839 3220 3787 ns

MSIO IO Bank




continuedtDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

Single

Ended

2684 3159 2495 2935 2590 3046 3273 3850 3035 3571 ns

Differential 2927 3444 2673 3143 2671 3141 3030 3566 3280 3860 ns

MSIOD IO Bank

Single

Ended

1592 1873 1764 2075 1872 2202 2561 3014 2391 2813 ns

Differential 1805 2123 2102 2473 2102 2473 2386 2806 2570 3023 ns










mdash 189 V















47 mdash mdash mA






63 mdash mdash mA









93 mdash mdash mA






134 mdash mdash mA












VDIFF

(AC)







0175


0175

V



(for DDRIO IOBank)

AC loading perJEDEC

specification


Maximum datarate

(for MSIO IOBank)



Maximum datarate

(for MSIOD IOBank)






150Ω




150Ω

mdash 50 75

150

mdash Ω




mdash 5 mdash pF



mdash 50 mdash Ω



mdash 25 mdash Ω











50 0595 0701 ns

75 0595 0701 ns

150 0595 0701 ns


50 0616 0725 ns

75 0616 0725 ns

150 0616 0725 ns



50 1526 1796 ns

75 1526 1796 ns

150 1526 1796 ns


50 1436 1689 ns

75 1436 1689 ns

150 1436 1689 ns



50 1490 1753 ns

75 1490 1753 ns

150 1490 1753 ns


50 1421 1671 ns

75 1421 1671 ns

150 1421 1671 ns






tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Unit

SSTL18 Class I

DDRIO IO Bank

Single

ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 2979 3505 3786 4454 3837 4514 ns

MSIO IO Bank

Single

ended

3729 4386 3488 4102 3569 4198 4374 5145 4049 4763 ns

Differential 3959 4658 3799 4470 3795 4465 4386 5160 4054 4770 ns

MSIOD IO Bank

Single

ended

1853 2180 2206 2595 2362 2778 3125 3676 2887 3397 ns

Differential 2070 2436 2689 3163 2690 3165 3136 3689 2895 3405 ns

SSTL18 Class II

DDRIO IO Bank

Single

ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns

MSIO IO Bank

Single

ended

3675 4322 3433 4038 3538 4162 4373 5144 4047 4760 ns

Differential 3898 4586 3647 4290 3642 4284 4042 4755 4384 5157 ns

MSIOD IO Bank

Single

ended

1949 2293 2192 2578 2354 2769 3130 3682 2893 3404 ns

Differential 2160 2542 2617 3079 2616 3078 2887 3396 3138 3692 ns





















IOH atVOH



134 mdash mdash mA

IOL atVOL

















V









mdash 5 mdash pF


mdash 50 mdash Ω


mdash 25 mdash Ω








20 0606 0713 ns

30 0606 0713 ns

40 0606 0713 ns

60 0606 0713 ns

120 0606 0713 ns


20 0616 0725 ns

30 0616 0725 ns

40 0616 0725 ns

60 0616 0725 ns

120 0616 0725 ns





tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3380 3976 3079 3622 3129 3681 4186 4924 4270 5024 ns

Differential 3327 3913 3369 3963 3353 3945 4194 4933 4295 5052 ns


Single

Ended

3269 3846 3085 3629 3140 3693 4185 4924 4270 5024 ns

Differential 3222 3790 3305 3888 3290 3871 4189 4927 4279 5033 ns















LPDDR Reduced Drive









LPDDR Full Drive2











VDIFF(AC)
















mdash 5 mdash pF


mdash 50 mdash Ω












50 0596 0700 ns

75 0596 0700 ns

150 0596 0700 ns


50 0617 0726 ns

75 0617 0726 ns

150 0617 0726 ns



tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units


Single

Ended

3100 3646 2776 3266 2808 3303 3790 4460 3846 4525 ns

Differential 3089 3634 2998 3527 3003 3533 3850 4530 3782 4450 ns


Single

Ended

3025 3558 2745 3229 2778 3269 3844 4523 3927 4620 ns

Differential 3010 3541 2919 3434 2925 3440 3926 4619 3830 4507 ns






































10 mA VDDI ndash 045 045 10 10

12 mA VDDI ndash 045 045 12 12

16 mA VDDI ndash 045 045 16 16





tPY

SpeedGrade ndash1

tPY

SpeedGrade STD

tPYS

SpeedGrade ndash1

tPYS

SpeedGrade STD

Units


None 1028 1209 1028 1209 ns


tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

2 mA Slow 4088 4809 4054 4769 4101 4824 3815 4489 3609 4246 ns

Med 3710 4364 3685 4336 3670 4317 3203 3768 3009 3541 ns

4 mA Slow 3757 4419 3692 4343 3752 4414 3952 4649 3751 4413 ns

Med 3373 3968 3331 3918 3328 3915 3288 3869 3072 3614 ns

6 mA Slow 3438 4045 3357 3949 3424 4028 4026 4737 3783 4450 ns

Med 3086 3630 3030 3564 3035 3570 3319 3906 3080 3624 ns

8 mA Slow 3362 3955 3272 3849 3345 3935 4073 4792 3799 4470 ns

Med 3015 3546 2955 3476 2966 3490 3338 3928 3096 3643 ns

10 mA Slow 3228 3797 3146 3701 3205 3771 4077 4797 3788 4456 ns

Med 2917 3431 2855 3359 2848 3350 3331 3919 3080 3624 ns

12 mA Slow 3179 3739 3087 3631 3150 3706 4155 4888 3881 4566 ns

Med 2870 3376 2802 3296 2802 3296 3383 3980 3130 3683 ns




continued

tDP tZL tZH tHZ tLZ

Output

Drive

Selection

Slew

Control

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Speed

Grade

ndash1

Speed

Grade

STD

Unit

16 mA Slow 3126 3677 3025 3559 3087 3632 4237 4986 3948 4645 ns

Med 2826 3324 2750 3235 2752 3238 3415 4018 3158 3716 ns























mdash 250 350 450 mV


mdash 1125 125 1375 V




005 125 22 V









(MSIO IO Bank)




(for MSIOD IOBank)







95 100 105 Ω


190 200 210 Ω
















100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3151 3706 2765 3253 2760 3248 2990 3517 3211 3778 ns

MSIOD

No pre-emphasis

1919 2257 2179 2563 2154 2534 2538 2985 2388 2809 ns

Min pre-emphasis

1843 2167 2178 2563 2154 2534 2375 2793 2535 2982 ns

Med pre-emphasis

1807 2125 2179 2563 2154 2534 2538 2985 2388 2809 ns




















mdash 250 350 450 mV


mdash 1125 125 1375 V



006 125 18 V


500 mdash 2400 mV














VID ge 500 mV















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 2816 3313 2330 2741 2329 2741 2604 3063 2749 3234 ns



























(MSIO IO Bank)






















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns



























(MSIO IO Bank)



















IOBank

tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3193 3756 2756 3243 2749 3234 3008 3539 3240 3811 ns


















005 mdash 15 V


termination (Rt)

005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF







100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Grade

ndash1

tDP

Speed

Grade

STD

tZL

Speed

Grade

ndash1

tZL

Speed

Grade

STD

tZH

Speed

Grade

ndash1

tZH

Speed

Grade

STD

tHZ

Speed

Grade

ndash1

tHZ

Speed

Grade

STD

tLZ

Speed

Grade

ndash1

tLZ

Speed

Grade

STD

Units

MSIO 3177 3737 2753 3238 2749 3235 2998 3526 3219 3786 ns

MSIOD 1910 2247 2079 2446 2067 2432 2375 2794 2537 2984 ns


















mdash 05 mdash 15 V




005 mdash 22 V





















95 100 105 Ω


190 200 210 Ω





mdash 5 mdash pF








100 1244 1463 ns


100 1232 1448 ns


IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

MSIO 3175 3736 2806 3302 2800 3294 2983 3509 3205 3770 ns

MSIOD


Minimum

pre-emphasis

1919 2257 2178 2563 2154 2534 2375 2793 2535 2982 ns




continued

IO Bank tDP

Speed

Gradendash1

tDP

Speed

Grade

STD

tZL

Speed

Gradendash1

tZL

Speed

Grade

STD

tZH

Speed

Gradendash1

tZH

Speed

Grade

STD

tHZ

Speed

Gradendash1

tHZ

Speed

Grade

STD

tLZ

Speed

Gradendash1

tLZ

Speed

Grade

STD

Units

Medium

pre-emphasis

1843 2167 2179 2563 2154 2534 2538 2985 2388 2809 ns

Maximum

pre-emphasis

1807 2125 2178 2563 2154 2534 2375 2793 2535 2982 ns

















90 100 150 Ω










100 1204 1416 ns













Nodes

(from to)

Speed

Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units






ndash0336 0019 ns


D E 0828 1745 0974 1941 ns


D E ndash0212 0067 ndash0250 0106 ns


C G 1013 1013 1191 1191 ns


C G 1050 1050 1236 1236 ns





C E 0948 0948 1115 1115 ns


C C 1041 1041 1225 1225 ns


E E 0320 0320 0377 0377 ns


E E 0333 0333 0391 0391 ns












(from to)





Unit


E G or E I 0375 0375 0441 0441 ns


A E or J E 0622 1540 0732 1700 ns




B E 0972 1890 1144 2111 ns





Nodes

(from to)





Unit


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0211 0069 ndash0248 0108 ns


(ADn = 1)

C G or C I 1250 1250 1471 1471 ns


(ADn = 0)

C G or CI 1129 1129 1329 1329 ns




C E 0918 0918 1079 1079 ns


C C 1034 1034 1216 1216 ns


E E 0322 0322 0379 0379 ns


E E 0334 0334 0393 0393 ns














(from to)





Units


B C 0200 0200 0235 0235 ns


B D 0197 0197 0232 0232 ns


A B 0652 1523 0767 1615 ns


A B ndash0077 0104 ndash0091 0148 ns


E B 0968 1885 1138 2106 ns





Nodes

(from to)





Units




G B 0828 1745 0974 1941 ns


G B ndash0212 0067 ndash0250 0106 ns


(ADn = 1)

F C 1013 1013 1191 1191 ns


(ADn = 0)

F C 1050 1050 1236 1236 ns


(ADn=1)

F D 1003 1003 1180 1180 ns


(ADn=0)

F D 1044 1044 1228 1228 ns




F B 0948 0948 1115 1115 ns


F F 1041 1041 1225 1225 ns


B B 0334 0320 0392 0377 ns


B B 0333 0333 0391 0391 ns














(from to)





Units


E G 0375 0375 0441 0441 ns


F E 0560 1478 0659 1627 ns


A E 0622 1540 0732 1700 ns


F E ndash0135 0145 ndash0159 0197 ns





Nodes

(from to)





Units


A E ndash0147 0132 ndash0173 0182 ns


B E 0973 1890 1145 2112 ns


B E ndash0280 0000 ndash0329 0026 ns


D E 0833 1750 0980 1947 ns


D E ndash0209 0071 ndash0246 0110 ns


(ADn = 1)

C G 1235 1235 1453 1453 ns


(ADn = 0)

C G 1118 1118 1315 1315 ns




C E 0948 0948 1115 1115 ns


C C 1034 1034 1216 1216 ns


E E 0335 0322 0394 0379 ns


E E 0334 0334 0393 0393 ns








Figure 5-1 LUT4





INV Y = A tPD 0061 0072 ns








OR2 Y = A + B tPD 0156 0183 ns

NOR2 Y = (A + B) tPD 0131 0154 ns


















Units



0429 1300 0505 13 ns


ndash0005 0275 ndash0005 035 ns


1098 1968 1291 2096 ns




0872 1789 1025 1993 ns


ndash0144 0136 ndash0169 0187 ns









Units


1037 1037 1220 122 ns


1066 1066 1255 1255 ns




0879 0879 1034 1034 ns


0129 0129 0152 0152 ns


0142 0142 0167 0167 ns


0201 0201 0237 0237 ns









Min Max Min Max











Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















2128 2628 2504 3091 ns

FPGA Fabric SRAM



continued


Gradendash1

SET

Filter

OFF

Speed

Gradendash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units











1505 2005 1771 2358 ns


2005 2358 ns



0131 ndash0105 0154 ndash0124 ns






5694 5694 6698 6698 ns




4204 4204 4946 4946 ns


1373 1373 1615 1615 ns


FPGA Fabric SRAM







Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



















B_DOUT_EN)

2136 2635 2513 3100 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units














5360 5360 6306 6306 ns




3916 3916 4607 4607 ns


1373 1373 1615 1615 ns



FPGA Fabric SRAM






Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units





1828 2384 2150 2805 ns


ECC = PIPELINE

4262 4262 5013 5013 ns



4642 5254 5461 6181 ns



6929 7541 8151 8871 ns




ECC = PIPELINE








FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


ECC=PIPELINE

1614 1614 1899 1899 ns



1996 2608 2348 3068 ns



3493 4104 4109 4828 ns




ECC = PIPELINE









0350 0350 0350 0350 ns






1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns








1575 2083 1853 2451 ns








1591 2017 1872 2373 ns


1337 1928 1573 2268 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units




0028 ndash0281 0033 ndash0331 ns


1437 1945 1690 2288 ns


1158 1760 1363 2070 ns





1726 1726 2030 2030 ns


OUTPUT = BYPASS

4557 4557 5361 5361 ns


OUTPUT = BYPASS

4371 4371 5142 5142 ns



6767 6767 7960 7960 ns



6257 6257 7360 7360 ns



8651 8651 10178 10178 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



3569 3569 4199 4199 ns



5899 5899 6940 6940 ns


1237 1237 1456 1456 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns



4642 5254 5461 6181 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units







2032 2483 2390 2922 ns



1996 2608 2348 3068 ns







0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns
















1725 1725 2029 2029 ns


4296 4296 5054 5054 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


6180 6180 7270 7270 ns


3485 3485 4100 4100 ns


1231 1231 1448 1448 ns


255 255 216 216 MHz




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


3922 3922 4630 4630 ns




1828 2384 2150 2805 ns


4642 5254 5461 6181 ns





FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units


2032 2483 2390 2922 ns


1996 2608 2348 3068 ns






0350 0350 0350 0350 ns


0987 0987 1161 1161 ns




1003 1003 1003 1003 ns



1538 1977 1810 2326 ns



ndash0181 0063 ndash0213 0075 ns



1566 2005 1842 2358 ns



ndash0183 0061 ndash0216 0072 ns



1503 1941 1768 2284 ns



ndash0152 0092 ndash0178 0109 ns



1837 2337 2161 2750 ns

FPGA Fabric SRAM




Grade

ndash1

SET

Filter

OFF

Speed

Grade

ndash1

SET

Filter

ON

Speed

Grade

STD

SET

Filter

OFF

Speed

Grade

STD

SET

Filter

ON

Units
















1723 1723 2028 2028 ns


4286 4286 5042 5042 ns


6173 6173 7262 7262 ns


3481 3481 4096 4096 ns


1228 1228 1444 1444 ns


255 255 216 216 MHz

FPGA Fabric SRAM




Table 8-1 μPROM












5526 6501 ns




















JTAG






Units










7351 ms




















Units













1929 micros









VDD

VPPVDDIx

DEVRST_N

INBUF

OUTBUF

TD EVR ST2PO R

TD EVR ST2O U T

RCOSC_50MHz

POWER_ON_RESET_N



LowHigh


TD EVR ST2R GR ST

User Control


User Control


TD EVR ST2G RS T

Weak pullup

TD EVR ST2W PU

TRG R ST2O UT

TRG R ST2G RS T

TRG R ST2PO R

TPO R2G R ST

TO UT2 POR

TN oGR ST2 OU T








mdash 4625 50 5375 MHz




(peak to peak)



Output jitter

(peak to peak)

with FPGA fabric

switching noise1





On-Chip Oscillator








10 mdash 400 MHz




10 200 MHz














ps








Ref Clock

IO Standard


Temperature (degC)



Unit



ps










ps



ps





ps


ps






Ref Clock

IO Standard



Unit



LVDS25

HCSL

RSDS

BLVDS

M-LVDS

MiniLVDS












continuedRef Clock

IO Standard



Unit

Differential 33V

MSIO input

LVPECL

LVDS33


















high






mdash 143 mdash ns



mdash 145 mdash ns






33V 20 mA

25V 16 mA

18V 12 mA

15V 8 mA

12V 4 mA












SET FilterON

SET FilterOFF

SET FilterON

Units


0073 1007 0086 0956 ns


0456 0618 0536 0730 ns




1234 2105 1452 2247 ns


0228 0358 0268 0424 ns


-0456 -0456 -0536 -0536 ns


0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units






1234 2105 1452 2247 ns






SET FilterON

SET FilterOFF

SET FilterON

Units


0228 0358 0268 0424 ns




0601 0601 0707 0707 ns


0961 0961 1131 1131 ns






SET FilterON

SET FilterOFF

SET FilterON

Units




1229 2100 1446 2241 ns


0205 0334 0241 0396 ns




0601 0601 0707 0707 ns


3171 3171 3731 3731 ns











2912 2912 3426 3426 ns


2040 2040 2400 2400 ns






Delay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

0 1194 1404 0837 0984 0828 0975 ns

1 1344 1581 0979 1152 0971 1142 ns

2 1443 1697 1088 1280 1081 1271 ns

3 1593 1874 1235 1453 1224 1440 ns

4 1669 1964 1295 1523 1288 1515 ns

5 1819 2140 1442 1696 1431 1684 ns

6 1919 2257 1549 1822 1541 1813 ns

7 2069 2434 1693 1992 1685 1982 ns

8 2099 2469 1739 2046 1729 2034 ns

9 2249 2646 1881 2213 1873 2203 ns

10 2348 2762 1993 2344 1983 2333 ns

11 2498 2939 2136 2512 2126 2501 ns

12 2575 3029 2200 2588 2189 2576 ns

13 2725 3206 2342 2755 2333 2744 ns

14 2824 3322 2454 2886 2443 2873 ns

15 2974 3499 2598 3056 2587 3043 ns

16 2967 3490 2596 3053 2582 3039 ns

17 3117 3667 2738 3221 2725 3205 ns

18 3216 3783 2848 3350 2836 3336 ns

19 3366 3960 2992 3520 2979 3504 ns

20 3443 4050 3054 3593 3042 3579 ns

21 3593 4227 3199 3763 3185 3747 ns

22 3692 4344 3310 3894 3296 3877 ns

23 3842 4520 3455 4064 3438 4045 ns

24 3872 4555 3498 4115 3483 4097 ns

25 4022 4731 3642 4285 3627 4267 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

26 4121 4848 3753 4415 3737 4396 ns

27 4272 5025 3896 4584 3880 4564 ns

28 4347 5114 3959 4657 3944 4639 ns

29 4498 5291 4103 4826 4086 4807 ns

30 4596 5406 4212 4955 4198 4938 ns

31 4747 5584 4357 5125 4340 5105 ns

32 4709 5539 4328 5091 4309 5070 ns

33 4859 5716 4472 5261 4452 5238 ns

34 4958 5833 4581 5389 4563 5368 ns

35 5108 6010 4725 5559 4706 5536 ns

36 5184 6099 4787 5632 4770 5611 ns

37 5335 6276 4933 5803 4913 5779 ns

38 5434 6392 5042 5932 5023 5909 ns

39 5584 6569 5187 6102 5166 6078 ns

40 5614 6604 5230 6152 5211 6131 ns

41 5764 6781 5375 6323 5354 6299 ns

42 5863 6898 5484 6451 5465 6429 ns

43 6013 7074 5630 6623 5610 6600 ns

44 6089 7163 5690 6694 5671 6672 ns

45 6240 7340 5838 6867 5815 6841 ns

46 6339 7457 5947 6996 5925 6971 ns

47 6489 7634 6093 7167 6069 7139 ns

48 6481 7624 6088 7162 6064 7134 ns

49 6632 7801 6235 7335 6207 7302 ns

50 6731 7918 6343 7462 6318 7433 ns

51 6880 8094 6487 7631 6462 7602 ns

52 6956 8183 6549 7704 6524 7674 ns

53 7107 8361 6694 7875 6667 7843 ns

54 7207 8478 6805 8005 6778 7974 ns




continuedDelay

Step

DDR IO

Speed

Grade ndash1

DDR IO

Speed

Grade STD

MSIO IO

Speed

Grade ndash1

MSIO IO

Speed

Grade STD

MSIOD IO

Speed

Grade ndash1

MSIOD IO

Speed

Grade STD

Units

55 7357 8655 6949 8174 6922 8143 ns

56 7387 8690 6994 8227 6965 8193 ns

57 7537 8866 7139 8398 7108 8362 ns

58 7636 8983 7246 8524 7220 8494 ns

59 7786 9160 7392 8696 7365 8664 ns

60 7862 9249 7454 8768 7426 8735 ns

61 8012 9426 7598 8939 7569 8904 ns

62 8112 9542 7708 9068 7681 9036 ns

63 8262 9719 7852 9237 7825 9205 ns












































0238 12 V





























































to 125

25 to 125 ndash55 to125

ndash55 to125

25 to 125 ndash55 to125

ndash55 to 125


360 80 107 360 80 107 100


06 ndash18


See tables





05 ndash24



VID geVICM


VID geVICM
















ndash1 400 500 800 ps


STD 600 800 1300 ps











Jitter)

















































Max(STD)

Units




1 mdash 100 90 MHz



1 mdash 66 58 MHz



1 mdash 75 66 MHz



1 mdash 66 58 MHz


















(1FSWCLK)

mdash mdash ns









(ndash1)Max(STD)

Units


















Temperature

forced on

package


using ndash55 degC

and 100 degC

T0 calculated

at ndash55 degC

TJ calculated

using m and T0

Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash74879 61517




25 degC 0792 2213 degC 287 degC

85 degC 0710 8353 degC 147 degC

100 degC 0688 10000 degC 000 degC



Temperature

forced on

package


m calculated

using 0 degC

and 125 degC

T0 calculated

at 0 degC


Accuracy

(Actual

ndash Calculated)

ndash55 degC 0895

ndash73099 60234




25 degC 0792 2339 degC 161 degC

85 degC 0710 8333 degC 167 degC

100 degC 0688 9942 degC 058 degC

125 degC 0653 12500 degC 000 degC


























Revision History








Revision History

















Revision History






















Revision History



























Revision History










Revision History































ISBN













Introduction

1 Device Status


Table of Contents








1131 Theta-JB

1132 Theta-JC

2 Power Consumption





41 Input Buffer



44 IO Speeds




462 33V LVCMOSLVTTL



463 25V LVCMOS



464 18V LVCMOS



465 15V LVCMOS



466 12 V LVCMOS



467 33V PCIPCIX
























481 LVDS




482 B-LVDS



483 M-LVDS



484 Mini-LVDS



485 RSDS



486 LVPECL




491 Input Register










51 LUT4





7 FPGA Fabric SRAM




9 JTAG

91 Live Probe











20 Revision History



Customer Support


Legal Notice

Trademarks



DS0131 RTG4 FPGA Datasheet - Microsemi

Documents

Transcript of DS0131 RTG4 FPGA Datasheet - Microsemi