driving LED using XC9572XL CPLD

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Summary

This application note will help designers get the best results from XC9500XL CPLDs. Included are practical details on suchtopics as pin migration, timing, mixed voltage interfacing, power management, PCB layout, high speed considerations andJTAG best practices.

Xilinx Family

XC9500XL

IntroductionTo get the best performance from any CPLD the designermust be aware of its internal architecture and how the vari-ous device features work together. This application noteprovides useful examples and practical details for creatingsuccessful designs. These design techniques apply to allXC9500XL devices because the architecture is uniformacross the family.

XC9500XL ArchitectureThe XC9500XL architecture (Figure 1) bears a strongresemblance to its predecessor, the popular XC9500 fam-ily. In the XC9500XL family, a few changes were introducedwhere significant system improvement could be gained.The resulting family is one which can operate in a stand-alone 3.3V environment or in mixed 3.3/5V systems or inmixed 3.3/2.5V systems. Propagation delays are as fast as4 nanoseconds with clock speeds up to 200 MHz. As withthe XC9500 family, the XC9500XL family part numberingdirectly reflects the number of macrocells contained in eachpart. Where common packages exist, both XC9500 andXC9500XL have the same functional pins, so legacydesigns can be easily migrated from XC9500 versions toXC9500XL versions. The main changes are small, butimportant. First, a new FastCONNECT II Switch Matrix isintroduced with more inputs per Function Block and greaterspeed. Second, Macrocell functionality is enhanced byadding clock enable capability. Third, an improved powerup model makes interfacing with other chips even easierthan before. Fourth, each macrocell can select the clockphase of any clock source - globals or product term, individ-ually. Finally, this is all automatically supported with XilinxFoundation and Alliance Design Software solutions makingCPLD designs easier than ever before.

Function Block InterconnectXC9500XL interconnect is performed by an extremely fasthigh speed multiplexer that connects all input pins andmacrocell feedback points to Function Block inputs. Animportant fact about the interconnect is that all connectionsare uniform, and uniformly fast. This allows the XC9500XLto deliver a low power, fast and more flexible solution thanany CPLD available.

Function BlocksOne factor that limits the ability of design software to fitdesigns is the number of inputs available for signals to gainentry into the CPLD Function Blocks. XC9500XL FunctionBlocks permit up to 54 signals to find entry sites. Once sig-nals gain entry, the And Array portion of the Function Blockcan attach to whatever macrocells are needed.

The And Array contains ninety product terms that areassigned as needed by the design software which controlsthe Product Term Allocator. The software will direct productterms to macrocells to build the designer’s functions withthe number required for each macrocell. Up to ninety prod-uct terms can be assigned to a macrocell, if required. Mac-rocell outputs can be directed by the FastCONNECT IISwitch Matrix to attach to output and / or feedback points.See Figure 2.

1 Designing With XC9500XL CPLDs

XAPP112 January 22, 1999 (Version 1.1) Application Note

APPLICATION NOTE

XAPP112 January 22, 1999 (Version 1.1) 1

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Designing With XC9500XL CPLDs

In-System Programming ControllerJTAGController

I/OBlocks

FunctionBlock 1

Macrocells1 to 18

Macrocells1 to 18

Macrocells1 to 18

Macrocells1 to 18

JTAG Port

3

54

I/O/GTS

I/O/GSR

I/O/GCK

I/O

I/O

I/O

I/O

2 or 4

1

I/O

I/O

I/O

I/O

3

X5877

FunctionBlock 2

54

FunctionBlock 3

54

18

18

18

18FunctionBlock N

54

Ad

van

ced

Inte

rco

nn

ect

MA

TR

IXF

astC

on

nec

t II

Sw

itch

Mat

rix

Figure 1: XC9500XL Architecture

Macrocell 18

Macrocell 1

ProgrammableAND-Array

ProductTerm

Allocators

FromFastCONNECT II

Switch Matrix

X5878X5878

54

1

To FastCONNECT IISwitch Matrix

To I/O Blocks

OUT

GlobalSet/Reset

3

18

PTOE18

18

GlobalClocks _01_01

Figure 2: XC9500XL Function Block

2 XAPP112 January 22, 1999 (Version 1.1)

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The MacrocellIn its native configuration, the XC9500XL macrocell(Figure 3) can be thought to have 5 product terms directlyavailable to it. By appropriately importing unused neighbor-ing product terms, the macrocell logic can “grow”. Byexporting unused product terms to neighboring macrocells,the macrocell logic can “shrink”. Table 1 shows about howmany product terms (P-Terms) are needed to form somecommon logic functions. When designing, this gives anidea of how many p-terms are used to create the variousfunctions. Naturally, more operations exist than these,which can be found in the Xilinx Library documents.

As shown in Figure 3, the macrocell is comprised of theproduct term allocator, several configuration multiplexersand a D/T type flip flop with clock enable. The five nativeproduct terms can be thought of as directly available at thismacrocell site. In the native condition, each product termcan be thought of as having at least three alternate config-urations.

First, a p-term has a designated specialty function at a par-ticular macrocell. This is the ability to form a product termoutput enable, a product term clock, a product term set,product term reset or drive one leg of the EX-OR gate. Analternate configuration for a product term is to participate inthe local sum of products logic via the OR gate that drivesone EX-OR input pin. If a product term does not contributeits specialty function at the macrocell, or participate in thelocal logic OR operation, then it is available to be collectedby another OR and forwarded to a neighbor macrocell ineither direction. This is termed cascading, and will bedescribed in more detail later. Finally, the product term set

99012002

ToFastCONNECTIISwitch Matrix

AdditionalProductTerms(from othermacrocells)

GlobalSet/Reset

GlobalClocks

AdditionalProductTerms(from othermacrocells)

To I/O Blocks

OUT

1

0

54

3

PTOE

D/T QS

R

ProductTerm

Allocator

Product Term Set

Product Term Clock

Product Term Reset

Product Term OE

Product Term Clock Enable

EC

Figure 3: XC9500XL MacrocellTable 1: Macrocell/Product Term Usage

Data Operation P-Terms UsedShift Register 1 per bit

Counters 1 to 4 per bit

N:1 Mux N

2-Bit Adder 6

Exclusive-OR 2

Storage Register 1


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and reset product terms can assume the functionality ofdriving the flip flop clock enable. Figure 4 shows details ofProduct Term Allocation and Figure 5 and Figure 6 showhow clock enable circuitry is created.

Figure 4: Product Term Allocation

In Figure 4, all but the Product Term Allocators have beenomitted for clarity. In this situation, the design requirementis to deliver 18 product terms to the designated sum ofproduct output site. The native set of 5 p-terms is supple-

mented with 5 p-terms from each directly adjacent neighbortaking the tally to 15 product terms. In this case, three morep-terms are needed, so the software must find them. Thenext site (to the north) requires two of its native 5 productterms, but three are available to meet the demand. Thesoftware forwards the available three p-terms to therequired delivery site. In this case, two cascade times arerequired to provide 18 product terms. Note that the solutionis not unique. The software could just as well encounter anadjacent neighbor with locked down product terms andbeen forced to skip over another macrocell to satisfy itsneed. The bidirectional cascade permits passing to/fromboth directions, which increases the likelihood of findingneeded logic. This typically gives results within a singlecascade and occasionally needs to go further. Productterms are located circularly so that the bottom macrocellcan pass directly to the top macrocell and vice versa. Animportant factor here is that every macrocell has the samepotential access to product terms.

Figure 5: D/T Flip Flop Clock Enable Notation

Figure 6: D/T Flip Flop Clock Enable Structure

In Figure 5, the Flip Flop shows separate D/T and EC(clock enable) pins attached to the flop. Actually, the termclock enable is a misnomer, because as shown in Figure 6,it is simply a mux select pin that chooses between an exter-nal “D” pin and the flop's own Q output. Clock enable doesintroduce an additional control pin to be managed, but isoften used in cases where designers would otherwise betempted to gate the clock to obtain design control.

Not emphasized in the macrocell diagram is the ability toselectively invert any clock entering the clock mux beforeattaching to the flip flop clock input point. Figure 7 detailshow this is achieved at every macrocell site.

Macrocell LogicWith 18 Product Terms

Macrocell LogicWith 2 Product Terms

Product TermAllocator


X5896



>EC

D/T QS

R

To Out

>

D/T QS

R

To Out

D

CE

To FastCONNECT


R


5

Figure 7: Macrocell Clock Inversion Selection

XC9500XL Pin Migration CapabilityTable 2 shows the pin compatibility among XC9500XLdevices. Designs can be easily migrated to larger andsmaller devices. In many cases greater density with equiv-alent speed can be obtained by using larger parts. If adesign is initially targeted to a smaller device, the samedesign can be easily moved into a larger device, if more

capacity is required. This capability allows designers tomaintain their pin assignments when designs must bemoved to a larger device. Moving designs from larger tosmaller devices can also be accomplished, while keepingthe original pinout, if the smaller device has enoughresources to contain the design.

A reasonable design practice would be to pick the lowestcapacity for a given package in the slowest speed grade.Then, as design proceeds, larger or faster parts can acceptthe design as expectations and/or needs change. Pickingthe slowest and least dense part would economically be thebest first choice, anyway. The key is to first pick the oneclosest to your needs. This approach would be somewhatdifferent, if future field upgrade was a consideration,because here it might be appropriate to “over spec” a partto include speed latitude and additional available functionfor unforeseen future changes.

XC9500XL Timing ModelThe XC9500XL Timing Model is shown in Figure 8. Thistype of diagram exposes the architecture of an XC9500XLpart in a way that each encountered time delay is shown.Table 3 summarizes the individual time delays found. Theparameters identified in Table 3 are present in the fitterreport for a particular design. This lets a designer identifyexactly how their design's performance is determined by

simply tallying the delays incurred as each signal visits thevarious internal part functions. For instance, tPD is deter-mined in the simplest configuration as:

tPD = tIN + tLOGI + tPDI + tOUT

Other paths are easily identified and more examples areprovided in the XC9500XL Timing Application Note. (SeeXilinx application note number XAPP111 - Using theXC9500 Timing Model.)

>EC

D/T QS

R

GCKs

Pterm Clock

Table 2: XC9500XL Available Packages and Device I/O Pins

XC9536XL XC9572XL XC95144XL XC95288XL

44-Pin PLCC 34 3464-Pin VQFP 36 52100-Pin TQFP 72 81144-Pin TQFP 117 117208-Pin PQFP 16848-Pin CSP 36 38144-Pin CSP 117352-Pin BGA 192


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Table 3: Timing Parameters

Practical Considerations

Power On ModelXC9500XL parts are designed to provide a flexible voltageenvironment for today’s demanding voltage environments.Key to this is considering lots of details that permit design-ers the choice of speeds and densities, but automatically

handle electrical issues that are frequently overlooked byothers. First on the list is a flexible “Power On Model”.Figure 9 shows how an XC9500XL powers up. In this dia-gram, we will assume VCCINT and VCCIO are either tiedtogether or rising together. In this case, as VCC rises, thepins are assumed initially to be in high impedance condi-tion, with large pullup resistance to VCCINT. This provides alogic high that can be easily counter driven by a pin from anexternal chip wishing to dominate that electrical point. Atone point in the power up process, the XC9500XL passesits internal configuration bits to the parts functionalresources and the outputs are configured as dictated by theprogramming pattern. When the part is powered down,small keeper circuits retain the last value the pins drove asVCC drops. Some variation occurs if VCCIO is cycled sepa-rately, but in all cases, the most benign electrical state isassumed.

Figure 9: Power Up Model

S*tPTA

tPTSR

tPDI

tSUItHI

tCOI

tAOItRAI

D/T Q

SR>

tIN

tGCK

tGSR

tLOGILP

tLOGI

tPTCK

tPTTS

tOUT

tSLEW

tEN

tF

Macrocell

EC

tGTS

tECHO

tECSUI

Figure 8: XC9500XL Timing Model

Parameter NametAOI Register asynchronous S/R to output delay

tCOI Resister clock to output valid delay

tE Output tri-state enable time

tECHO Enable clock hold time

tECSUI Enable clock setup time

tGCK GCK buffer delay

tGSR GSR buffer delay

tGTS GTS buffer delay

tHI Register hold time

tIN Input buffer delay

tLOGI Internal logic delay

tLOGILP Internal low power logic delay

tOU Output buffer time delay

tPDI Combinatorial logic propagation delay

tPTA Incremental product term allocator delay

tPTC Product term clock delay

tPTTS Product term tri-state delay

tRAI Register asynchronous S/R recovery before clock

tSLEW Slew rate limited delay

tSUI Register setup time

Outputs as configured

Outputs HIGHZ, pulled up

First time power up

Outputs followlast value (assumingVCCIO is still up here)


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Mixed Voltage OperationXC9500XL I/Os are designed to deliver output signals thatrange from 0 to 3.3V (+/- 10%). Figure 10 details the sepa-ration between VCCINT and VCCIO and shows the CMOSoutput buffer. Figure 11 and Figure 12 show operation with

mixed voltages. Table 4 summarizes the voltage compati-bility of the XC9500XL and other logic families. Finally,Figure 13 shows the input hysteresis that improves noisemargin for XC9500XL inputs.

Figure 10: XC9500XL I/O Architecture and Output Structure

Figure 11: Mixed Voltage 3.3/5V Operation Figure 12: Mixed Voltage 3.3/2.5V Operation

Table 4: XC9500XL Voltage Compatibility Summary

Power Management ConsiderationsXC9500XL family parts provide substantial power reduc-tion simply because the internal VCC ranges well below thatof 5V CPLD families. Due to the square law relationship,this alone provides a nearly 60% reduction in power over5V families. However, internal options are provided to lowerpower even more. This includes the ability to operate eachproduct term in a low power mode (at nominal speed reduc-tion) and the ability to operate the I/O pins at 2.5V whenappropriate.

CORELOGIC

VCCINT = 3.3VVCCIO = 3.3V/2.5V VCCIO

P

N

Any5V TTLdevice

XC9500XLAny3.3Vdevice

5V

3.3VVCCIO VCCINT

5V3.3V

3.3V

3.3V

3.3V

2.5V

Any3.3Vdevice

XC9500XLAny2.5Vdevice

VCCIO VCCINT

3.3V2.5V

2.5V

2.5V

5V CMOS 5V TTL 3.3V LVCMOS 3.3V LVTTL 2.5V NormalVIL X X X X X

VIH X X X X X

VOL X X X X X

VOH 3.3V 3.3V X X X

1.40V 1.45VVIN (Volts)

VOH

VOUT

VOL

(Volts)

Figure 13: XC9500XL Input Hysteresis

50mV


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Optimizing PowerThe following guidelines will aid in reducing power con-sumed by an XC9500XL CPLD.

1. Terminate unused Input pins. This guarantees they arenot floating. A convenient way to do this is with the UserProgrammable Ground (UPG) feature.

2. Assign High Speed only to those macrocells that abso-lutely require it. The remaining macrocells should beplaced in low power mode.

3. Eliminate or minimize slow slewing input signals. Thesesignals require input buffers to remain in their conduct-ing region for long periods.

4. If possible, set VCCIO to the 2.5V level to limit the outputvoltage swing range and lower power in that section.

Power Supply SequencingSeparate power supplies for VCC and VCCIO may be pow-ered up or down in any sequence without harming anXC9500XL CPLD.

High Speed Design ConsiderationsAlthough XC9500XL parts are not prone to having signalquality issues, ground rise and signal reflections can bemanaged by planning. The following design guidelinesshould strongly be considered in advance to avoid difficultywhen operating with lots of simultaneously switching sig-nals and at high frequencies.

1. Only connect the essential outputs to I/O pins. Interme-diate shift register bits and counter bits that need notdrive outputs should remain buried.

2. Minimize the number of outputs switching simulta-neously.

3. Two global clock inputs can be managed by delayingone to introduce signal skew. Breaking long clock chainsacross multiple clock drivers can provide skew (lessthan 1 nanosecond) that can significantly reduce groundrise.

4. Using additional ground pins can lower ground riseeffects. Unused pins configured as User ProgrammableGrounds (UPG) can be tied directly to the PCB groundplane. This splits the current driven into heavily loadedground pins and lowers the voltage rise. Best UPGplacement is uniformly around the chip, if possible.

5. Signal skewing can reduce ground rise. This can beachieved by mixing ordinary and fast slew rate outputs.Only assign fast slew rate to signals that require it.

PC Board Layout ConsiderationsKey to a good digital design is a good electrical design. Thefollowing checklist will be helpful to make sure practical

oversights do not occur when creating a new printed circuitboard. Most of these practices are typical of high speedmicroprocessor board design, so there should be no issuewhen using the same practices for XC9500XL CPLDdesigns.

Layout Checklist1. Avoid floating inputs. Invoke User Programmable

Ground if possible to deliver low driven output signal tointernal input. For additional ground management,attach such pins to PCB ground.

2. Locate XC9500XL parts near the devices they drive (orare driven by) to minimize transmission line effects.Usewide spacing between fast signal lines (particularlyclocks) to minimize crosstalk.

3. Place power pins (VCC and GND) on separate boardplanes. Fast signals should reside on a different plane,still.

4. Decouple all device VCC pins with 0.1 µF and 0.01 µFcapacitors connected to the nearest ground plane. Lowinductance surface mounted capacitors are recom-mended. Some designs may require different values.

5. Decouple the printed circuit board power inputs with 0.1µF ceramic (high frequency) and 100 µF electrolytic (lowfrequency) filter capacitors.

6. Connect all device ground pins together, to ground.

7. Avoid using sockets to attach XC9500XL CPLDs to thePCB. Direct soldered connection minimizes inductanceand reduces ground rise. XC9500XL CPLDs are specif-ically designed for direct PCB attachment.

Pin Preassigning GuidelinesFrequently, designers must layout their PCBs prior to thedevelopment of the design. Any commercially availableCPLD will have difficulty keeping the pin assignment for atotally arbitrary design done with little or no forethought. Asmentioned earlier, it is a good idea to always target adesign to the lowest density available in a given packagefor the slowest speed grade available.

If a legacy design can be used as a “comfortable” model,then it's pin assignment may be appropriate. In this case,having density and speed slack available is important. If nolegacy design exists, spreading the pins uniformly so thatavailable blank slots exist between pins will help assureavailable product terms will exist to handle future changesas the design proceeds. Remember, pin preassigning with-out having the software make a first pin assignment is notrecommended. If at all possible, let the design softwarehave a preliminary version of the design prior to producinga printed circuit board, to assure a reasonable first pinouthas been obtained.

8 January 22, 1999 (Version 1.1)

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Boundary-Scan and ISP CapabilityXC9500XL CPLDs include a significant repertoire of IEEEstd 1149.1testing and JTAG ISP instructions. Table 5 sum-marizes the set of instructions that might be encounteredduring a design. Others exist, which are proprietary to Xil-inx CPLDs.

Table 5: Supported JTAG & ISP Instructions and Affected Registers

Multi-voltage JTAG CapabilityXC9500XL CPLDs are designed specifically to operate in amultivoltage JTAG environment and maintain full signal andJTAG integrity. Internal pullup resistors are on TMS andTDI to 3.3V.

ISP ChecklistWhen programming an ISP CPLD, best results areobtained when common practices are used. The followingchecklist gives the standard points to observe to obtainbest ISP results.

1. Make sure VCCINT is within the rated value: 3.3V +/- 5%.

2. Provide both 0.1 and 0.01 µF capacitors at every VCCpoint of the chip, and attach directly to the nearestground.

3. Use the latest Xilinx download cables. This would be aParallel Cable with serial numbers greater than 5000 orany X-Checker cable.

4. Consider including buffers on TCK and TMS interleavedat various points on your JTAG circuitry to account forunknown device impedance.

5. Always be certain to use the latest version of the XilinxJTAG Programmer Software.

6. Put the rest of the JTAG chain into HIGHZ when pro-gramming a troublesome part. This is optional.

7. If free running clocks are delivered into the ISP CPLD, itmay be necessary to disconnect or disable their entryinto the CPLD while programming.

8. For XC9500XL designs attach VCC from the parallelcable to 3.3V on the PCB.

ConclusionXC9500XL CPLDs provide an abundance of logicresources and require only a minimum number of designconsiderations to obtain the best results. By carefully fol-lowing the guidelines and checklists included here, design-ers can expect to obtain all the features needed in today’shigh speed, low voltage systems.

Instruction JTAG RegistersBypass Bypass Register

Clamp Bypass Register

EXTEST Boundary Scan Register

FlashErase Configuration Register

FlashProgram Configuration Register

FlashVerify Configuration Register

HIGHZ Bypass Register

INTEST Boundary Scan Register

Sample/Preload Boundary Scan Register


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