DreamWork Animation DWA

Copyright © 2015, Intel Corporat ion. Al l r ights reserv ed. *Other names and brands may be claimed as the property of others.

Anson Chu (presenter) & Alex Wells,

& Martin Watt (DWA)

August 11 & 13, 2015

DreamWork Animation (DWA):

How We Achieved a 4x Speedup of Skin Deformation

with SIMD


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Copyright © 2015, Intel Corporat ion. Al l r ights reserv ed. *Other names and brands may be claimed as the property of others.Copyright © 2015, Intel Corporat ion. Al l r ights reserv ed. *Other names and brands may be claimed as the property of others.

DWA Character with Skin Deformation

4


The Algorithm

Vectorization– Basic techniques

– SBB Integration

– Indirect Access

– Data padding

– Manage uniform data

Results

Summary

How we got 4x SIMD speedup

5


Skin Deformation Videos

6


DWA’s largest and most complex deformation kernel

C++ Object-Oriented– Up to 3 levels of indirect access

Loop body– Many levels of nested function calls– Multiple source files across multiple libraries– 8625 instructions executed per iteration

Double-precision math Parallel, but no SIMD

Skin Deformation Algorithm - Overview

7


8

Motion System Skin Deformation

Hierarchy Joints Control Points Curve,Offsets,

& Attachment Bindings

Skin MeshAttachments boundto Skin Vertices


Compute deformed vertex positions and offsets of skin mesh– Control Points are on a curve

Curve driven by character’s motion system

– Each vertex Attachment 1-4 “Control Point(s)”

– Shared (e.g. 3 out of 4)

Weights, offsets, scales, …

Skin Deformation Algorithm - Detail

0 1 2 3 2 3 4 51 2 3 4

Control Points (Curve)

Skin Mesh

Attachment

0

12

34

5

9


SIMD instructions – Can process multiple data lanes in a single

operation

One vector register can hold multiple data values– SSE4 : 128-bit

2 doubles or 4 floats

– AVX : 256-bit 4 doubles or 8 floats

Vector operations compute math (+, -, *, /) on all of data lanes at the same time

SIMD = Single Instruction Multiple Data

vector_register_10 1 2 3


Step 4vector_register_10 1 2 3

SIMD += operation

vr1[0]+=vr2[0]

vr1[1]+=vr2[1]

vr1[2]+=vr2[2]vr1[3]+=vr2[3]

10


No function calls

– Inlined all calls made from loop body (i.e. “inline” keyword)

– Removed non-inlineable calls (e.g. print statements)

– “#pragma inline recursive” scoping entire loop body

Single entry, single exit

– Removed data-dependent exit conditions (e.g. early outs)

– Removed exception throwing

Intel® C++ Composer XE (ICC) Vectorization

11

https://software.intel.com/sites/default/files/8c/a9/CompilerAutovectorizationGuide.pdf

https://software.intel.com/en-us/node/524498

https://software.intel.com/sites/default/files/8c/a9/CompilerAutovectorizationGuide.pdf


Straight-line code Removed conditionals

– No “switch” statements

– “if” statements supported (as masked or blended assignments) But best to avoid

Created templatized inlined functions– To handle conditionals at compile time

– Branch outside loop instead of at each iteration

ICC Vectorization (Part 2)

12

Code example on next slide


Templates to avoid conditionals inside loopvoid compute() {

switch (mAlgorithm->mVersion){case 0:

computeHelper<0>(); break;case 1:

computeHelper<1>(); break;default:};

}

template<int VersionT>void computeHelper() {

for (int i = 0; i<mCount; ++i) {mAlgorithm->computePosition<VersionT>(data[i]);

}}

template<int VersionT>inline void computePosition(Data d) {

if (VersionT < 1) {// support older version

} else {// run newer version of algorithm

}}

void compute() {for (int i=0; i<mCount; ++i) {

mAlgorithm->computePosition(data[i]);}

}

void computePosition(Data d) {if (this->mVersion < 1) {

// support older version} else {

// run newer version of algorithm}

}13

Converted “Version” to template argument VersionT

Dead code elimination will remove one of these branches at compile time

“VersionT” (known at compile time) creates separate code paths

Hoisted conditional to outside loop

Main Loop

Loop Body


SIMD Building Blocks (SBB)

C++ template library

Abstracts out aspects of creating an efficient data parallel (SIMD + threading) program– Via concepts of Containers, Accessors, Kernels, and Engines

– Helps avoid common pitfalls of writing efficient SIMD code

Compatibility– Compatible with Intel® Threading Building Blocks (TBB) and

OpenMP*

– Generates correct code with a C++11 compiler

What is SBB?

14

Developed by Alex Wells ([email protected])


Let compiler (ICC) handle privatization of local variables in a SIMD loop– Each SIMD lane gets a private instance of the variable

“SBB Primitives” restrict objects to help the compiler succeed in privatization– Plain Old Data

– Inlined object members

– No nested arrays in objects

– No virtual functions

Follow SBB’s Vectorization Strategy

15



Converting to a SBB Primitive (Example)

class Vec3 {//...double length();

double v[3];//...

};

class Vec3 {//...inline double length();

double x;double y;double z;//...

};

Individual data members

16


ICC optimization report on vectorization– Compile with flag: “-qopt-report=5 -qopt-report-phase=vec”

– Provides per loop summary of vectorization and estimated performance impact

– Helps isolate what prevented vectorization of a loop

Intel® VTune™ Amplifier XE– Analyzed performance (used Task API)

– Inspected assembly that actually executes

Useful Tools

17




ICC compiler tells us…

– “Could vectorize but may be inefficient”

Successfully forced vectorization with #pragma simd

– Actual runtime showed essentially no improvement

Opt-report

– “Estimates” a slowdown

Needed investigate into why

“Could vectorize but may be inefficient”

18

Use Opt-Report to investigate obstacles to efficient SIMD code


Indirect memory addressing– Gather : indexed reads (“loads”)

– Scatter : indexed writes (“stores”)

Gathers or scatters can degrade SIMD performance

We want to avoid indirect accesses

So, is there any loop-invariant data that we can treat as uniform across loop?

Opt-report littered w/ “indirect access” remarks

// Gatherfor (i = 0; i<N; ++i)

x[i] = y[idx[i]];

// Scatterfor (i = 0; i<N; ++i)

y[idx[i]] = x[i];

19

Loop index is used to look up another index


Most data is accessed via ControlPoint index

– Up to 3 levels of indirection

– Causing chains of gathers

Can we refactor algorithm such that ControlPoint indices would be loop invariant?

Algorithm Has Too Many Indirections

AttachmentData array

ControlPoint array

XformData array

Matrix3, Vec3, double, int, …XformData

i

j

k

20

Example on next slide


Sort, Hoist Uniform Data, & Sub-Loop

21

Original AttachmentsNo uniformity

0 1 2 3

2 3 4 5

2 3 4 5

2 3 4 5

1 2 3 4

0 1 2 3

1 2 3 4

0 1 2 3

0 1 2 3

0

1

2

8

Trip count = 9

Sorted: Each sub-loop has uniform ControlPoints.

Sub-loop #3Uniform: (2,3,4,5)

2 3 4 5

2 3 4 5

8

6

0 1 2 3

0 1 2 3

0 1 2 3

0 1 2 3

0

1

2

Sub-loop #1Uniform: (0,1,2,3)

3

1 2 3 4

1 2 3 4 Sub-loop #2Uniform: (1,2,3,4)

5

4

Control Point Indexes

2 3 4 57

6

3

5

4

7


Introduced data sorting…

– To break up Attachments into many sub-loops, Each with uniform set of ControlPoints

– Vectorize over each sub-loop Eliminating many indirect accesses

Attachment data is non-changing

– So only have to do sort once

Algorithm with uniform ControlPoints

Pull loop-invariant data outside loop

22



Hoisting ControlPoints outside loop (Example)

// Vectorized loopfor (int i = 0; i < count; i++){

AttachmentData& a = mAttachments[i];ControlPoint& cp0 = mControlPoints[a.index0];ControlPoint& cp1 = mControlPoints[a.index1];ControlPoint& cp2 = mControlPoints[a.index2];ControlPoint& cp3 = mControlPoints[a.index3];

computePosition(a, cp0, cp1, cp2, cp3);}

for (int i = ; i < mSubLoops.count; i++){

SubLoop& ss = mSubLoops[i];ControlPoint& cp0 = mControlPoints[ss.index0];ControlPoint& cp1 = mControlPoints[ss.index1];ControlPoint& cp2 = mControlPoints[ss.index2];ControlPoint& cp3 = mControlPoints[ss.index3];

// Vectorized sub-loop over Attachments with// loop-invariant ControlPointsfor (int j = ss.begin; j < ss.end; j++) {

AttachmentData& a = mAttachments[j];computePosition(a, cp0, cp1, cp2, cp3);

}}

Loop over unsorted Attachments

1. Added sub-loop2. Hoisted ControlPoints outside vectorized sub-loop

23


Resolved all “indirect access” remarks

– No more gather instructions

Impact of Uniform ControlPoints

Mine input data for Uniformity

XformData array

XformData

ControlPoint

Matrix3, Vec3, double, int, …

Set of (1-4) ControlPoint’sare uniform over loop

24

2x Speedup (AVX)


Main SIMD loop always starts and ends on SIMD boundaries– Processes N SIMD Lane Count (e.g. 4 doubles) iterations at a time

Peel loop - any iterations up to before first SIMD boundary

Remainder loop - any iterations from after the last SIMD boundary to the end of the iteration space

Anatomy of a SIMD Loop

25

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Loop from 3 through 18

Peel Loop(scalar)

Remainder Loop(scalar or masked SIMD)

Main SIMD Loop

Example of 4 Vector Lanes


VTune Shows Execution TimeScreenshot from Intel® VTune Amplifier XE

26

Main Loop (vectorized)

Remainder Loop

Peel Loop

Blue marks alongside scrollbar

indicate where execution time is spent in assembly


Investigated trip counts of the sub-loops

And observed short trip counts

– We had 4 to 32 or more iterations

– Enough to cover vectorization

Start and end of iteration space of sub-loops did not align with SIMD lane boundaries

– Spending over 35% in Peel and Remainder loops

Short Trip Counts

27


Added padded entries into our input data stream

Ensured iterations started and ended on a SIMD lane boundary

– 2 (SSE4.2), 4 (AVX)

– Attachment data is non-changing, so only have to do padding once

For padded entries, just repeat work

– Scatter result to same output address

Implemented data padding

28



Padded Attachments

0 1 2 3

0 1 2 3

0 1 2 3

0 1 2 3

1 2 3 4

1 2 3 4

0

1

2

1 2 3 4

0 1 2 3

0 1 2 3

8

Not padded

Sub-loop #1Trip count = 6

Sub-loop #2Trip count = 3

0 1 2 3

0 1 2 3

0 1 2 3

0 1 2 3

1 2 3 4

1 2 3 4

0

1

2

1 2 3 4

1 2 3 4

0 1 2 3

0 1 2 3

0 1 2 3

0 1 2 3

3

4

5

6

7

8

9

10

11

Padded to 4 data lanes

Sub-loop #1 Trip count = 8

Sub-loop #2 Trip count = 4

Padded Entries

Control PointIndexes

29

3

4

5

6

7

Main SIMD Loop

Remainder Loop

Peel Loop

Example of 4 Vector Lanes


Execution Time : Not Padded vs. Padded

Screenshots from Intel® VTune Amplifier XE

30

PaddedNot Padded

All time spentin Main SIMDLoop

Blue marks alongside scrollbar indicates

where executed time is spent in assembly


Allowed all of the time to be spent in our aligned vectorized code

Speedup overcame the processing overhead of padded data

Data Padding Impact

Pad data to align with SIMD lane boundaries

31

14% more speedup


After padding, compiler (icc14) chose to unroll our vectorized AVX loop

– Caused it to iterate by 8 element rather than 4

Since our we are padding to boundary of 4

– Once again, spending time in the peel and remainder loops

Resolved by explicitly setting SIMD length

– #pragma simd vectorlength(4)

Encountered obstacle to padding

Avoid surprises. Explicitly set vector length.

32


Inspecting assembly (VTune), we noticed room for improvement

Data is uniform for entire loop,

– But is still accessed via indirection at each loop iteration

So we refactored algorithm to manually manage allindirect accesses (from ControlPoint indexes) outside of loop

– Pre-populate all indirect data into uniform data structure

Uniform Indirection Overhead

33


Before entering a SIMD loop– For each uniform value the compiler may

Load scalar value into register

Broadcast scalar value in register to all lanes of SIMD register

Store SIMD register to new location on stack for use inside the SIMD loop body

– Multiply overhead by up to 59 doubles per Control Point

For long trip counts, overhead easily amortized

– But short trip counts can not

Overhead of Uniform Data in SIMD Loops

34


sbb::UniformSoaOver1d

– Store loop invariant data in a SIMD ready format

SIMD loops can directly access the data without conversion

– Decouples SIMD conversion overhead from the loop

Puts user in control of when to incur the overhead

– Over multiple sub-loops

Enables partial updates of Uniform Data

Enables reuse of Uniform Data

Uniform Data & SBB

35



Partial Updating of Uniform data

0 1 2 3

0 1 2 3

0 1 2 3

0 1 2 3

1 2 3 4

1 2 3 4

0

1

2

1 2 3 4

1 2 3 4

3

4

5

6

7

Loop #1 : Load uniform data for ControlPoints (0,1,2,3)

Loop #2 : Reuse uniform data for (1,2,3). Load (4).

2 3 4 5

2 3 4 5

2 3 4 5

2 3 4 5

8

9

10

11

Loop #3 : Reuse uniform data for (2,3,4). Load (5).

AttachmentIndexes

Control PointsSub-Loop #

36


From one sub-loop to the next, on average, we only update ¼ of the UniformData

– Save 75% of overhead involved in setting up uniform data

Impact of Managing Uniform Data

Explicitly manage uniform data

37

13% more speedup


Performance data collected using VTune– CPU Time– Instructions Executed

Hardware: SandyBridge, Xeon (dual-socket, 16-core) Single-threaded execution Comparison definitions

– Baseline Original algorithm

– New algorithm Scalar - Vectorization disabled SIMD - Vectorization enabled

Results

38


Results: Same Work, Less Instructions

39

8.5x improvement (AVX)

Lower is better


Results: Algorithm Speedups

Higher is better

4.2x total speedup (AVX)

40

1.5x Scalar speedup


Results: Do More in Less Time

41

SIMD,Double Resolution

Lower is better

Original algorithm,1x Vertices


Biggest payoff was from eliminating all indirection

Padded data to align with SIMD lane boundaries

Explicitly managed and re-used uniform data

Summary

42

4.2x total speedup!


Anson Chu : [email protected]

Alex Wells : [email protected]

For SBB inquiries, contact Alex!

Thank you!

43

mailto:[email protected]?subject=Siggraph 2015 SIMD Skin Deformation Inquiry

mailto:[email protected]?subject=Siggraph 2015 SIMD Skin Deformation Inquiry


Optimization Notice

44

Optimization Notice

Intel® compilers, associated libraries and associated development tools may include or utilize options that optimize for instruction sets that are available in both Intel® and non-Intel microprocessors (for example SIMD instruction sets), but do not optimize equally for non-Intel microprocessors. In addition, certain compiler options for Intel compilers, including some that are not specific to Intel micro-architecture, are reserved for Intel microprocessors. For a detailed description of Intel compiler options, including the instruction sets and specific microprocessors they implicate, please refer to the “Intel® Compiler User and Reference Guides” under “Compiler Options." Many library routines that are part of Intel® compiler products are more highly optimized for Intel microprocessors than for other microprocessors. While the compilers and libraries in Intel® compiler products offer optimizations for both Intel and Intel-compatible microprocessors, depending on the options you select, your code and other factors, you likely will get extra performance on Intel microprocessors.

Intel® compilers, associated libraries and associated development tools may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include Intel®

Streaming SIMD Extensions 2 (Intel® SSE2), Intel® Streaming SIMD Extensions 3 (Intel® SSE3), and Supplemental Streaming SIMD Extensions 3 (Intel® SSSE3) instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors.

While Intel believes our compilers and libraries are excellent choices to assist in obtaining the best performance on Intel® and non-Intel microprocessors, Intel recommends that you evaluate other compilers and libraries to determine which best meet your requirements. We hope to win your business by striving to offer the best performance of any compiler or library; please let us know if you find we do not.

Notice revision #20101101

C o p y r i g h t © 2 0 1 5 , I n t e l C o r p o r a t i o n . A l l r i g h t s r e s e r v e d . * O t h e r n a me s a n d b r a n d s ma y b e c l a i me d a s t h e p r o p e r t y o f o t h e r s .


Backup Slides


Manually define copy constructor for objects

– Compiler had trouble with some objects

– Even though logically equivalent to compiler provided default

Allows privatization of local variable instances inside vector loop

Replaced ‘bool’ with ‘int’

– ‘bool’ is not supported for SIMD privatization

Opt-report “unsupported data type” remark

May need to manually define copy constructor

47


__builtin_expect

– Added to conditionals when control flow follows a known path

– Allows compiler to test all data lanes to see that the expression was zero and skip a code block

Faster than following a masked blended code path

– Used carefully, and verified doesn’t hurt performance

Other incremental improvements

48

http://stackoverflow.com/questions/7346929/why-do-we-use-builtin-expect-when-a-straightforward-way-is-to-use-if-else

https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html


Okay to divide by zero

– Result will be NAN

Any subsequent operations with NAN, results in NAN

– Removed multiple conditional tests for zero when dividing

Continue computation

Test final result for NAN (if necessary)

– Hint: combine with ‘__builtin_expect’

Other incremental improvements (Part 2)

49

#define IS_NAN(val) \((val == val) == false)

https://en.wikipedia.org/wiki/NaN


If you store bool values as anything other than 32-bit, compiler needs to do extra work to test for true/false– In C++, a Boolean is:

False, when 0x0

True, when anything else

– But in SSE/AVX SIMD, True when 'high bit set‘

False otherwise

So we used int instead of bool– Tested explicitly against integer (0 or 1)

Other incremental improvements (Part 3)

50


Let SBB Containers & Accessors…

– Automatically handle data transformation and alignment

Let SBB Engines…

– Handle loop iteration

Let SBB Primitive and underlying compiler (ICC)…

– Handle privatization of local variables in a SIMD loop

Such that a private instance exists for each SIMD lane

SBB Integration

51


Converted data containers– sbb::Soa1dContainer (instead of std::vector) – Use SBB Accessors to read/write data from/to Containers

Converted algorithm loop– SBB Kernels

Define unit of work (i.e. loop body)

– SBB Engines Control code generation (e.g Scalar vs. Simd)

– Control peel or remainder loop generation– Set number of SIMD lanes

Control threading model (Single-threaded, TBB, OpenMP) and grain size.

SBB Integration – Containers, Kernels, Engines

52


Converted objects in DWA’s 3D math library

– Meet SBB Primitive requirements

– Example:

SBB Integration

// Math library’s 3D Vectorclass Vec3 {

//...protected:

double v[3];//...

};

#include <SBB/Primitive.h>class Vec3 {

//...public:

double x;double y;double z;//...

};SBB_PRIMITIVE(Vec, x, y, z)

53


SBB Primitive Nesting(Example)

#include <SBB/Primitive.h>class Vec3 {public:double x;

double y;double z;

};SBB_PRIMITIVE(Vec3, x, y, z)

struct AttachmentData {double weight;math::Vec3 offset;double scale;…

};

SBB_PRIMITIVE(AttachmentData,weight,offset,scale,…);

Primitives can be nested

54


Provides familiarity of AOS Object-Oriented programming,

– But stores data in SIMD efficient format internally (e.g. SOA)

– API similar to std::vector<Struct>

Used sbb::Soa1dContainer

SBB Integration: Container

class AttachmentPartition{

// Array of structures (AOS)std::vector<Attachment> mData;

}

class AttachmentPartition{

// Easily switch between types of memory layout//typedef sbb::Aos1dContainer<Attachment> SbbContainer;typedef sbb::Soa1dContainer<Attachment> SbbContainer;

SbbContainer mData;}

55


Converted loop to SBB kernel

Use SBB Accessors

– To read/write data from/to Containers, from within loop

SBB Integration: Kernel and Accessors// SBB accessors to input and output arraysauto sbbInputs = mPartition.mData->access();sbb::Aos1dAccessor<AffectedPosition, sbb::AccessByStride>

sbbOutputs(&(mAffectedPositions.rawDataArray()[0]), mCount);

// Define SBB Kernel (loop body)SBB_KERNEL_BEGIN(kernel)

SBB_ITER_D1_BEGIN(index){

// Get SBB accessor to individual elementauto attachment = sbbInputs[index];

gmath::Vec3d affectedPos;affectedPos = mAlgorithm->computePosition(attachment);affectedPos *= attachment.weight();

sbbOutputs[index] = affectedPos;}SBB_ITER_END

SBB_KERNEL_END

auto is your SBB friend

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Used SBB Engine to…

Control code generation (e.g Scalar vs. Simd)

– Control peel or remainder loop generation

– Set number of SIMD lanes

Control threading model (and grain size)

– TBB, OpenMP, or single-threaded

[Example on next slide…]

SBB Integration: Engine

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SBB Integration : Engine (example)

SBB_KERNEL_BEGIN(loop)…

SBB_KERNEL_END

// SBB Enginesbb::Block1dBounds bounds(0, count);sbb::Block1dSize blockSize(16);Engine engine;engine.run(loop, bounds, blockSize);

// Easily switch between Code Strategy (i.e. SIMD vs. non-SIMD)typedef sbb::SimdCode<SimdLaneCount, sbb::BoundsAreSimdAlignedYes> CodeGen;//typedef sbb::VectorCode<SimdLaneCount, sbb::BoundsAreSimdAlignedYes> CodeGen;//typedef sbb::ScalarCode<SimdLaneCount, sbb::BoundsAreSimdAlignedYes> CodeGen;

// Easily switch between SBB Enginestypedef sbb::Tbb1dEngine<CodeGen> Engine;//typedef sbb::SingleThreaded1dEngine<CodeGen> Engine;

typedef’s are useful for debugging and performance tuning

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Array of Structures (AOS)– Ex. std::vector<gmath::Vec3d> A

– Multiple (load, shuffles, or gather) instructions to get data into a vector register

– Possibly access multiple cache lines

Structures of Arrays (SOA)– Ex. struct A {double x[N], y[N], z[N]}

– All ‘x’ is adjacent in memory

– Often, single vector load instruction

AOS vs. SOA

X

A[i+0]

Y Z X

A[i+1]

Y Z X

A[i+2]

Y Z X

A[i+3]

Y Z


AOS in Memory Layout


A

Z[i+0] Z[i+1] Z[i+2] Z[i+3]

Y[i+0] Y[i+1] Y[i+2] Y[i+3]

X[i+0] X[i+1] X[i+2] X[i+3]

SOA in Memory Layout

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Definitely, improves assembly inside a vectorized loop

But, there’s a cost to adding a separate AOS to SOA conversion

– Would likely eat up any improvements

– Could be worth it,

If data is accessed multiple times or by a multi-pass algorithm

Ideally, avoid doing any conversion

– Keep the data as SOA the entire time

Is converting to SOA worthwhile?

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Intel® C++ Composer XE (ICC) can generate SIMD code for us implicitly or explicitly:

– Implicit

Compiler decides its safe to do so and just does it

aka “auto-vectorization”

– Explicit

Programmer declares its safe and/or worthwhile

Ex. “#pragma simd”

Intel® C++ Composer XE (ICC) : Vectorization

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Find and replace ‘size_t’ with ‘int’

– Help avoid 64-bit indexes

– Got rid of “64bit indexed” remarks for a single level of indirection

Resolved opt-report “64bit indexed” remarks

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Results: Vectorization Efficiency

AVX (scalar & vector) gains efficiency due to 3 operand instructions, so more work represented in fewer instructions

Higher is better

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Results: SIMD Speedups

Higher is better

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ICC opt-report

– Diagnostic messages do not always report exact culprit or line number

– Errors and remarks are sometimes vague and ambiguous

– But, ICC continues to improve this in newer versions

Inlined code from several different files

– So it was guesswork, looking at line number of each file for suspect code

Difficulties

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Inlining code can change execution order of math operations – Still correct, but results may differ

Due to floating point rounding differences

Bloated compile time– Enormous size of inlined loop body (likely uncommon)

– Workaround was to separate our several variations of loop into multiple compilation units, to allow parallel compilation

Intel® Advisor XE 2016 with Vectorization Advisor– Was not available at the time

– May have been useful tool for vectorization of this algorithm

Difficulties (Part 2)

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https://software.intel.com/en-us/intel-advisor-xe


Try various instruction sets (SSE4.2, AVX, AVX2).

– May get additional diagnostics

– e.g. AVX2 reported “indirect access” and “64bit indexed” remarks

Try both ‘#pragma simd’ and ‘#pragma vector’ with opt-report’s

– ‘#pragma ivdep’ with ‘#pragma vector’ proved more useful than ‘#pragma simd’

Things To Try When Vectorizing

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Try different compiler versions

– ICC 15 improved formatting over ICC 14

– And sometimes more useful information

If line numbers are vague from opt-report

– Try commenting out lines to isolate culprit line number

– Try commenting out code blocks until it works

E.g. binary search strategy

Things to try when vectorizing (Part 2)

DreamWork Animation DWA

Software

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