Dr. Yi Cao Digital Hardware Designer, RIM (Research In … · Welcome 1 Dr. Yi Cao Digital Hardware...

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Welcome 1 Dr. Yi Cao Digital Hardware Designer, RIM (Research In Motion) Hee-Soo Lee 3D EM Applications Specialist, Agilent EEsof EDA

Transcript of Dr. Yi Cao Digital Hardware Designer, RIM (Research In … · Welcome 1 Dr. Yi Cao Digital Hardware...

Page 1: Dr. Yi Cao Digital Hardware Designer, RIM (Research In … · Welcome 1 Dr. Yi Cao Digital Hardware Designer, RIM (Research In Motion) Hee-Soo Lee 3D EM Applications Specialist, Agilent

Welcome

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Dr. Yi Cao Digital Hardware Designer, RIM (Research In Motion)

Hee-Soo Lee 3D EM Applications Specialist, Agilent EEsof EDA

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The Effect of Digital Noise on RF Receiver Sensitivity in Modern

Smart-Phones Applications

Yi Cao Digital Hardware Designer, Ph.D

HeeSoo LEE

EEsof 3DEM Technical Lead

October 6, 2011 Copyright 2011 © Agilent Technologies

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October 6, 2011 Copyright 2011 © Agilent Technologies

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Agenda

Review of EMI/EMC basic definitions Modern Smart phones and its design challenges Investigation of digital-to-RF interference via EM simulations A case study: Digital noise on Wi-Fi receiver sensitivity Conclusion

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Quick Review on EMI/EMC Definitions

EMI (Electro-magnetic Interference):

• Electromagnetic emissions from a device or system that cause another device or system to behave in an undesired manner, also referred to as Radio Frequency Interference (RFI)

EMC (Electro-magnetic Compatibility):

• The ability of a device or system to function satisfactorily in its electromagnetic environment with other electronic systems and not produce or be susceptible to interference

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Two Types of Interferences

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Source (Culprit, emitter)

Receptor (Victim,

Receiver) Transfer

(Coupling Path)

Conducted

Radiated

• Power Lines • Signal Lines

• Magnetic • Electric • Planewave

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Why EMI/EMC becomes more important?

Increasing complexity and integration of electronic systems cause more issues with EMI/EMC • Smaller and lower-power devices • Increasing clock frequencies, faster slew rate • Increasing packaging density Increasing product weight and cost pressure • Increased use of lower cost material • Decreased use of good shielding due to lighter product designs Physically debugging EMI/EMC issues in reverberant or anechoic chambers is time-consuming and costly

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Common Characteristics of Modern Smart Phones

Very small form factor • More compact/slim PCB

High trace routing density

Ever increasing clock speed and data rate • DDR, HDMI, USB 3, SATA etc.

Complex multi-band and multi-mode designs • WIFI, BT, GPS, GSM, UMTS, LTE etc.

Mixed RF/Analog and high-speed digital contents

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Design Challenges of Smart Phones for EMI Compliance

Increased digital to RF interference • Need to isolate digital and RF circuits from each other • Need to mitigate digital to RF noise interference Increased shared grounds • Limited number of ground layers available on board Smaller grounding area

Increased proximity effects

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Problem Statement

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“When the device is turned on and loading contents (involving CPU and DDR together), the Wi-Fi receiver sensitivity is affected!”

Wi-Fi Ant

Bluetooth

PCB

CPU

DDR

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Understanding DDR2 Clock Signal in Frequency and Time Domain

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Clock Frequency : 266MHz

Data Rate : 533Mbps

Clock contains high frequency components around 2.45GHz, which may act as the noise source

Clock Signal Spectrum

f

p

t

v

Rise/Fall: 0.31ns and 0.26ns respectively

DDR CLK

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EM Simulation Technologies

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• Frequency Domain EM • 3D Planar structures • Full Wave and Quasi-Static • Dense & Compressed Solvers • Multiport simulation at no

additional cost • High Q

• Frequency Domain EM • 3D Arbitrary Structures • Full Wave EM

Simulation • Direct, Iterative Solvers • Multiport simulation at

no additional cost • High Q

• Time Domain EM • 3D arbitrary structures • Full Wave EM simulations • Handles much larger and complex problems • Simulate full size cell phone antennas • EM simulations per each port • GPU based hardware acceleration

FDTD (Finite Difference Time Domain)

FEM (Finite Element Method)

MoM (Method of Moments)

Best for EMI/EMC problems

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EMPro FDTD Technology

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t1

t2

t3

Full 3D, Time Domain Preparing a 3D structure: • Complete simulation domain

segmented using E and H fields as unknowns

• Boundary conditions to truncate simulation domain

Time stepping algorithm • Alternating update of E and H field at

each mesh cell, progressing in time until steady state time domain is reached

• No matrix solve • Use FFT to obtain broadband S-

parameters

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Faster FDTD Simulation with GPU Acceleration

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Simulation is multi-threaded on GPU cores The speedup scales with # of GPU cards used 3~40 times typical simulation speed improvement

GPU CPU

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EM simulation Approaches to EMI Perform S-parameter analysis with a broadband source at locations of suspected EMI sources and receptors • Understand the frequency selectivity of PCB across broad

frequency range

Find hot spots on PCB layers at the frequency of interest • Pinpoint the areas for de-coupling capacitor locations and potential

noise coupling path

Perform time-domain analysis with an actual digital CLK • Understand the time-domain noise builds-up as time progresses

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Approach 1: Network (S-parameter) Analysis

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High frequency component of DDR clock noise may interfere with Wi-Fi, Bluetooth, and Antenna

S-parameter analysis technique will provide insight on the board’s frequency selectivity to DDR noise

Clock Signal (Broadband Input)

f

p

PCB Structure (Network)

f

p

Board ‘s Frequency Selectivity Response

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Detailed S-parameter (Network) Analysis Setup

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Clock Signal (Broadband Input)

f

p PCB Structure

(Network)

f

p Board’s Frequency Selectivity Response Wi-Fi Ant

Bluetooth

PCB

CPU

DDR

Apply 50-ohm load for collecting S-parameter

Apply a broadband source

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Adding De-Caps Approach 2: Hot Spot Analysis

Find hot spots

Place de-caps

This example is from the paper, “Using CUDA Enabled FDTD Simulations To Solve Multi-Gigahertz EMI Challenges” by Davy Pissoort, Cheng Wang, Hany Fahany, and Amolak Badesha

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Approach 3: Time-Domain Analysis with Differential Clock Signals

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Excite the differential line at CPU BGA balls for DDR2 directly with time domain clock signal to understand time-domain behavior of PCB

CPU

DDR

Time-Domain

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Result of Network Analysis: DDR to RF

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Network analysis can reveal the board’s frequency susceptibility to DDR noise

Network’s frequency susceptibility

Plot Legend Light Green : Wi-Fi Magenta : RF Ant Dotted Blue : Bluetooth

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Networks’ (PCB Board) Frequency Selectivity

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The frequency response of DDR2 to Wi-Fi, BT, and RF Ant proves the clock noise couples more to Wi-Fi than others

Wi-Fi

BT

Ant

10+ dB

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Results of Hot Spot Analysis

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Hot Spots Performed single frequency steady state analysis, which was at 2.45GHz Various planar sensors were located on different PCB layers Plot and investigate the conduction currents from the planar sensors for any hot spots

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Result of Time Domain Simulation

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Noise voltages are time-dependent and keep increasing due to multiple paths available for coupling

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Possible Approaches for EMI Reduction

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Shielding/grounding improvement for reduced radiation

De-coupling capacitor placement

Apply advanced packaging technology such as PoP (Package on Package) that combines CPU and DDR in a single package

PCB

Processor

Memory

Courtesy of TI

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Effect of Shielding on Radiation at 2.45GHz

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Proper shielding could reduces the radiation approximately 3.8dB

Radiation Plot Without Shielding

Radiation Plot With Shielding

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Effect of Shielding on Radiation at 2.45GHz

Azimuth Cut Radiation Plot

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Radiation Plot Without Shielding

Radiation Plot With Shielding

Direction of Reduction

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Effects of De-caps on Hot Spots

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Without De-caps placement

With De-caps placement

Reduced Hot Spots

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Effect of De-caps on Radiation at 2.45GHz

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De-caps could reduces the radiation approximately 1.5 dB

Radiation Plot Without De-caps

Radiation Plot With De-caps

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Conclusion

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Digital signal (including clocks) noise to RF may reduce the receiver’s sensitivity unexpectedly

PCB’s network analysis through EM simulations provides a great insight and potential ways to reduce digital to RF noise coupling

With a proper shielding and the use of de-caps, EMI can be significantly reduced, for example, 5dB as shown in this case study

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Acknowledgement

Author Yi Cao thanks the management at RIM (Jack Idzik and Rick Brogle) in supporting this work

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Q&A

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Yi Cao Digital Hardware Designer, Ph.D

HeeSoo LEE

EEsof 3DEM Technical Lead

[email protected]

[email protected]

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Want More Information on Agilent EM Solutions? Available from www.agilent.com/find/eesof-empro

• Overview video and brochure

• Archived webcasts

• EMPro Workshop & Getting Started Videos

5 minute overview video on YouTube

8 page color brochure

Webcast on 3D EM flow

Webcast on EM for SI apps

EMPro Workshop Slides and lab projects

Webcast: “Which EM Solver Should I Use?

Getting Started Videos Nine videos covering 3D drawing, FEM simulation, FDTD simulation, Python scripting, etc

31 October 6, 2011 Copyright 2011 © Agilent Technologies

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You are invited

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You can find more webcasts www.agilent.com/find/eesof-innovations-in-eda www.agilent.com/find/eesof-webcasts-recorded Andy Howard

Senior Applications Engineer Agilent EEsof