DR. SAIBAL MUKHOPADHYAY ASSOCIATE PROFESSOR SCHOOL...

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DR. SAIBAL MUKHOPADHYAY ASSOCIATE PROFESSOR

SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING, GEORGIA TECH

I. EARNED DEGREES

PhD (August, 2006) Electrical & Computer Engineering, Purdue University, West Lafayette, USA

B.E. (June, 2000) Electronics & Telecommunication Engineering, Jadavpur University, India

II. EMPLOYMENT HISTORY

July 2016-present Professor, Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta, GA

July 2012-June 2016 Associate Professor, Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta, GA

Sept. 2007-June 2012 Assistant Professor, Electrical & Computer Engineering, Georgia Institute of Technology, Atlanta, GA

Sept. 2006-Sept. 2007 Research Staff Member, High Performance Circuit Design Dept. IBM T. J. Watson Research Center, Yorktown Heights, NY

Aug. 2001-July 2006 Graduate Teaching and Research Assistant, Electrical & Computer Engineering, Purdue University, West Lafayette, IN, USA

Summers: 2003, 2004, and 2005

Technical Co-op, High Performance Circuit Design Dept. IBM T. J. Watson Research Center, Yorktown Heights, NY

III. HONORS AND AWARDS

A. International and National Awards

• Best Paper Award, 2016 IEEE International Symposium on Low Power Electronic Design (ISLPED), August 2016.

• Best Student Paper Award, 2016 IEEE S3S Conference, Oct. 2016. • Best in Session Award at SRC TECHCON 2015, Sept. 2015. • Best Paper Award, 2015 IEEE International Symposium on Low Power Electronic Design (ISLPED),

July 2015. • Best Student Paper Award, 2015 IEEE Reliability Physics Symposium (IRPS), April 2015. • Three Best in Session Awards at SRC TECHCON 2014, October 2014. • Best Paper Award, 2014 IEEE International Symposium on Low Power Electronic Design (ISLPED),

August 2014. • Best Paper Award, IEEE Transactions on VLSI Systems (TVLSI), July 2014. • Best Paper Award, IEEE Transactions on Component, Packaging, and Manufacturing Technology

(TCPMT) in Component and Characterization Category, April 2014.

October 2015 Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech

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• Honorable Mention in Best Paper Selection, 2014 IEEE SemiTherm, March 2014. • Office of Naval Research (ONR) Young Investigator Award, 2012 • National Science Foundation CAREER Award, 2011. • IBM Faculty Award, 2010. • IBM Faculty Award, 2009. • Semiconductor Research Corporation (SRC) Inventor Recognition Award, 2008. • SRC Technical Excellence Award as a member of the Purdue Research Team, 2005. • Best in Session Award at SRC TECHCON 2005. • Best Paper Award, 2004 International Conference on Computer Design. • Best Student Paper Award, 2003 IEEE Nano. • Dr. B. C. Roy Memorial Gold Medal for standing 1st among approx. 600 students in the Faculty of

Engineering & Technology, Jadavpur University, India, 2000.

B. Institute or School Awards

• Class of 1934 Course Survey Teaching Effectiveness Award 2014 • Class of 1934 Course Survey Teaching Effectiveness Awards 2012 • ECE Outstanding Junior Faculty Member Award, 2012

IV. RESEARCH, SCHOLARSHIP, AND CREATIVE ACTIVITIES

A. PUBLISHED BOOKS, BOOK CHAPTERS, AND EDITED VOLUMES

A1. Books No data

A2. Refereed Book Chapters 1. A. Agarwal, S. Mukhopadhyay, C. H. Kim, A. Raychowdhury, and K. Roy, “Leakage power

analysis and reduction for nano-scale circuits,” in System-on-Chip: Next Generation Electronics, Edited by Bashir M. Al-Hashimi, IET, May 2006, pp. 415-444.

A3. Edited Volumes 1. “Low-power Variation-Tolerant Design in Nanometer Silicon” Co-edited by S. Bhunia and S.

Mukhopadhyay, Springer, published Nov. 2010.

B. REFEREED PUBLICATIONS AND SUBMITTED ARTICLES

*Boldface font is used to identify co-authors who were students being advised by Prof. Mukhopadhyay. *Citation counts are obtained from Google Scholar search, August 2015.

B1. Published and Accepted Journal Articles

♦ 2017

1. J.H. Ko, K. Z. Ahmed, M. F. Amir, T. Na, and S. Mukhopadhyay, “A Single-Chip Image Sensor Node with Energy Harvesting from CMOS Pixel Array" accepted for publication in IEEE Transactions of Circuits and Systems – Regular Papers (TCAS-I).


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2. T. Na, J. H. Ko, and S. Mukhopadhyay, “Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction" accepted for publication in IEEE Transactions of Circuits and Systems – Regular Papers (TCAS-I).

3. M. Kar, A. Singh, A. Rajan, V. De, and S. Mukhopadhyay, “An All-Digital Fully Integrated Inductive Buck Regulator with A 250MHz Multisampled Compensator and A Lightweight Auto-Tuner in 130nm CMOS,” accepted for publication in IEEE Journal of Solid State Circuits (JSSC).

4. D. Kim, J. H. Kung, and S. Mukhopadhyay, “A Power-Aware Digital Multilayer Perceptron Accelerator with On-Chip Training based on Approximate Computing,” accepted for publication in IEEE Transactions on Emerging Topics in Computing (IEEE TETC).

♦ 2016

5. W. Yueh, Z. Wan, Y. Joshi, and S. Mukhopadhyay, “Design, Characterization, and Application of a Field Programmable Thermal Emulation Platform”, IEEE Transactions on Component, Packaging, and Manufacturing Technology, vol. 6, no. 9, Sept. 2016, pp. 1330-1339.

6. H. Xiao, W. Yueh, S. Mukhopadhyay and S. Yalamanchili, “Thermally Adaptive Cache Access Mechanisms for 3D Many-core Architectures”, IEEE Computer Architecture Letters, vol. 15, no. 2, July-Dec. 1 2016, pp. 129-132.

7. M. F. Amir, A. Trivedi, and S. Mukhopadhyay, “Exploration of Si/Ge Tunnel FET Bit Cells for Ultra-low Power Embedded Memory,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 6, no. 2, June 2016, pp. 185-197.

8. D. Lie, A. Trivedi, and S. Mukhopadhyay, “Impact of Heterogeneous Technology Integration on the Power, Performance, and Quality of a 3D Image Sensor,” IEEE Transactions on Multi-Scale Computing Systems, Vol. 2, No. 1, Jan-March, 2016, pp. 61-67./

9. D. Kim, and S. Mukhopadhyay, “On the Design of Interface Circuit for Heterogeneous System in 3D-IC under Process Variation,” IEEE Transactions on VLSI Systems, vol. 24, no. 5, May 2016, pp. 1626-1635.

10. S. Carlo, and S. Mukhopadhyay, “A High Power Density, Dynamic Voltage Scaling Compatible, Single-Inductor Four-Output Regulator using a Power-Weighted CCM Controller and a Floating Capacitor-Based Output Filter,” IEEE Transactions on Power Electronics (TPE), Vol.31, No.6, June 2016, pp. 4252-4264.

11. M. Kar, K. Z. Ahmed, and S. Mukhopadhyay, “A Scalable Hybrid Regulator For Down Conversion of High Input Voltage Using Low Voltage Devices,” IEEE Transactions on Power Electronics (TPE), Vol.31, No.3, March 2016, pp.1857-1862.

12. K. Z. Ahmed and S. Mukhopadhyay, “A 190nA Bias Current 10mV Input Multi-Stage Boost Regulator with Intermediate Node Control to Supply RF Blocks in Self-powered Wireless Sensors,” IEEE Transaction on Power Electronics (TPE), Vol. 31, No. 2, Feb. 2016, pp. 1322-1333.

♦ 2015

13. W. Song, S. Mukhopadhyay, and S. Yalamanchili, “Architectural Reliability: Lifetime Reliability Characterization and Management of Many-Core Processors,” IEEE Computer Architecture Letters (CAL), Vol. 14, No. 2, Dec. 2015, pp. 103-106.

14. W. Song, S. Mukhopadhyay, and S. Yalamanchili, “KitFox: Multi-Physics Libraries for Integrated Power, Thermal, and Reliability Simulations of Multicore Microarchitecture,” IEEE Transactions on Component, Packaging and Manufacturing Technology, Vol.5, No.11, Nov. 2015, pp.1590-1601.

15. D. Manatunga, H. Kim, and S. Mukhopadhyay, “SP-CNN: A Scalable and Programmable CNN-based Accelerator,” IEEE Micro. Vol. 35, No. 5, Sept-Oct 2015, pp. 42-50.


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16. J. H. Ko, B. Muhammad, and S. Mukhopadhyay, “An Energy-Efficient Wireless Video Sensor Node for Moving Object Surveillance,” IEEE Transactions on Multi-Scale Computing Systems, Vol. 1, No. 1, Sept. 2015, pp. 7-18.

17. J. Kung, D. Kim, and S. Mukhopadhyay, “On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing,” IEEE Transactions on Computer Aided Design (TCAD), vol. 34, no. 7, July 2015, pp. 1070-1081.

18. W. Yueh, S. Chatterjee, M. Zia, S. Bhunia, and S. Mukhopadhyay, “A Memory-Based Logic Block with Optimized-for-Read SRAM for Energy-efficient Reconfigurable Computing Fabric,” IEEE Trans. on Circuits and Systems –II (TCAS-II), vol.62, no.6, June 2015, pp.593-597.

19. J. Kung, W. Yueh, S. Yalamanchili, and S. Mukhopadhyay, “Post-silicon Estimation of Spatiotemporal Temperature Variations Using MIMO Thermal Filters,” IEEE Transactions on Component, Packaging, and Manufacturing Technology (TCPMT), vol.5, no.5, May 2015, pp.650 – 660.

20. K. Roy, D. Fan, X. Fong, M. Sharad, S. Paul, S. Chatterjee, S. Bhunia, and S. Mukhopadhyay, “Exploring Spin Transfer Torque Devices for Unconventional Computing,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol.5, no.1, pp. 5-16, March 2015 (Review paper in special issue).

21. A. Trivedi, K. Z. Ahmed, and S. Mukhopadhyay, “Negative Gate Transconductance in Gate/Source Overlapped Heterojunction Tunnel FET and application to Single Transistor Phase Encoder,” IEEE Electron Device Letters (EDL), vol. 36, no. 2, Feb. 2015, pp. 201-203.

♦ 2014

22. S. Paul, S. Mukhopadhyay, S. Bhunia, “A Variation-Aware Preferential Design Approach for Memory Based Reconfigurable Computing,” IEEE Transactions on VLSI (TVLSI), vol. 22, no. 12, Nov. 2014, pp. 2449-2461.

23. A. Trivedi, S. Datta, and S. Mukhopadhyay, “Application of Silicon-Germanium Source Tunnel-FET to enable Ultra-low power Cellular Neural Network based Associative Memory,” IEEE Transactions on Electron Devices (TED), vol. 61, no. 11, Nov. 2014, pp. 3707-3715.

24. D. H. Kim, S. Mukhopadhyay, and S. Lim, “TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3D Stacked ICs,” IEEE Transactions on Computer Aided Design, vol. 33, no. 9, Sept. 2014, pp. 1384-1395.

25. B. Alexandrov, O. Sullivan, W. Song, S. Yalamanchili, S. Kumar, and S. Mukhopadhyay, “Control Principles and On-chip Circuits for Active Cooling using Integrated Super Lattice Based Thin-Film Thermoelectric Devices,” IEEE Transactions on VLSI Systems (TVLSI), vol. 22, no. 9, September 2014, pp. 1909-1919.

26. K. Z. Ahmed, and S. Mukhopadhyay, “A wide conversion ratio, extended input 3.5µA Boost Regulator with 82% Efficiency for Low Voltage Energy Harvesting,” IEEE Transactions on Power Electronics, vol.29, no.9, Sept. 2014, pp. 4776-4786.

27. A. Trivedi and S. Mukhopadhyay, “Potential of Ultra-low-power Image Proecssing with Si/Ge Tunneling Nanowires based Cellular Neural Network,” IEEE Transactions on Nanotechnology, vol. 13, no. 4, July 2014, pp. 627-629. The top most accessed article in TNANO in every month from August, 2014 to February, 2015.

28. A. Trivedi and S. Mukhopadhyay, “In-situ Power Gating Efficiency Learner for Fine-Grain Self Adaptive Power Gating,” IEEE Transactions on Circuits and Systems – II (TCAS-II), vol.61, no.5, May 2014, pp. 344 – 348.


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29. A. Trivedi, T. Ando, A. Singhee, P. Kerber, E. Acar, D. J. Frank, and S. Mukhopadhyay, “A Simulation Study of Oxygen Vacancy induced Variability in HfO2/Metal Gated SOI FinFET,” IEEE Transactions on Electron Devices (TED), vol.61, no.5, May 2014, pp.1262-1269.

30. K. Chae, and S. Mukhopadhyay, “Resilient Pipeline under Supply Noise with Programmable-Time-Borrowing and Delayed-Clock-Gating,” IEEE Transactions on Circuits and Systems – II (TCAS-II), vol.61, no.3, pp.173-177, March 2014.

31. D. Lie, K. Chae, and S. Mukhopadhyay, “Analysis of the Performance, Power, and Noise Characteristics of a CMOS Image Sensor with 3D Integrated Image Compression Unit,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies (TCPMT), vol. 4, no.2, Feb. 2014, pp.198-208.

32. K. Chae and S. Mukhopadhyay, “A Dynamic Timing Error Prevention Technique with Time Borrowing and Clock Stretching to Widen Operating Range of Pipelines,” IEEE Transactions of Circuits and Systems (TCAS-I), vol.61, no.1, Jan. 2014, pp.74-83.

33. M. Cho, K. Z. Ahmed, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Post-Silicon Characterization and On-Line Prediction of Transient Thermal Field in Integrated Circuits Using Thermal System Identification," IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), vol.4, no.1, Jan. 2014, pp.37-45.

♦ 2013

34. K. Chae, X. Zhao, S. Lim, and S. Mukhopadhyay, “Tier-Adaptive-Body-Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3D ICs,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies (TCPMT), vol.3, no.10, Oct. 2013, pp.1720-1730.

35. O. Sullivan, B. Alexandrov, S. Mukhopadhyay, and S. Kumar, “3D Compact Model of Packaged Thermoelectric Coolers,” ASME Journal of Electronic Packaging (JEP), vol. 135, no. 3, June 2013, pp. 031006-031006-7.

36. W. Yueh, S. Chatterjee, A. Trivedi, and S. Mukhopadhyay, “Performance and Robustness of 3D Integrated SRAM Considering Tier-to-tier Thermal and Supply Cross-talk,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies (TCPMT), vol. 3, no.6, June 2013, pp. 943-953.

37. M. Redmond, K. Manickaraj, O. Sullivan, S. Mukhopadhyay, and S. Kumar, “Hotspot Cooling in Stacked Chips using Thermoelectric Coolers,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies (TCPMT), vol.3, no.5, May 2013, pp.759-767.

38. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Electro-Thermal Analysis of Spin-Torque-Transfer Random Access Memory Arrays,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 9, No. 2, Article 15 (17 pages), May 2013.

39. M. Cho, C. Kersey, M. P. Gupta, N. Sathe, S. Kumar, S. Yalamanchili, and S. Mukhopadhyay, “Power Multiplexing for Thermal Field Management in Many Core Processors,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies (TCPMT), vol. 3, no. 1, January 2013, pp. 94-104. Received IEEE TCPMT Best Paper Award, 2014.

♦ 2012

40. K. Chae, and S. Mukhopadhyay, “All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in Low Voltage Operation,” IEEE Transactions on Circuits and Systems-II: Express Briefs (TCAS-II), vol. 59, no. 2, December 2012, pp. 893 - 897.

41. S. Narasimha, W. Yueh, X. Wang, S. Mukhopadhyay, and S. Bhunia, “Improving IC Security against Trojan Attacks through Integration of Security Monitors”, IEEE Design and Test of Computers (IEEE D&T), vol. 29, no. 5, October 2012, pp. 37-46.


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42. X. Zhao, J. R. Tolbert, C. Liu, S. Mukhopadhyay, and S. K. Lim, “Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 8, August 2012, pp. 1222-1234.

43. O. Sullivan, M. P. Gupta, S. Mukhopadhyay, and S. Kumar, “Array of Thermoelectric Coolers for On chip Thermal Management,” ASME Journal of Electronic Packaging. vol. 134, no. 6, June 2012, pp. 021005-021005-8.

44. M. P. Gupta, M. Cho, S. Mukhopadhyay, and S. Kumar, “Thermal Investigation into Power Multiplexing for Homogeneous Many-Core Processors,” ASME Journal of Heat Transfer, vol. 134, No. 6, June 2012, 061401-061401-8.

45. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Impact of Self-Heating on Reliability of Spin-Torque-Transfer RAM Cell,” IEEE Transactions on Electron Devices (TED), Vol. 59, No. 3, March 2012, pp. 791-799.

46. J. Tolbert, P. Kabali, S. Brar, and S. Mukhopadhyay, “Designing for Accuracy and Energy Efficiency in Wireless Encephalography Systems,” ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 8, no. 1, February 2012, pp. 1-21.

♦ 2011

47. M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, “Pre-bond and Post-bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System,” IEEE Transactions on Components, Packaging and Manufacturing (TCPMT), vol. 1, no. 11, Nov. 2011, pp. 1718-1727. Number of citations 28.

48. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, “Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS). vol. 1, no. 3, Sept. 2011, pp. 369-380.

49. J. R. Tolbert, X. Zhao, S. K. Lim, and S. Mukhopadhyay, “Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems,” IEEE Transaction on Computer Aided Design (TCAD), vol. 30, no. 9, Sept. 2011, pp. 1348-1358.

50. M. Gupta, M. Sayer, S. Mukhopadhyay, and S. Kumar, "Ultrathin Thermoelectric Devices For On-Chip Peltier Cooling,” IEEE Transactions on Components, Packaging, and Manufacturing Technologies (TCPMT), vol. 30, no. 9, Sept. 2011, pp. 1395-1405.

51. A. R. Trivedi and S. Mukhopadhyay, “Through-Oxide-Via Induced Back Gate Effect in 3D Integrated FDSOI Devices,” IEEE Electron Device Letters (EDL), vol. 32, no. 8, Aug. 2011, pp. 1020-1022.

52. S. Kim, S. Mukhopadhyay, and M. Wolf, “Modeling and Analysis of Image Dependence and Its Implications for Energy Saving for Error Tolerant Image Processing,” IEEE Transactions on Computer Aided Design (TCAD), vol. 30, no. 8, Aug. 2011, pp. 1163-1172 (Top 20 downloaded article in TCAD in 2012).

53. S. Chatterjee, M. Rasquinha, S. Yalamanchili, and S. Mukhopadhyay, “A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective,” IEEE Transactions on VLSI Systems (TVLSI), vol. 19, no. 5, May 2011, pp. 809-817. Received IEEE TVLSI Best Paper Award in 2014.

54. S. Paul, S. Mukhopadhyay, and S. Bhunia, “Circuit and Architecture Co-design Approach for Hybrid CMOS-STTRAM non-volatile FPGA,” IEEE Transactions on Nanotechnology (TNANO), vol. 10, no. 3, May 2011, pp. 385-394.

55. D. H. Kim, S. Mukhopadhyay, and S. K. Lim, “Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling,” IEEE Transactions on Components, Packaging, and Manufacturing Technology (TCPMT), vol. 1, no. 2, Feb. 2011, pp. 168-180.


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56. S. Mukhopadhyay, R. Rao, J.J. Kim, and C. T. Chuang, “SRAM Write-ability Improvement with Transient Negative Bit-line Voltage,” IEEE Transactions on VLSI Systems (TVLSI), vol. 19, no. 1, Jan. 2011, pp. 24-32.

57. M. Cho, J. Schlessman, W. Wolf, and S. Mukhopadhyay, “Reconfigurable SRAM Architecture with Spatial Voltage Scaling for Low Power Mobile Multimedia Applications,” IEEE Transactions on VLSI Systems (TVLSI), vol. 19, no. 1, Jan. 2011, pp. 161-165. Number of citations 12.

♦ 2010

58. M. Cho, J. Schlessman, H. Mahmoodi, M. Wolf, and S. Mukhopadhyay, “Postsilicon Adaptation for Low-Power SRAM under Process Variation,” IEEE Design and Test of Computers (D&T), vol. 27, no. 6, Nov.-Dec. 2010, pp. 26–35.

59. S. Kim, S. Mukhopadhyay, and M. Wolf, “System Level Energy Optimization for Error tolerant Image Compression,” IEEE Embedded System Letters (ESL), vol. 2, no. 3, Sept. 2010, pp. 81–84.

60. S. Chatterjee, S. Salahuddin, and S. Mukhopadhyay, “Dual Source-Line-Bias Scheme to Improve Read Margin and Sensing Accuracy of STTRAM in sub-90nm Nodes,” IEEE Transactions on Circuits and Systems- II (TCAS-II), vol. 57, no. 3, Mar 2010, pp. 208-212.

61. N. N. Mojumder, S. Mukhopadhyay, J. J. Kim, C. T. Chuang, and K. Roy, “Self-Repairing SRAM using On-Chip Detection and Compensation,” IEEE Transactions on VLSI Systems (TVLSI), vol. 18, no. 1, Jan 2010, pp. 75-84.

♦ 2009

62. S. Mukhopadhyay, “A Generic Data-Driven Non-Parametric Framework for Variability Analysis of Integrated Circuits in Nanometer Technologies,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 28, no. 7, July 2009, pp. 1038-1046.

63. R. Joshi, S. Mukhopadhyay, D. W. Plass, Y. H. Chan, C. T. Chuang, and Y. Tan “Design of sub-90nm Low power and Variation tolerant PDSOI SRAM cell based on dynamic stability metrics,” IEEE Journal of Solid State Circuits (JSSC), vol. 44, no. 3, Mar. 2009, pp. 965-976.

♦ 2008

64. S. Mukhopadhyay, K. Kim, K. A. Jenkins, C. T. Chuang, and K. Roy, “An On-chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process,” IEEE Journal of Solid State Circuits (JSSC), vol. 43, no. 9, Sept. 2008, pp. 1951–1963.

65. A. Datta, S. Bhunia, J. H. Choi, S. Mukhopadhyay, and K. Roy, “Profit Aware Circuit Design under Process Variations Considering Speed Binning,” IEEE Transactions on VLSI System (TVLSI), vol. 16, no. 7, July 2008, pp. 806-815.

66. A. Bansal, K. Kim, J. J. Kim, S. Mukhopadhyay, C. T. Chuang, and K. Roy, “Optimal Dual-VT Design in Sub-100 Nanometer PD/SOI and Double-Gate Technologies,” IEEE Transactions on Electron Devices (TED), vol. 55, no. 5, May 2008, pp. 1161-1169 .

67. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Reduction of Parametric Failures in Sub-100nm SRAM Array using Body Bias,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 21, no. 1, Jan. 2008, pp. 174-183 (Top 20 downloaded article in TCAD in 2008).

68. S. Mukhopadhyay, K. Kim, and C. T Chuang, “Device Design and Optimization Methodology for Leakage and Variability Reduction in sub-50nm FD/SOI SRAM,” IEEE Transactions on Electron Devices (TED), vol. 55, no. 1, Jan. 2008, pp. 152-162. Considered for IEEE Electron Device Society’s 2008 Paul Rappaport Award given to the best paper in IEEE TED – selected as top 1% of all papers submitted to TED in 2008.

♦ 2007


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69. S. Mukhopadhyay, K. Kim, J. J. Kim, S. Lo, R. Joshi, C. T. Chuang, and K. Roy, “Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits,” Microelectronics Journal, vol. 38, no. 8-9, Aug.-Sept. 2007. pp. 931-941.

70. A. Bansal, S. Mukhopadhyay, and K. Roy, “Device-optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era,” IEEE Transactions on Electron Devices (TED), vol. 54, no. 6, June 2007, pp. 1409-1419.

71. S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, “Design of A Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nano-scaled CMOS,” IEEE Journal of Solid-State Circuits (JSSC), vol. 42, no. 6, June 2007, pp. 1370–1382 (citations 74).

♦ 2006

72. A. Datta, S. Bhunia, S. Mukhopadhyay, and, K. Roy, “Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 11, Nov. 2006, pp. 2427-2436.

73. S. Mukhopadhyay, K. Kim, C. T. Chuang, and K. Roy, “Modeling and Analysis of Leakage Currents in Double-Gate Technologies,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 10, Oct. 2006, pp. 2052-2061.

74. S. Mukhopadhyay, S. Bhunia, and K. Roy, “Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 25, no. 8, Aug. 2006, pp. 1486-1495.

75. S. Mukhopadhyay, K. Kim, X. Wang, D. J. Frank, P. Oldiges, C. T. Chuang, and K. Roy, “Optimal Ultra-Thin Body FD/SOI Device Structure using Thin-BOX for sub-50 nm SRAM Design,” IEEE Electron Device Letters (EDL), vol. 27, no. 4, April 2006, pp. 284-287.

76. A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. H. Kim, “Leakage Power Analysis and Reduction for Nanoscale Circuits,” IEEE Micro, vol. 26, no. 2, Mar.-Apr. 2006, pp. 68-80.

77. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Design of High Performance Sense Amplifier Using Independent Gate Control in Fully Depleted Double-Gate MOSFET,” IEEE Transactions on VLSI Systems (TVLSI), vol. 14, no. 2, Mar. 2006, pp. 183-192.

♦ 2005

78. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nano-Scaled CMOS,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 12, Dec. 2005, pp. 1859-1880 (citations 364, Top 20 downloaded article in TCAD in 2008, 2009, 2012).

79. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Estimation of Delay Variation Due to Random Dopant Fluctuations in Nano-scale CMOS Circuits,” IEEE Journal of Solid State Circuits (JSSC), vol. 40, no. 9, Sept. 2005, pp. 1787-1796 (citations 121).

80. A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, “Process Variation in Embedded Memories: Failure Analysis and Process Tolerant Architecture,” IEEE Journal of Solid State Circuits (JSSC), vol. 40, no. 9, Sept. 2005, pp. 1804-1814 (citations 143).

81. A. Agarwal, S. Mukhopadhyay, C. H. Kim, A. Raychowdhury, and K. Roy, “Leakage Power Analysis and Reduction: Models, Estimation and Tools,” IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 3, May 2005, pp. 353-368.

82. S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low-Power Scan Design Using First Level Supply Gating,” IEEE Transactions on VLSI Systems (TVLSI), vol. 13, no. 3, Mar. 2005, pp. 384- 395.


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83. C. H. Kim, J. J. Kim, S. Mukhopadhyay, and K. Roy, “A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations,” IEEE Transactions on VLSI Systems (TVLSI), vol. 13, no. 3, Mar. 2005, pp. 349-357.

84. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate estimation of total leakage in nanometer scale bulk-CMOS circuits based on device geometry and doping profile,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 3, Feb. 2005, pp. 363-381. One of the Top 20 downloaded papers in 2005 in TCAD (citations 85).

♦ 2004

85. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A circuit-compatible model of ballistic carbon nanotube field-effect transistors,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 23, no. 10, Oct. 2004, pp. 1410-1420. One of the Top 20 downloaded papers in 2004 in TCAD (citations 176).

♦ 2003

86. S. Mukhopadhyay, C. Neau, T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, “Gate leakage reduction for scaled devices using transistor stacking,” IEEE Transactions on VLSI Systems (TVLSI), vol. 11, no. 4, Aug. 2003, pp. 716-730 (citations 126).

87. K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits,” Proceeding of IEEE, vol. 91, no. 2, Feb. 2003, pp. 307-327 (citations 1645).

♦ 2002

88. K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage Current in Deep-Submicron CMOS Circuits,” Journal of Circuits, Systems and Computers, vol. 11, no. 6, Dec. 2002, pp. 575-600.

B2. Conference Presentations with Proceedings (Refereed) ♦ 2017

1. J. Kung, Y. Long, D. Kim, and S. Mukhopadhyay, “A Programmable Hardware Accelerator for Simulating Dynamical Systems,” IEEE International Symposium on Computer Architecture (ISCA), 2017.

2. J. H. Ko, T. Na, and S. Mukhopadhyay, “Design of An Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation,” Design Automation Conference (DAC), 2017.

3. T. Na, J. H. Ko, J. Kung, and S. Mukhopadhyay, “On-Chip Training of Recurrent Neural Networks with Limited Numerical Precision,” International Joint Conference on Neural Network (IJCNN), May 2017.

4. J. H. Ko, and S. Mukhopadhyay, “A Low-Power Wireless Image Sensor Node with Noise-Robust Moving Object Detection and a Region-of-Interest Based Rate Controller,” 42th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech 2017).

5. J. Kung, Y. Long, D. Kim, and S. Mukhopadhyay, “An Energy-Efficient Physical Platform for Solving Differential Equations,” 42th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech 2017).

6. A. Trivedi, and S. Mukhoapdhyay, “CMOS-based Stochastically Spiking Neural Network for Optimization under Uncertainties,” 42th Annual Government Microcircuit Applications and Critical Technology Conference (GOMACTech 2017).


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7. J. H. Ko, D. Kim, T. Na, J. Kung, and S. Mukhopadhyay, "Adaptive Weight Compression for Memory-Efficient Neural Networks,” Design, Automation, and Test in Europe (DATE 2017).

8. T. Na, J. H. Ko, and S. Mukhopadhyay, "Clock Data Compensation Aware Clock Tree Synthesis in Digital Circuits with Adaptive Clock Generation,” Design, Automation, and Test in Europe (DATE 2017).

9. M. Kar, A. Singh, S. Mathew, A. Rajan, V. De, and S. Mukhopadhyay, “Improved Power Side-Channel Attack Resistance of an AES-128 Core via a Security-Aware Integrated Buck Voltage Regulator,” International Solid State Circuit Conference (ISSCC), 2017.

♦ 2016

10. J. Kung, Y. Long, and S. Mukhopadhyay, “An Energy-Efficient Physical Platform for Solving Differential Equations,” International Workshop on Post-Moore's Era Supercomputing (PMES), 2016.

11. K. Z. Ahmed and S. Mukhopadhyay, “A Single-Inductor-Cascaded-Stage Topology for High Conversion Ratio Boost Regulator,” IEEE International Conference on Computer Design (ICCD), 2016.

12. M. Kar, A. Singh, A. Rajan, V. De, and S. Mukhopadhyay, “What does ultra low power requirements mean for side-channel secure cryptography?,” IEEE International Conference on Computer Design (ICCD), 2016.

13. M. F. Amir, D. Kim, J. Kung, D. Lie, S. Yalamanchili, and S. Mukhopadhyay, NeuroSensor: A 3D Image Sensor with Integrated Neural Accelerator, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016. Best Student Paper Award

14. M. Kar, A. Singh, A. Rajan, V. De and S. Mukhopadhyay. “An Integrated Inductive VR with a 250MHz All-Digital Multisampled Compensator and on-Chip Auto-Tuning of Coefficients in 130nm CMOS.” IEEE European Solid State Circuit Conference (ESSCIRC), 2016.

15. K. Z. Ahmed, M. F. Amir, J. H. Ko, and S. Mukhopadhyay, “Reconfigurable 96x128 Active Pixel Sensor with 2.1µW/mm2 Power Generation and Regulated Multidomain Power Delivery for Self-Powered Imaging,” IEEE European Solid State Circuit Conference (ESSCIRC), 2016.

16. J. H. Ko, T. Na, and S. Mukhopadhyay, “An Energy-Efficient Wireless Video Sensor Node with a Region-of-Interest Based Multi-Parameter Rate Controller for Moving Object Surveillance,” 2016 IEEE Advanced Video and Signal-based Surveillance (AVSS 2016), Aug. 2016.

17. M. Kar, A. Singh, S. Mathew, A. Rajan, V. De and S. Mukhopadhyay. “Exploiting Fully Integrated Inductive Voltage Regulators to Improve Side Channel Resistance of Encryption Engines.” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2016.

18. J. H. Ko and S. Mukhopadhyay, “An Energy-Aware Approach to Noise-Robust Moving Object Detection for Low-Power Wireless Image Sensor Platforms,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2016 (Best Paper Award).

19. T. Na and S. Mukhopadhyay, “Speeding up Convolutional Neural Network Training with Dynamic Precision Scaling and Flexible Multiplier-Accumulator,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2016

20. J. H. Kung, D. Kim, and S. Mukhopadhyay, “Dynamic Approximation with Feedback Control for Energy-Efficient Recurrent Neural Network Hardware,” IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2016.

21. Y. Long, E. M. Jung, J. Kung and S. Mukhopadhyay, “ReRAM Crossbar based Recurrent Neural Network for Human Activity Detection,” International Joint Conference on Neural Network (IJCNN), 2016.


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22. D. Kim, J. Kung, S. Chai, S. Yalamanchili, and S. Mukhopadhyay,” Neurocube: A Programmable Digital Neuromorphic Architecture with High-Density 3D Memory,” ACM/IEEE International Symposium on Computer Architecture (ISCA), 2016.

23. A. Singh, M. Kar, A. Rajan, V. De, and S. Mukhoapdhyay, “Integrated All-Digital Low-dropout Regulator as a Countermeasure to Power Attack in Encryption Engines,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2016.

24. D. Kim, J. H. Kung, S. Chai, S. Yalamanchili, and S. Mukhopadhyay, “NeuroCube: A Scalable, Efficient, Platform for Neuro-Inspired Computing,” GOMACTECH 2016

25. J.H. Ko, K. Ahmed, M. F. Amir, and S. Mukhoapdhyay, “A Self-powered Wireless Video Sensor Node for Moving Object Surveillance,” GOMACTECH 2016

26. A. Trivedi, S. Datta, and S. Mukhopadhyay, “Ultra Low Power Neuromorphic Associative Processing with Si/Ge and InAs/GaSb Heterojunction TFET,” GOMACTECH 2016.

27. T. Na and S. Mukhopadhyay, “Behavioral Modeling of Timing Slack Variation in Digital Circuits Due to Power Supply Noise,” Design Automation and Test in Europe, March 2016.

28. (Invited) K. Z. Ahmed, M. Kar, and S. Mukhopadhyay, “Energy Delivery for Self-Powered IoT Devices,” Asia South Pacific Design Automation Conference, 2016.

♦ 2015

29. A. Trivedi, R. Pandey, H. Liu, S. Datta, and S. Mukhopadhyay, “Gate/Source Overlapped Heterojunction Tunnel FET for non-Boolean Associative Processing with Plasticity,” IEEE International Electron Device Meeting (IEDM), Dec. 2015.

30. S. Marella, A. Trivedi, S. Mukhopadhyay, and S. Sapatnekar, “Optimization of FinFET-based circuits using a dual gate pitch technique,” to be presented at IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov. 2015.

31. W. Yueh, Z. Wan, Y. Joshi, and S. Mukhopadhyay, “Experimental Characterization of In- Package Microfluidic Cooling on a System-On-Chip,” IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED), July 2015. Best Paper Award

32. J. H. Kung, D. Kim, and S. Mukhopadhyay, “A Power-Aware Digital Feedforward Neural Network Platform with Backpropagation Driven Approximate Synapses,” IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED), July 2015.

33. A. Singh, M. Kar, and S. Mukhopadhyay, “Exploring Power Attack Protection of Resource Constrained Encryption Engines using Integrated Low-Drop-Out Regulators,” IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED), July 2015.

34. W. Song, S. Mukhopadhyay, and S. Yalamanchili, “Managing Performance-Reliability Tradeoffs in Multicore Processors,” IEEE International Reliability Physics Symposium, April 2015. Best Student Paper Award.

35. D. Manatunga, H. Kim, and S. Mukhopadhyay, “SP-CNN: A Scalable and Programmable CNN-based Accelerator,” GOMACTECH, March 2015.

36. M. Kar, A. Singh, D. Lie, M.Wolf, and S. Mukhopadhyay, “Improving Power Attack Immunity of Integrated Circuits using Integrated Inductive Voltage Regulators,” GOMACTECH, March 2015.

37. J. Ko, B. Ahmed, and S. Mukhopadhyay, “Adaptive Wireless Video Sensor Node Using Content- Aware Pre-processing for Moving Object Surveillance, “ GOMACTECH, March 2015.

♦ 2014


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38. M. F. Amir, A. Trivedi, and S. Mukhopadhyay, “A Tunnel-FET SRAM Array for Energy-Efficient Embedded Memory Blocks in Reconfigurable computing Platforms,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct. 2014.

39. Z. Wan, W. Yueh, Y. Joshi, and S. Mukhopadhyay, “On-Chip Temperature and Leakage Power Measurement and Comparison between Air Cooling and Microfluidic Cooling,” THERMINIC Sept. 2014

40. M. Kar, D. Lie, M. Wolf, V. De, and S. Mukhopadhyay, “Impact of Inductive Integrated Voltage Regulator on the Power Attack Vulnerability of Encryption Engines: A Simulation Study,” IEEE Custom Integrated Circuit Conference (CICC), Sept. 2014.

41. B. Alexandrov, K. Z. Ahmed, and S. Mukhopadhyay, “An On-Chip Autonomous Thermoelectric Energy Management System for Energy-Efficient Active Cooling,” IEEE International Symposium on Low-power Electronic Design (ISLPED), Aug. 2014. Best Paper Award.

42. M. Kar, S. Carlo, H. Krishnamurthy, and S. Mukhopadhyay, “Impact of the Process Variation in Inductive Integrated Voltage Regulator on Delay and Power of Digital Circuits,” IEEE International Symposium on Low-power Electronic Design (ISLPED), Aug. 2014.

43. D. Kim and S. Mukhopadhyay, “On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking,” IEEE/ACM Design Automation Conference (DAC), June 2014.

44. A. Trivedi, M. F. Amir, and S. Mukhopadhyay, “Ultra-low Power Electronics with Si/Ge Tunnel FET,” Design, Automation, and Test in Europe (DATE), March 2014.

45. A. Trivedi and S. Mukhopadhyay, “Si/Ge Tunneling Nanowires based Low Power Cellular Neural Network,” GOMACTech March 2014

46. W. Yueh, K. Z. Ahmed, and S. Mukhopadhyay, “Field Programmable Thermal Emulator (FPTE): An All-Silicon Test Structure for Thermal Characterization of Integrated Circuits,” IEEE Semi Therm March 2014. Honorable Mention in the Best Paper Award Selection.

47. S. Parthasarathy, K. Z. Ahmed, B. Alexandrov, S. Kumar, and S. Mukhopadhyay, “Energy Efficient Active Cooling of Integrated Circuits Using Autonomous Peltier/Seebeck Mode Switching of a Thermoelectric Module,” IEEE Semi Therm, March 2014.

♦ 2013

48. K. Yeleswarapu, A. Trivedi, and S. Mukhopadhyay, “Simulation of the TSV-to-Device Coupling in 3D ICs for Short-Channel Strained Silicon Transistors,” IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2013.

49. J. Kung, M. Cho, S. Yalamanchili, and S. Mukhopadhyay, “On-line Real-time Temperature and Power Estimation of an IC using Time-domain Thermal Filters,” IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2013.

50. M. Wolf and S. Mukhopadhyay, “Physics of Computing as an Introduction to Computer Engineering,” IEEE Frontiers of Education (FIE), Oct. 2013.

51. K. Z. Ahmed and S. Mukhopadhyay, “A 110nA Synchronous Boost Regulator with Autonomous Bias Gating for Energy Harvesting,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2013.

52. D. Lie, K. Chae, and S. Mukhopadhyay, “On the Impact of 3D Integration on High-Throughput Sensor Information Processing: A Case Study with Image Sensing,” NANOARCH, July 2013.

53. X. Wang, W. Yueh, S. Mukhopadhyay, D. Basu Roy, D. Mukhopadhyay, S. Narasimhan, Y. Sheng, and S. Bhunia, “Role of Power Grid in Side Channel Attack and Power-Grid-Aware Secure Design,” Design Automation Conference (DAC), June 2013.


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54. A. Trivedi, S. Carlo, and S. Mukhopadhyay, “Exploring Tunnel-FET for Ultra Low Power Analog Applications: A Case Study on Operational Transconductance Amplifier,” Design Automation Conference (DAC), June 2013. (Citations 28)

55. S. Carlo, W. Yueh, and S. Mukhopadhyay, “On the Potential of 3D Integration of Inductive DC-DC Converter for High-Performance Power Delivery,” Design Automation Conference (DAC), June 2013.

56. W. Yueh, M. Cho, and S. Mukhopadhyay, “Perceptual quality preserving SRAM architecture for color motion pictures,” Design, Automation and Test in Europe (DATE), March 2013.

♦ 2012

57. M. Cho, M. Khellah, K. Chae, K. Ahmed, J. Tschanz, and S. Mukhopadhyay, “Characterization of Inverse Temperature Dependence in Logic Circuits,” IEEE Custom Integrated Circuits Conference (CICC), Sept. 2012.

58. A. Trivedi and S. Mukhopadhyay, “Self-Adaptive Power Gating with Test Circuit for On-line Characterization of Energy Inflection Activity,” IEEE VLSI Test Symposium (VTS), April 2012.

59. W. Yueh, S. Chatterjee, A. Trivedi, and S. Mukhopadhyay, “On the Parameteric Failures of SRAM in a 3D-die Stack considering Tier-to-Tier Supply Cross-talk,” IEEE VLSI Test Symposium (VTS), April 2012.

60. W. Song, S. Yalamanchili, S. Mukhopadhyay, and A. Rodrigues, “Instruction-based Energy Estimation Methodology for Asymmetric Manycore Processor Simulations,” SIMUTools 2012.

61. S. Chatterjee, M. Cho, R. Rao, and S. Mukhopadhyay, “Impact of Die-to-Die Thermal Coupling on the Electrical Characteristics of 3D Stacked SRAM Cache,” IEEE Semi-Therm, Feb. 2012.

62. M. Cho, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Thermal System Identification (TSI): A Methodology for Post-silicon Characterization and Prediction of the Transient Thermal Field in Multicore Chips,” IEEE Semi-Therm, Feb. 2012.

63. B. Alexandrov, O. Sullivan, S. Kumar, and S. Mukhopadhyay, “Prospects of Active Cooling with Integrated Super-Lattice based Thin-Film Thermoelectric Devices for Mitigating Hotspot Challenges in Microprocessors,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2012.

64. K. Chae and S. Mukhopadhyay, “Tier-Adaptive-Voltage-Scaling (TAVS): A Methodology for Post-Silicon Tuning of 3D ICs,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2012.

♦ 2011

65. O. Sullivan, B. Alexandrov, S. Mukhopadhyay, and S. Kumar, “Compact Model of Thermoelectric Coolers on a Micro-electronic Chip,” ASME International Mechanical Engineering Congress & Exposition (IMECE), Nov. 2011.

66. A. Trivedi, W. Yueh, and S. Mukhopadhyay, “Impact of Through-Silicon-Via Capacitance on High Frequency Supply Noise in 3D-Stacks,” IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS), Oct. 2011.

67. S. Kim, S. Mukhopadhyay, H. Kim, and M. Wolf, “Low Energy Process Variation Tolerant Digital Image Processing System Design Based On Accuracy-Energy Tradeoffs,” IEEE Workshop in Signal Processing System (SiPS), Oct. 2011.

68. J. Tolbert and S. Mukhopadhyay, “Modeling and Designing for Energy Efficiency in Wireless EEG Systems” IEEE Sub-threshold Microelectronics Conference (IEEE SubVt), Sept. 2011.


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69. X. Zhao, J. Tolbert, S. Mukhopadhyay, and S. K. Lim, “Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits,” International Symposium on Low-power Electronic Design (ISLPED), Aug. 2011.

70. M. P. Gupta, M. Cho, S. Mukhopadhyay, and S. Kumar, “An Investigation into Power Migration Policies for Many-Core Processors to Manage On-chip Thermal Profile,” The ASME 2011 Pacific Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, MEMS, and NEMS (InterPACK2011), July 2011.

71. X. Zhao, S. Mukhopadhyay, and S. K. Lim, “Variation-Tolerant and Low-Power Clock Network Design for 3D ICs,” Electronic Components and Technology Conference (ECTC), May-June 2011.

72. (INVITED) K. Chae, C. H. Lee, and S. Mukhopadhyay, “Timing error prevention using elastic clocking,” IEEE International Conference on IC Design and Technology (ICICDT), May 2011.

73. J. J. Kim, B. P. Linder, R. M. Rao, T. H. Kim, P. F. Lu, K. A Jenkins, C. H. Kim, A. Bansal, S. Mukhopadhyay, and C. T. Chuang, “Reliability Monitoring Ring Oscillator Structures for Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies,” International Reliability Physics Symposium (IRPS), April 2011.

♦ 2010

74. M. Cho, C. Liu, D. H. Kim, S. Lim, and S. Mukhopadhyay, “Design Method and Test Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System,” IEEE International Conference on Computer Aided Design (ICCAD), Nov. 2010. pp. 694-697. (Citations 38)

75. O. Sullivan, M. Gupta, S. Mukhopadhyay, and S., Kumar, “Thermoelectric coolers for thermal gradient management on chip,” ASME International Mechanical Engineering Congress & Exposition (IMECE), Nov. 2010, pp.1-9.

76. M. Cho, N. Sathe, A. Raychowdhury, and S. Mukhopadhyay, “Optimization of Burn-in Test for Many-core Processors Through Adaptive Spatiotemporal Power Migration,” International Test Conference, Oct. 2010, pp. 1-9.

77. K. Chae, S. Mukhopadhyay, C. H. Lee, and J. Laskar, “A Dynamic Timing Control Technique Utilizing Time Borrowing and Clock Stretching,” IEEE Custom Integrated Circuit Conference (CICC), Sept. 2010, pp. 1-4.

78. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Analysis of Thermal Behaviors of Spin-Torque-Transfer RAM: A Simulation Study,” International Symposium on Low-Power Electronic Design (ISLPED), August 2010, pp. 13-18.

79. M. Rasquinha, D. Choudhary, S. Chatterjee, S. Mukhopadhyay, S. Yalamanachili, “An Energy Efficient Cache Design Using Spin Torque Transfer (STT) RAM,” International Symposium on Low-Power Electronic Design (ISLPED), August 2010, pp. 389-394.

80. M. P. Gupta, M. H. S. Sayer, S. Mukhopadhyay, and S. Kumar, “On-Chip Peltier Cooling Using Current Pulse,” IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Itherm), June 2010, pp. 1 – 7.

81. M. P. Gupta, M. Cho, S. Mukhopadhyay, and S. Kumar, “Thermal Management of Multicore Processors Using Power Multiplexing,” IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Itherm), June 2010, pp. 1-7.

82. J. Tolbert, P. Kabali, S. Brar, and S. Mukhopadhyay, “A Low Power System with Adaptive Data Compression for Wireless Monitoring of Physiological Signals and its Application to Wireless Electroencephalography,” IEEE International Symposium in Quality Electronic Design, March 2010. pp. 333-341.


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83. M. Cho and S. Mukhopadhyay, “Signal Processing Methods and Hardware-Structure for On-line Characterization of Thermal Gradients in Many-Core Processors,” IEEE International Symposium in Quality Electronic Design (ISQED), March 2010. pp. 797-803

84. M. Cho, N. Sathe, M. Gupta, S. Kumar, S. Yalamanchili and S. Mukhopadhyay, “Proactive Power Migration to Reduce Maximum Value and Spatiotemporal Non-uniformity of On-chip Temperature Distribution in Homogeneous Many-Core Processors,” IEEE Semi-Therm, Feb. 2010, pp. 180-186.

♦ 2009

85. S. Paul, S. Mukhopadhyay, and S. Bhunia, “A Variation-Aware Preferential Design Approach for Memory Based Reconfigurable Computing,” International Conference on Computer Aided Design (ICCAD), Nov. 2009, pp. 180-183.

86. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, “A Circuit-Software Co-Design Approach for Improving EDP in Reconfigurable Frameworks,” International Conference on Computer Aided Design (ICCAD), Nov. 2009, pp. 109-112.

87. S. Chatterjee, M. Rasquinha, S. Yalamanchili, and S. Mukhopadhyay, “A Methodology for Robust, Energy Efficient Design of Spin-Torque-Transfer RAM Arrays at Scaled Technologies,” International Conference on Computer Aided Design (ICCAD), Nov. 2009, pp. 474-477.

88. A. Bansal, R. N. Singh, R. N. Kanj, S. Mukhopadhyay, J. F. Lee, E. Acar, A. Singhee, K. Kim, C. T. Chuang, S. Nassif, F. L. Heng, and K. K. Das, “Yield Estimation of SRAM Circuits using Virtual SRAM Fab,” International Conference on Computer Aided Design (ICCAD), Nov. 2009, pp. 631-636.

89. S. Khire and S. Mukhopadhyay, “On improving the algorithmic robustness of a low-power FIR filter,” IEEE International Conference on Computer Design (ICCD), Oct. 2009, pp. 384-389.

90. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Modeling of Self-Heating in STTRAM and Analysis of its Impact on Reliable Memory Operations,” IEEE Non-Volatile Memory Technology Symposium (NVMTS), Oct. 2009, pp. 86-89.

91. J. Tolbert, P. Kabali, S. Brar, and S. Mukhopadhyay, “Accuracy Aware Low Power Wireless EEG Unit with Information Content based Adaptive Data Compression,” Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS'09), Sept. 2009, pp. 5417-5420.

92. J. Tolbert, X. Zhao, S. Mukhopadhyay, and S. Lim, “Slew-Aware Clock Tree Design For Reliable Subthreshold Circuits,” International Symposium on Low-Power Electronic Design (ISLPED), Aug. 2009, pp. 15-20.

93. S. Kim, S. Mukhopadhyay and W. Wolf, “Experimental analysis of sequence dependence on energy saving for error tolerant image processing,” International Symposium on Low-Power Electronic Design (ISLPED), Aug. 2009, pp. 347-350.

94. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, “Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array,” International Conference on Nanotechnology (IEEE Nano), July 2009.

95. D. H. Kim, S. Mukhopadhyay, and S. Lim, “Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs,” International Workshop on System Level Interconnect Prediction, July 2009, pp. 85-92.

96. D. H. Kim, S. Mukhopadhyay, and S. Lim, “TSV-aware Interconnect Length and Power Prediction for 3D Stacked ICs,” IEEE International Interconnect Technology Conference (IITC), June 2009, pp. 26-28.

97. J. Tolbert and S. Mukhopadhyay, “Accurate Buffer Modeling with Slew Propagation in Subthreshold Circuits,” International Symposium on Quality Electronic Design (ISQED), Mar. 2009, pp. 91-96.


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98. M. Cho, J. Schlessman, W. Wolf, and S. Mukhopadhyay, “Accuracy-Aware SRAM: A Reconfigurable Low Power SRAM Architecture for Mobile Multimedia Applications,” Asia-Pacific Design Automation Conference (ASPDAC), Jan. 2009, pp. 823-828.

♦ 2008

99. S. Paul, S. Mukhopadhyay, and S. Bhunia, “Hybrid CMOS-STTRAM Non-Volatile FPGA: Design Challenges and Optimization Approaches,” International Conference on Computer Aided Design (ICCAD), Nov. 2008, pp. 589-592.

100. A. Bansal, R. Singh, S. Mukhopadhyay, G. Han, F. L. Heng, and C. T. Chuang, “Pre-Si Estimation and Compensation of SRAM Layout Deficiencies to Achieve Target Performance and Yield,” International Conference on Computer Design, Oct. 2008, pp. 457-462.

101. M. Cho, K. Maitra, and S. Mukhopadhyay, “Analysis of the Impact of Interfacial Oxide Thickness Variation on Metal-Gate High-K Circuits,” Custom Integrated Circuit Conference (CICC), Sept. 2008, pp. 285-288.

102. S. Mukhopadhyay, “A Generic Method for Variability Analysis of Nanoscale Circuits,” International Conference on IC Design & Technology (ICICDT), June 2008, pp. 285-288, (citations in an article in www.semiconductor.net).

103. J.J. Kim, R. Rao, S. Mukhopadhyay, and C. T. Chuang, “Ring Oscillator Circuit Structures for Measurement of Isolated NBTI/PBTI Effects,” International Conference on IC Design & Technology(ICICDT), June 2008, pp. 163-166.

104. S. Mukhopadhyay, R. Rao, J. J. Kim, and C. T. Chuang, “Capacitive Coupling Based Transient Negative Bit-line Voltage (Tran-NBL) Scheme for Improving Write-ability of SRAM Design in Nanometer Technologies,” IEEE Intl. Symp on Circuits and Systems (ISCAS), May 2008, pp. 384-387.

105. N. N. Mojumder, S. Mukhopadhyay, J. J. Kim, C. T. Chuang, and K. Roy, “Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry,” IEEE VLSI Test Symposium (VTS), April 2008, pp. 101-106.

106. S. Mukhopadhyay, R. Joshi, K. Kim, and C. T. Chuang, “Variability Analysis for Sub-100 nm PD/SOI Sense-Amplifier,” IEEE Intl. Symp. on Quality Electronic Design (ISQED), Mar 2008, pp. 488-491.

107. A. Bansal, J. J. Kim, K. Kim, S. Mukhopadhyay, C. T. Chuang, and K. Roy, “Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies,” Intl. Conf. on VLSI Design, Jan. 2008, pp. 125-130.

♦ 2007

108. S. Mukhopadhyay, K. Kim, and C. T. Chuang, “Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies,” in Proc. of the Intl. Symp. on Low Power Electronics and Design (ISLPED) Aug. 2007, pp. 20-25.

109. A. Bansal, K. Kim, J. J. Kim, S. Mukhopadhyay, C. T. Chuang, and K. Roy, “High-Performance Device Optimization and Dual-VT Technology Options for Double Gate FET,” in Proc. of Intl. Conf. on Integrated Circuit Design and Technology (ICICDT), May 2007, pp. 1-4.

110. S. Mukhopadhyay, Q. Chen, K. Roy, “Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance,” in Proc. of Design and Diagnostics of Electronic Circuits and Systems (DDECS), Apr. 2007, pp. 1-6.

111. S. Mukhopadhyay, K. Kim, K. A. Jenkins, C. T. Chuang, and K. Roy, “Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense Amplifier-Based Test Structure”, in Tech. Digest of IEEE Intl. Solid State Circuit Conference (ISSCC), Feb. 2007, pp. 400-401 (citations 42).


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112. S. Bhunia, S. Mukhopadhyay, and K. Roy, “Process Variations and Process-Tolerant Design,” in Proc. of IEEE International Conference on VLSI Design, 2007, Jan. 2007, pp. 699-704.

♦ 2006

113. S. Mukhopadhyay, A. Agarwal, Q. Chen, and K. Roy, “SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design (INVITED),” in Proc. of IEEE Custom Integrated Circuit Conf. (CICC), Sept. 2006, pp. 547-554.

114. S. Gangwal, S. Mukhopadhyay, and K. Roy, “Optimization of Surface Orientation for High-Performance, Low-Power, and Robust FinFET SRAM,” in Proc. of IEEE Custom Integrated Circuit Conf. (CICC), Sept. 2006, pp. 433-436.

115. S. Mukhopadhyay, S. Ghosh, K. Kim, and K. Roy, “Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies (INVITED)”, in Proc. of IEEE Intl. System-On-Chip Conf. (SOCC), Sept. 2006, pp. 155-159.

116. S. Ghosh, S. Mukhopadhyay, K. Kim, and K. Roy, “Self-Calibration Technique for Reducing Hold Failures in Low-Power Nano-scaled SRAM under Process Variation,” in Proc. of Design Automation Conference (DAC), July 2006, pp. 971-976.

117. S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, “Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory,” in Tech. Digest of Symp. on VLSI Circuits, June 2006, pp. 132-133.

118. Q. Chen, S. Mukhopadhyay, A. Bansal, and K. Roy, “Circuit-aware device design methodology for nanometer technologies: A case study for low power SRAM design,” in Proc. of Design, Automation and Test in Europe (DATE), Mar. 2006, pp. 983-988.

119. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, “Speed Binning Aware Design Methodology to Improve Profit under Parameter Variation”, in Proc. of Asia and South Pacific Design Automation Conf. (ASP-DAC), Jan. 2006, pp. 712-717, nominated for the best paper award.

120. K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Low-Power and High-Performance Circuit Design using FinFET Devices (INVITED),” in Proc. of Intl. Conf. on VLSI Design, Jan. 2006, pp. 445-452.

♦ 2005

121. S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy, “Leakage Current based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM,” in Proc. of Asian Test Symp. (ATS), Dec. 2005. pp. 176-181.

122. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, “A statistical approach to area-constrained yield enhancement for pipelined circuits under parameter variations,” in Proc. of Asian Test Symp. (ATS), Dec. 2005, pp. 170-175.

123. K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Double-Gate SOI Devices for Low-Power and High-Performance Applications (INVITED),” in Proc. of Intl. Conf. on Computer Aided Design (ICCAD), Nov. 2005, pp. 217-224.

124. S. Mukhopadhyay, K. Kang, H. Mahmoodi, and K. Roy, “Reliable and Self-Repairing SRAM in Nano-scale Technologies using Leakage and Delay Monitoring,” in Proc. of Intl. Test Conf. (ITC), Nov. 2005.

125. T. Cakici, H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Independent Gate Skewed Logic in Double-Gate SOI Technology,” in Proc. of IEEE Intl. SOI Conf., Oct. 2005, pp. 83-84.


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126. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A Feasibility Study of Subthreshold SRAM across Technology Generations,” in Proc. of IEEE Intl. Conf. on Computer Design (ICCD), Oct. 2005. pp. 417-424.

127. A. Bansal, S. Mukhopadhyay, and K. Roy, “Modeling and Optimization Approach to Robust and Low-Power FinFET SRAM Design in NanoScale Era,” in Proc. of IEEE Custom Integrated Circuit Conf. (CICC), Sept. 2005. pp. 835-838.

128. I. J. Chang, K. Kang, S. Mukhopadhyay, C. H. Kim, and K. Roy, “Fast and Accurate Estimation of Nano-Scaled SRAM Read Failure Probability using Critical Point Sampling,” in Proc. of IEEE Custom Integrated Circuit Conf. (CICC), Sept. 2005, pp. 439-442.

129. S. Mukhopadhyay, K. Kim, C. T. Chuang, and K. Roy, “Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Circuits,” in Proc. of Intl. Symp. on Low Power Electronics and Design (ISLPED), Aug. 2005, pp. 8-13.

130. Q. Chen, S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Process Variation Tolerant Online Current Monitor for Robust Systems,” in Proc. of IEEE Intl. On-Line Testing Symp. (IOLTS), July 2005, pp. 171-176.

131. A. Datta, S. Mukhopadhyay, S. Bhunia, and K. Roy, “Reliability Analysis and Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in sub-100nm Technology,” in Proc. of IEEE Intl. On-Line Testing Symp. (IOLTS), July 2005, pp. 275-280.

132. S. Mukhopadhyay, S. Bhunia and K. Roy, "Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits," in Proc. of Design, Automation, and Test in Europe (DATE), Mar. 2005, pp. 224-229.

133. A. Datta, S. Bhunia, S. Mukhopadhyay, N. Banerjee, and K. Roy, "Statistical Modeling and Design of Pipeline under Process Variation to Enhance Yield," in Proc. of Design, Automation, and Test in Europe (DATE), Mar. 2005, pp. 926-931.

134. S. Mukhopadhyay, K. Kim, J. J. Kim, S.H. Lo, R. Joshi, C. T. Chuang, and K. Roy, “Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits,” in Proc. of IEEE Intl. Symp. on Quality Electronic Design (ISQED), Mar. 2005, pp. 410-415.

135. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Design of High Performance Sense Amplifier Using Independent Gate Control in Fully Depleted Double-Gate MOSFET," in Proc. of IEEE Intl. Symp. on Quality Electronic Design (ISQED), Mar. 2005, pp. 490-495.

♦ 2004

136. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Statistical Design and Optimization of SRAM Cell for Yield Enhancement," in Proc. of Intl. Conf. on Computer Aided Design (ICCAD), Nov. 2004. pp. 10-13 (citations 85).

137. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “High Performance and Low Power Domino Logic Using Independent Gate Control in Double-Gate SOI MOSFETs,” in Proc. of IEEE Intl. SOI Conf., Oct. 2004, pp. 67-68.

138. S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy, “A Novel Low-Power Scan Design Technique Using Supply Gating,” in Proc. of IEEE Intl. Conf. on Computer Design (ICCD), Oct. 2004, pp. 60-65, Best Paper Award.

139. R. Joshi, S. Mukhopadhyay, D. Plass, Y. Chan, C. T. Chuang, and A. Devgan, "Variability analysis for Sub-100 nm PD/SOI CMOS SRAM Cell," in Proc. of European Solid State Circuit Conf. (ESSCIRC), Sept. 2004, pp. 211-214.


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140. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nano-Scaled CMOS Circuits," in Proc. of IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2004, pp. 17-20.

141. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling and Estimation of Failure Probability due to Parameter Variations in Nano-scale SRAMs for Yield Enhancement," in Tech. Digest of Symp. on VLSI Circuits, June 2004. pp. 64-67 (citations 67).

142. A. Agarwal, C. H. Kim, S. Mukhopadhyay, and K. Roy, "Leakage in Nano-Scale Technologies: Mechanisms, Impact and Design Considerations," in Proc. of Design Automation Conf. (DAC), June 2004, pp. 6-11.

143. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Modeling and Estimation of Leakage in sub-90nm Devices,” in Proc. of Intl. Conf. on VLSI Design, Jan. 2004, pp. 65-70.

♦ 2003

144. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Modeling of Ballistic Field-effect Transistors for Efficient Circuit Simulation,” in Proc. of Intl. Conf. on Computer Aided Design (ICCAD), Nov. 2003, pp. 487-490.

145. S. Mukhopadhyay, H. Mahmoodi, C. Neau, and K. Roy, “Leakage in Nanometer Scale CMOS Circuits (INVITED),” in Proc. of Intl. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), Oct. 2003, pp. 307-312.

146. S. Mukhopadhyay and K. Roy, “Modeling and Estimation of Total Leakage Current in Nano-scaled CMOS Devices Considering the Effect of Parameter Variation,” in Proc. of Intl. Symp. on Low Power Electronics and Design (ISLPED), Aug. 2003, pp. 172-175 (citations 120).

147. C. H. Kim, J. J. Kim, S. Mukhopadhyay, and K. Roy, “A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations,” in Proc. of Intl. Symp. on Low Power Electronics and Design (ISLPED), Aug. 2003, pp. 6-9.

148. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Circuit Compatible Modeling of Carbon Nanotube FETs in the Ballistic Limit of Performance,” in Proc. of IEEE Conf. on Nanotechnology (IEEE Nano), Aug. 2003, pp. 343-346, Best Student Paper Award.

149. S. Mukhopadhyay and K. Roy, "Accurate Modeling of Transistor Stacks to Effectively Reduce Total Standby Leakage in Nano-Scale CMOS Circuits," in Tech. Digest of Symp. of VLSI Circuits, June 2003, pp. 53-56.

150. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling,” in Prof. of Design Automation Conf. (DAC), June 2003, pp. 169-174, nominated for the Best Paper Award.

151. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Leakage Control for Deep Submicron Circuits (INVITED),” in Proc. of SPIE – vol 5117, VLSI Circuits and Systems, April 2003, pp. 135-146.

B3. Other Refereed Material 1. W. Yueh, K. Z. Ahmed, and S. Mukhopadhyay, “An All-Silicon Field Programmable Thermal

Emulator for Integrated Circuits,” Electronics Cooling Magazine, May, 2015, Available online: http://www.electronics-cooling.com/2015/05/an-all-silicon-field-programmable-thermal-emulator-for-integrated-circuits/?hootPostID=d0cb708043b817d8bbfa973c3b9eac0e

2. M. Kar, H. Krishnamurthy, and S. Mukhopadhyay, “Analysis of the Effect of Process Variation on Integrated Voltage Regulators,” SRC TECHCON 2014, Best in Session Award

3. K. Z. Ahmed, and S. Mukhopadhyay, “Multi-Domain Power Delivery System for Microwatt Wireless Sensor Networks,” SRC TECHCON 2014, Best in Session Award


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4. W. J. Song, S. Mukhopadhyay, and S. Yalamanchili, “Lifetime Reliability Characterization and Management of Many-Core Processors,” SRC TECHCON 2014, Best in Session Award

5. A. Trivedi and S. Mukhopadhyay, “Self Adaptive Power-Gating Scheme by On-Line Characterization of Energy Inflection Activity,” SRC TECHCON, September 2012.

6. K. Chae, X. Zhao, A. R. Trivedi, S. Lim, and S. Mukhopadhyay, “Post-Silicon Tuning Method for Clock Networks to Minimize Clock Skews in 3D ICs,” SRC TECHCON, September 2012.

7. K. Chae, M. Rasquinha, S. M. Hasan, S. Yalamanchili, and S. Mukhopadhyay, “Statistical Analysis of the Effect of Network on Performance of Many-Core Platform with 3D-Stacked DRAM,” SRC TECHCON, Sept. 2011.

8. M. Cho, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Modeling of the Thermal Field of Many-Core System using Frequency Domain System Identification,” SRC TECHCON, Sept.2011.

9. W. J. Song, M. Cho, S. Yalamanchili, S. Mukhopadhyay, and A. F. Rodrigues “Energy Introspector: Simulation Infrastructure for Power, Temperature, and Reliability Modeling in Manycore Processors,” SRC TECHCON, Sept. 2011.

10. M. Rasquinha, S. M. Hassan, W. Song, K. Chae, M. Cho, S. Mukhopadhyay, and S. Yalamanchili, “System Impact of 3D Processor-Memory Interconnect: A Limit Study,” SRC TECHCON, Sept. 2011.

11. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Analysis and Reduction of Parametric Failures in SRAM to Enhance Yield in Nano-Scale Memories,” SRC TECHCON, Oct. 2005, Best in Session Award.

C. OTHER PUBLICATIONS AND CREATIVE PRODUCTS

C1. Non-refereed Conference Presentations with Proceedings

No data

C2. Software

No data

C3. PATENTS Awarded

1. S. Banerjee, D. Chidambarrao, J. Culp, P. Elakkumanan, and S. Mukhopadhyay, “Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance,” United States Patent no. 8176444, issued on 03/08/2012.

2. C. T. Chuang, J. J. Kim, T. H. Kim, P. F. Lu, R. Rao, S. Mukhopadhyay, and S. Wang, “Circuits and Design Structures for Monitoring NBTI (Negative Bias Temperature Instability) Effect and/or PBTI (Positive Bias Temperature Instability),” United States Patent No. 7642864, issued on, 01/05/2010.

3. C. T. Chuang, J. J. Kim, and S. Mukhopadhyay, “Circuits and Methods for Characterizing Device Variation in Electronic Memory Circuits,” United States Patent no. 7673195, issued on 03/02/2010.

4. S. Mukhopadhyay, H. Mahmoodi, K. Kim, and K. Roy, “Self Repairing technique in nano-scale SRAM to reduce parametric failures,” United States Patent no. 7508697, issued on 03/24/2009.

5. S. Bhunia, H. Mahmoodi, A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Low power scan design and delay fault testing technique using first level supply gating,” United States Patent no. 7319343, issued on 1/15/2008.


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6. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Sense Amplifier Circuit,” United States Patent no. 7304903, issued on 12/4/2007.

Pending

1. S. Bagheri, F. L. Heng, R. V. Joshi, K. Lai, D. O. Melville, S. Mukhopadhyay; A. E. Rosenbluth, R. N. Singh, And K. Tian, Analyzing A Patterning Process Using A Model Of Yield, patent pending, filed on Jan. 18, 2012 by IBM Corporation, Publication No. 20130185045, Publication Date: 2013-07-18.

2. C. T. Chuang, F. L. Heng, R. Kanj, K. Kim, J. F. Lee, S. Mukhopadhyay, S. R. Nassif, and R. N. Singh, “Techniques For Pattern Process Tuning And Design Optimization For Maximizing Process-Sensitive Circuit Yields,” patent pending, filed on Feb. 1, 2008 by IBM Corporation, Publication No. 20110173577, Publication Date: 2011-07-14..

3. C. T. Chuang, J. J. Kim, N. Mojumder, and S. Mukhopadhyay, “Circuits, Methods and Design Structures for Adaptive Repair of SRAM Arrays,” patent pending, filed on Jan. 24, 2008 by IBM Corporation, Publication No. 20090190426, Publication Date: 2009-07-30.

D. PRESENTATIONS

D1. Keynote Addresses and Plenary Lectures

1. S. Mukhopadhyay, “What do ultra low power requirements mean for secure hardware?,” 10th Workshop on Embedded Systems Security (WESS 2015), Oct. 2015.

D2. Invited Conference and Workshop Presentations

1. S. Mukhopadhyay, “Ultra Low Voltage Energy Harvesting: Challenges and Design Methodologies,” IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct. 2014.

2. S. Mukhopadhyay, “Ultra-Low Power Electronics With Si/Ge Tunnel FET,” Design, Automation, and Test in Europe (DATE), Dresden, Germany, 2014.

3. S. Mukhopadhyay, “Low-voltage Resilient Circuits under Dynamic Noise,” International Conference on VLSI Design, Mumbai, India, 2014,

4. S. Mukhopadhyay, “Error-Resilient Logic Circuits under Dynamic Variations,” IEEE International On-line Test Symposium, Greece, July 2013.

5. S. Mukhopadhyay, “Low-Power Design under Variation using Error Prevention and Error Tolerance,” IEEE Latin American Test Workshop (LATW), April 2012.

6. S. Mukhopadhyay, “Variability Characterization for Narrow-Width Devices and Application to Post-Silicon Repair in SRAM,” VLSI Test Symposium, Santa Cruz, CA, April 2010.

D3. Conference and Workshop Presentations

No data

D4. Invited Seminar Presentations

1. “Designing Energy-Efficient and Reliable Electronics: The Role of System Level Multi-physics Interaction,” Microsoft Corporation, CA, Nov. 2014.

2. “Designing for Energy-Efficiency and Reliability in Future Systems.” Invited Seminar at Qualcomm Corp., San Diego, CA, Feb. 2013.


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3. “Designing for Energy-Efficiency and Reliability in Future Systems,” Invited Seminar at IBM India Pvt. Ltd, Bangalore, India, Jan. 2013.

4. “Designing for Energy-Efficiency and Reliability in Future Multi-Core and 3D Systems,” Invited Seminar at Texas Instruments, Dallas, TX, Oct. 2012.

5. “Low-Power and Temperature-Aware Design of Integrated Circuits,” Invited Seminar at IBM T. J. Watson Research Center, Yorktown Heights, NY, June. 2012.

6. “Low-Power and Temperature-Aware Design of Integrated Circuits,” Invited Seminar at Intel Labs, Hillsboro, OR, June. 2012.

7. “Energy and Reliability of 3D Integration: Opportunities and Challenges,” Invited Seminar at 3D System Integration Workshop, Interconnect and Packaging Center, Atlanta, GA, June 2011.

8. “Designing for Energy-Efficiency and Reliability in Future Multi-Core and 3D Systems,” Invited Seminar at Texas Instruments, Dallas, TX, Nov. 2011.

9. “Addressing the Thermal Challenges in Many-Core Processors,” Invited Seminar at IBM T. J. Watson Research Center, Yorktown Heights, NY, Oct 2010.

10. “Addressing the Thermal Challenges in Many-Core Processors,” Invited Seminar at IBM Austin Research Lab, Austin, TX, Oct 2010.

11. “Gigascale Reliable Energy-Efficient Many-Core and 3D IC Design in Nanometer Nodes,” Invited Seminar at Intel Circuit Research Lab, Hillsboro, OR, Oct 2009.

12. “Design Challenges and Solutions in Nanometer Technologies: Embedded Memories and 3D IC,” Invited Seminar at Portland Technology Development, Intel Corp, Hillsboro, OR, Oct 2009.

13. “Design in Emerging Technologies: Circuit and Technology Perspectives,” Invited Seminar at National Chiao-Tung University, Hsinchu, Taiwan, Nov. 2008.

14. “Embedded Memory Design in Nanoscale Silicon Technologies,” Invited Seminar at National Chiao-Tung University, Hsinchu, Taiwan, Nov. 2008.

15. “Embedded Memory Design in Nanoscale Silicon Technologies,” Invited Seminar at Faraday Technology Corporation, Hsinchu, Taiwan, Nov. 2008.

D5. Other Presentations

No data

E. GRANTS AND CONTRACTS

Total Grant allocated to Dr. Mukhopadhyay’s research group (~5,500,000). Grant allocated as: PI: ~$4,200,000 ; co-PI: $1,068, 000; Equipment Grant: ~$135,000 Sponsors: National Science Foundation, Office of Naval Research, Sandia National Lab, Semiconductor Research Corporation, Defense Advanced Research Program Agency, Intel, Qualcomm, and IBM.

E1. As Principal Investigator

♦ Active Grants

1. S. Mukhopadhyay (PI) and M. Swaminathan (co-PI), “A System-In-Package Platform for Energy Harvesting and Delivery for IoT Edge Devices,” Semiconductor Research Corporation, Fund from Sponsor ($300,000); Fund including GT Cost-share: $460,785; June 1, 2017 - May 31, 2020


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2. S. Mukhopadhyay (PI), “On-line Self-Testing and Self-Tuning of Integrated Voltage Regulators,” Semiconductor Research Corporation, Fund from Sponsor ($246,000); Fund including GT Cost-share: $317,454; Nov 1, 2016 - Oct 31, 2019

3. S. Mukhopadhyay (PI), “OROEB: On-line Real-Time Optimal Energy Balancing for Self-Powered Environment Adaptive Sensor Node,” Office of Naval Research Young Investigator Program; Fund from Sponsor ($510,000); Fund including GT Cost-share: $690,000; Jan. 1, 2013 – July. 31, 2018.

4. S. Mukhopadhyay (PI), “CSR: SMALL: Exploiting 3D Integration for Power Management In Embedded Processors,” National Science Foundation; Fund: $450,000; Aug. 1, 2012 – July 31, 2016

5. S. Mukhopadhyay (PI), “CAREER: 3D Heterogeneous Integration for Power Reduction in Embedded Systems: Application to Wireless Image Sensing and Transport,” National Science Foundation, Fund from sponsor: $461,170, Fund including GT Cost Share: $717,347; Feb. 1, 2011 – Jan. 31, 2017.

♦ Industrial Gifts via Georgia Tech Foundation (Active)

6. S. Mukhopadhyay, “Integrated Voltage Regulators for Power Attack Protection of Encryption Engine”, Intel Corp, Fund: $255,000, received $85,000 on March, 2015.

7. S. Mukhopadhyay, “Integrated Voltage Regulators for Power Attack Security”, Intel Corp, Fund: $61,377 received on September 2014.

8. S. Mukhopadhyay, “Integrated Voltage Regulators”, Qualcomm Corp, Fund: $40,000 received on August, 2014.

9. S. Mukhopadhyay (PI), “Thermal and Power Analysis and On-Line Management in 3D Systems ” IBM Faculty Award, 2010; Fund: $25,000 received on August 2010.

10. S. Mukhopadhyay (PI), “3D Integrated Circuits,” Intel Corp, Fund: $25,000. Gift received on March 2010.

11. S. Mukhopadhyay (PI), “On-line Thermal Management of Many-Core Processors,” IBM Faculty Award, 2009, Fund: $25,000 received on August 2009.

12. S. Mukhopadhyay (PI), “Designing Many Processing Element Systems in Nanometer Era,” Intel Corp., Fund: $36,000 (Cash) + 3 Dell PCs (~$5000 in equipment); Gift received on January 2009.

13. Equipment: S. Mukhopadhyay (PI), 5 Virtex-V FPGA board from Xilinx Corp. thorugh Xilinx University Program (equivalent value ~ $9995). Gift received on 2008.

♦ Completed Grants

14. S. Mukhopadhyay (PI), “Distributed Power Delivery Architecture for 2D and 3D Integrated Circuits,” Semiconductor Research Corp, Fund (including IPC cost-share): $255,832; Aug. 1, 2012 – July 31, 2016.

15. S. Mukhopadhyay (PI) and S. Lim (co-PI), “Design of 3D Heterogeneous Systems,” Semiconductor Research Corp, Fund: $420,957; Mar. 1, 2011 – May. 31, 2015; Dr. Mukhopadhyay’s share ~50%.

16. S. Mukhopadhyay (PI), “Collaborative Research: Reconfigurable Computing Using 2D Nanoscale Memory Array For Multimedia Signal Processing,” National Science Foundation, Fund: $174,198; July 1, 2010 – June 30, 2014.

17. S. Mukhopadhyay (PI) and S. Yalamanchili (co-PI), “On-Line Coordinated Global Power And Thermal Management For Many-Core Processors,” Semiconductor Research Corp, Fund: $330,000; Aug. 1, 2010 – July 31, 2013; Dr. Mukhopadhyay’s share ~50%.

18. S. Mukhopadhyay (PI) and W. Wolf (co-PI) “SHF:Small:A Generic Micro-Architecture for Accuracy-Aware Ultra Low Power Multimedia Processing,” National Science Foundation, Sept. 1, 2009 – Aug. 31, 2013, Fund: $485,638. Dr. Mukhopadhyay’s share ~50%.


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19. S. Mukhopadhyay (PI) and S. Yalamanchili (co-PI), “A System Driven Approach to Exploit the Advantage of 3D – a project under IFC research program for "connectivity" in hyper-integrated electronics,” Marco (Microelectronics Advanced Research Corp), July 1, 2010- Dec. 31, 2012; Received amount $157,227. Dr. Mukhopadhyay’s share ~50%.

20. S. Mukhopadhyay (PI), “Design of Low-Power Wireless Electroencephalography,” SCEEE, July 1, 2010 – June 30, 2011, received amount $38,000

E2. As Co-Principal Investigator

♦ Active Grants

21. M. Swaminathan (PI), S. Mukhopadhyay (co-PI), A. Raychowdhury (co-PI), H. Wang (co-PI), and P. Kohl (co-PI), “Power Delivery for Electronic Systems (PDES)”, An Industry Consortium under IPC and IEN. Launch Date: Sept 15, 2015, Phase-I: 2 years; Current budget: 6 members @ 60,000/year, total: $720,000; Dr. Mukhopadhyay’s share ~$150,000. Dr. Mukhopadhyay is the leader of Thrust IV. Note PDES projects have a minimal (10%) rate for indirect costs.

22. H. Kim (PI), S. Mukhopadhyay (co-PI), and S. Yalamanchili (co-PI), “XPS: FULL: CCA: Cymric: A Flexible Processor-Near-Memory System Architecture,” National Science Foundation, August 1, 2015-July 31, 2018; Total budget: $750,000; Dr. Mukhopadhyay’s share ~$33%.

23. S. Yalamanchili (PI), S. Mukhopadhyay (co-PI), and H. Kim (co-PI), “EAGER: CCF: Transient Architectures for Energy Efficient Computation,” National Science Foundation, March. 1, 2014 – Feb. 28, 2016, amount $300,000, Dr. Mukhopadhyay’s share ~$100,000.

♦ Industrial Gifts via Georgia Tech Foundation (Active)

24. S. Mukhopadhyay, “Power-Thermal-Co-Design,” Qualcomm Corp, Fund: $15,000; Gift received on April, 2013.

♦ Completed Grants

25. M. Bakir (PI), GT Co-PIs: Y. Joshi, S. Yalamanchili, S. Mukhopadhyay, “SUPERCool 3D ICs - SUperior Performance Electronics using Recirculating Coolant for 3D ICs,” DARPA, Dec. 1, 2014 – Nov. 30, 2016, amount: $2.282M, Dr. Mukhopadhyay’s share ~ $200K.

26. S. Yalamanchili (PI) and S. Mukhopadhyay (co-PI), “Exploration of Adaptive 3D Many-core Architecture,” Semiconductor Research Corp, Fund: $255,000; Aug. 1, 2012 – July 31, 2015; Dr. Mukhopadhyay’s share ~50%.

27. S. Yalamanchili (PI), M. Bakir (co-PI), S. Mukhopadhyay (co-PI) and Y. Joshi (co-PI); Power-Architecture-Thermal Co-Design (PATCO) for Exascale Node Architectures, Sandia National Lab; Jan 1, 2012 – Dec. 31, 2015; Fund: $360,000. Dr. Mukhopadhyay’s share ~25%.

28. S. Kumar (PI, ME) and S. Mukhopadhyay (co-PI), “Collaborative Research: Energy Efficient Thermal Design of Heterogeneous System with Active Cooling,” National Science Foundation, Fund: $325,744. Dr. Mukhopadhyay’s share: ~50%; Aug 15, 2010 – Aug. 14, 2014.

29. Equipment Grant: K. Schwan (PI), H. Kim (co-PI), S. Mukhopadhyay (co-PI), H. Lee (co-PI), Y. Joshi (co-PI), “II-NEW: GreenIT: Testbeds for Real-time Data Center and Platform Energy and Thermal Management,” National Science Foundation, Jan. 1, 2010 – Dec. 31, 2013, amount $500,000, Dr. Mukhopadhyay’s share ~$125,000 (probe-station for power/thermal characterization).

30. S. Lim (PI) and S. Mukhopadhyay (co-PI) “SHF:Small:3D Integration of Sub-Threshold Multi-core Co-processor for Ultra Lower Power Computing,” National Science Foundation, Sept. 15, 2009 – Aug. 31, 2013, Fund: $450,000, Dr. Mukhopadhyay’s share ~50%.


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31. A. Gavrilovska (SCS), R. Hutchins (OIT), Y. Joshi (ME), H. Kim (SCS), H. H. Lee (ECE), S. Mukhopadhyay (ECE) , S. Pande (SCS), C. Pu (SCS), K. Schwan (SCS), M. Swaminathan (ECE), Y. Wardi (ECE), M. Wolf (SCS), J. Xu (SCS), and S. Yalamanchili (ECE: Coordinator), “GreenIT: IT Technologies for Green Computing,” Georgia Tech Innovation Grant Funding FRP, Total amount $74,923 for 1 year. Dr. Mukhopadhyay received one 1/6th GRA for summer.

E3. As Senior Personnel or Contributor

No data

E4. Pending Proposals

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F. OTHER SCHOLARLY AND CREATIVE ACCOMPLISHMENTS

No data

G. SOCIETAL AND POLICY IMPACTS

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H. OTHER PROFESSIONAL ACTIVITIES

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V. TEACHING

A. COURSES TAUGHT Year Term Course Number Course Title No. Of Students

2015 Spring ECE 8893 Digital system in nanometer nodes 51 2013 Fall ECE 6130 Advanced VLSI Systems 62 2013 Fall ECE 4130 Advanced VLSI Systems 9 2013 Fall ECE 4420 Digital Integrated Circuits 44 2012 Fall ECE 4420 Digital Integrated Circuits 31 2012 Fall ECE 8893 Digital system in nanometer nodes 27 2011 Fall ECE 6130 Advanced VLSI Systems 66 2011 Fall ECE 4130 Advanced VLSI Systems 4 2011 Fall ECE 4420 Digital Integrated Circuits 14 2011 Spring ECE8893 Digital system in nanometer nodes 16 2010 Fall ECE 6130 Advanced VLSI Systems 45 2010 Fall ECE 4130 Advanced VLSI Systems 2 2010 Spring ECE8823 CAD for DFM 12 2010 Spring ECE3060 VLSI and Advanced Digital Design 43 2009 Fall ECE 6130 Advanced VLSI Systems 58


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2009 Fall ECE 4130 Advanced VLSI Systems 1 2009 Summer ECE6430 Digital MOS Design 21 2009 Spring ECE 8893a Digital system in nanometer nodes 14 2008 Fall ECE 6130 Advanced VLSI Systems 31 2008 Spring ECE 6130 Advanced VLSI Systems 30 2008 Spring ECE 4130 Advanced VLSI Systems 3

B. INDIVIDUAL STUDENT GUIDANCE

B1. Ph. D Students B1.a Graduated Students

1. Dr. Francesco Barale, Date of Graduation: Dec. 2010, Thesis Title: Design of Integrated Frequency Synthesizers and Clock-Data Recovery Circuits for 60GHz Wireless Communications; Current Affiliation: Silicon Laboratories, Austin, TX, USA

2. Dr. Jeremy Tolbert, Date of Graduation: August 2012, Thesis Title: Energy-Efficient Digital Design of Reliable, Low-Throughput of Wireless Biomedical Systems; Current Affiliation: Samsung Electronics, Austin, TX, USA

3. Dr. Subho Chatterjee, Date of Graduation: September 2012, Thesis Title: A Design Methodology for Robust, Energy-Efficient, Application-Aware Memory Systems; Current Affiliation: Intel Corp., Hillsboro, OR, USA

4. Dr. Minki Cho, Date of Graduation: September 2012, Thesis Title: Design Methodology To Characterize And Compensate For Process And Temperature Variation In Digital Systems; Current Affiliation: Intel Labs., Hillsboro, OR, USA

5. Dr. Kwanyeob Chae, Date of Graduation: August 2013, Thesis Title: Design Methodologies for Robust Low-Power Digital Systems Under Static and Dynamic Variations; Current Affiliation: Samsung Electronics, Korea,

6. Dr. Denny Lie, Date of Graduation: January 2015, Thesis Title: Design Methodology For Low Power 3D-Integrated Image Sensing System For Network Based Applications; Current Affiliation: Intel Corp, OR

7. Dr. Wen Yueh, Date of Graduation: August 2015, Thesis Title: Modeling, Characterization, and Control of the Electrical-Thermal Interactions in Advanced Packages; Affiliation: Nvidia Corp, Santa Clara, CA

8. Dr. Boris Alexandrov Date of Graduation: August 2015, Thesis Title: Design Methodology for Thermal Management Using Embedded Thermoelectric Devices, Affiliation: Boston Consulting Group, Atlanta, GA.

9. Dr. Amit R. Trivedi Date of Graduation: October 2015, Thesis Title: Ultra Low Power Non-Boolean Computing with Tunneling Field-Effect-Transistors, Affiliation: Assistant Professor, University of Illinois, Chicago, IL..

10. Dr. Sergio Carlo Date of Graduation: October 2015, Thesis Title: Load-aware Power Conversion and Integration for Heterogeneous Systems, Affiliation: Intel Corporation, Hillsboro, OR

11. Dr. Khondker Z. Ahmed Date of Graduation: August 2016, Thesis Title: Power Management Circuits for Energy Harvesting System, Affiliation: Intel Labs, Hillsboro, OR

B1.b In Process 1. Khondker Z. Ahmed (advised since Fall 2011, Expected Graduation: August 2016)


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o Proposal Exam: Fall 2015 (scheduled); Preliminary Exam: Fall 2011 o Thesis Topic: Power Management Circuits for Energy Harvesting System

2. Jae-Ha Kung (advised since Fall 2011, Expected Graduation: December 2016) o Proposal Exam: Fall 2015 (planned); Preliminary Exam: Fall 2011 o Thesis Topic: Energy-efficient Neuromorphic Computing Platforms

3. Duckhwan Kim (advised since Spring 2012, Expected Graduation: August 2017) o Preliminary Exam: Fall 2011 o Thesis Topic: 3D Integration of Neuromorphic Platforms

4. Monodeep Kar (advised since Fall 2012, Expected Graduation: August 2017) o Preliminary Exam: Fall 2012 o Thesis Topic: Integrated Voltage Regulator and Application to Hardware Security

5. Jong-Hwan Ko (advised since Fall 2013, Expected Graduation: August 2018) o Preliminary Exam: Fall 2013 o Thesis Topic: Energy-efficient Wireless Image/Video Sensor

6. Mohammed F. Amir (advised since Fall 2013, Expected Graduation: August 2018) o Preliminary Exam: Fall 2013 o Thesis Topic: Ultra-low-power Memory and CMOS Image Sensor

7. Arvind Singh (advised since Fall 2014, Expected Graduation: August 2019) o Preliminary Exam: Fall 2014 o Thesis Topic: Lightweight Cryptography for Security of Low-power Devices

8. Taesik Na (advised since Fall 2014, Expected Graduation: August 2019) o Preliminary Exam: Fall 2013 o Thesis Topic: Co-design of Integrated Voltage Regulator and Digital Processors

9. Yun Long (advised since Spring 2015, Expected Graduation: August 2019) o Preliminary Exam: Spring 2015 o Thesis Topic: Neuromorphic Computing with Emerging Devices

B2. M. S. Students

B2.a. Graduated with M.S. Thesis 1. Mr. Nikhil Sathe, Date of Graduation: Aug, 2010; Thesis Title: Thermal Modeling in Many-

Core Processors; Current Affiliation: Qualcomm Inc 2. Mr. Muneeb Zia, Date of Graduation: May, 2013; Thesis: SRAM System Design For

Memory Based Computing; Current Affiliation: PhD Student, Georgia Tech 3. Mr. Prashant Nair, Date of Graduation: May, 2013; Thesis: Designing Low Power SRAM

System Using Energy Compression; Current Affiliation: PhD Student, Georgia Tech. 4. Mr. Krishnamurthy Yeleswarapu, Date of Graduation: January, 2014; Thesis Title: TCAD

Simulation Framework for the Study of TSV-device Interaction. 5. Mr. Swarrna K. Parthasarathy, Date of Graduation: December, 2014; Thesis Title: Energy

efficient active cooling of integrated circuits using embedded thermoelectric devices; Current Affiliation: Knowles, Chicago, IL.


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6. Mr. Burhand Muhammad, Date of Graduation: May, 2015; Thesis: Design and implementation of a content aware image processing module on Field Programmable Gate Array (FPGA)

7. Mr. Khondker Z. Ahmed, Date of Graduation: May, 2015; Thesis Title: Low Voltage Autonomous Buck-Boost Regulator For Wide Input Energy Harvesting; Current Affiliation: PhD Student, Georgia Institute of Technology

B3. Undergraduate Students

B3.a Undergraduate Students – Georgia Tech

No Student Semester Topic 1 Anurag Kadasne Fall 2009, Spring 2010 Many-core Thermal Management 2 Andrew Burks Spring 2010 Energy-efficient Wireless EEG system 3 Erik Ronshagen Fall 2010, Spring 2011 Thermal Management 4 Samrat Sinharoy Fall 2012 Low-swing 3D interconnect 5 Chawit Uswachoke Fall 2012 Low-swing 3D interconnect 6 Daniel Besse Spring 2013 Tunnel FET 7 Janani Ramakrishnan Fall 2014, Spring 2015 Cellular Neural Network 8 Huijie Pan Fall 2015 (PURA) Cellular Neural Network

B3.b. UG Students in Summer Undergraduate Research Experience (SURE)

No Student Semester Topic 8 Abner Ayalaa Summer 2010 Wireless Image Transmission: MATLAB Model 9 Erica Nwankwo Summer 2011 MATLAB based Wireless Channel Simulation 10 Leishla Z Ramos Rivera Summer 2012 Image Processing-Unit for A Wireless Sensor Node 11 Luis D. Nieves Summer 2014 Low-power Pre-processing for JPEG Compression 12 Maurisa Orona Summer 2014 Real-Time Image Sensor for JPEG Compression

B3.c. International UG Students from Shastra University, India

No Student Semester Topic 13 Swarrna K. Parthasarathy Spring 2012 Experiment with Thermoelectric Module 14 Karthik Swaminathan Spring 2013 Design of TFET Standard Cell Library 15 Sesha Swaroop, Vempalli Spring 2014 Analysis of Temperature Dependence of TFET 16 Arambakkam Narayanan Spring 2015 Analysis and implementation NOC router for 3D ICs

B4. Service on thesis or dissertation committees

B4.a. Internal (Partial list for since Fall 2010) Student Advisor Proposal Dissertation School Song,William Suahakar Yalamanchili 6/8/15 ECE Pan,Chenyun Azad Naeemi 12/9/14 7/7/15 ECE


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Wu,Jiadong Bo Hong 5/4/15 ECE Paul,Indrani Suahakar Yalamanchili 10/31/14 3/9/15 ECE Panth,Shreepad Sungkyu Lim 7/23/14 3/2/15 ECE Zhimin Wan Yogendra Joshi 1/29/15 ME Chakraborty,Partha John C. Cresslar 1/30/15 ECE Wang,Xian Abhijit Chatterjee 1/12/15 ECE Telikepalli,Satyanarayana Madhavan Swaminathan 1/23/14 11/19/14 ECE Ceyhan,Ahmet Azad Naeemi 9/11/13 10/27/14 ECE Blanco,Andres Gabriel Rincon Mora 9/11/14 ECE Kumar,Vachan Azad Naeemi 1/29/14 9/3/14 ECE Adil,Farhan Jennifer Hasler 12/5/13 7/29/14 ECE Jung,Moongon Sungkyu Lim 4/26/13 2/19/14 ECE Almoosa,Nawaf Suahakar Yalamanchili 6/11/12 1/7/14 ECE Wunderlich,Richard Jennifer Hasler 9/11/13 12/10/13 ECE Saha,Prabir John C. Cresslar 12/2/11 6/3/13 ECE Lee,Young Joon Sungkyu Lim 2/6/12 3/14/13 ECE Onyewuchi,Urenna Miroslav Begovic 2/6/12 11/12/12 ECE Zhao,Xin Sungkyu Lim 12/16/11 9/21/12 ECE Rakheja,Shaloo Azad Naeemi 8/17/12 ECE Athikulwongse,Krit Sungkyu Lim 12/2/11 7/10/12 ECE Kim,Dae Hyun Sungkyu Lim 6/29/11 3/6/12 ECE Bandyopadhyay,Tapobrata Rao Tumala 2/5/11 8/22/11 ECE Sen,Shreyas Abhijit Chatterjee 1/5/11 7/29/11 ECE Zhang,Yun Shyh-Chiang Shen 11/5/10 7/22/11 ECE Kim,Hyung Wook Manos Tentzeris 7/5/10 5/5/11 ECE Kim,Se Marilyn Wolf 1/25/11 11/1/11 ECE Natarajan, Vishwanath Abhijit Chatterjee 10/1/10 ECE

B5. Mentorship of postdoctoral fellows or visiting scholars

No data

C. OTHER TEACHING ACTIVITIES C1. Course Development 1. Digital System in Nanometer Nodes (Graduate)

Description: Current VLSI systems designed in sub-90nm silicon technologies have more than 300 million transistors operating in Gigahertz frequencies. This course discusses the challenges, such as power,


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variability, and reliability, etc. associated with designing these VLSI systems. The different principles and methods explored in both academia and industry to address these challenges are discussed. The course has been taught as a Special Topic for four times.

2. CAD Methodologies for VLSI Design-for-Manufacturability (Graduate, co-designed with S. Lim)

Course Description: The design for manufacturability (DFM) includes a set of techniques to modify the design of VLSI circuits in order to make them more manufacturable and improve reliability. The course has been offered as a Special Topic course in Spring 2010.

3. Physical Foundations of Computer Engineering (Undergraduate Core Course for CmpE Curriculum)

Course Description: Motivated by the concepts presented in “Feynman Lectures on Computation”, this new course will discuss the fundamental requirements in physical implementation of an information processing system and relate that to principles of semiconductor, circuit theory, electromagnetism, and thermodynamics. The connections of the above principles to the performance, energy, and robustness of computing system will be explained to introduce CmpE undergrads to the physics of any computing systems. This is a new core course for the revised undergraduate CmpE curricula. Dr. Mukhopadhyay has conceptualized this course and was involved in defining its materials in collaboration with several other ECE faculty.

C2. Course Improvement

1. Advanced VLSI Systems (ECE6130 and 4130, Graduate and Undergraduate)

Description: This course provides basic concepts on VLSI systems to new graduate students and senior undergraduate students. Since joining Georgia Tech, Dr. Mukhopadhyay has significantly revamped this course leading to tremendous increase in the number of enrollments as well as student satisfaction. The improvements includes increased emphasis on understanding concepts, rather than only practicing problem solving; a redefined project that stressed learning circuit concepts, instead of developing layout skills; and introducing new materials beyond the textbook to introduce newly developed concepts in the industry.

2. Digital MOS ICs (ECE4420, Undergraduate)

Description: This course provides basic concepts on digital circuit design to senior students. Dr. Mukhopadhyay has started teaching this course from Fall 2011. Dr. Mukhopadhyay modified the lectures to stress the understanding of concepts. The homework structures are revamped to introduce separate design homework and analytical homework. The design homework focused on simulation based circuit design problems to learn how to apply simple theory learned in class to complex circuit design problems. The exams are modified to introduce concept-testing short answer questions. The enrollments and student satisfaction have been steadily increasing since Dr. Mukhoadhyay first offered it in Fall 2011 (from 14 students in Fall 2011 to 52 students registered in Phase-I for Fall 2015).

C3. Professional Development/Continuing Education

No data

C4. Other Teaching Activities Tutorials Presented at Conferences

1. Design, Automation, and Test in Europe (DATE), Dresden, Germany, March 24-28, 2014, “Energy-Efficient System Design Through Error-Resilient Computing,” by Saibal Mukhopadhyay, Shidhartha Das, Anand Raghunathan, and Srimat Chakradhar,


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2. Design, Automation, and Test in Europe (DATE), Grenoble, France, March 18-22, 2013, “Energy-efficient Adaptive Circuits and Systems,” by Saibal Mukhopadhyay, Arijit Raychowdhury, Abhijit Chatterjee, and Sudhakar Yalamanchili.

3. International Conference on VLSI Design (VLSI), Pune, India, Jan 5-Jan 10, 2013, “Energy-efficient Adaptive Circuits and Systems,” by Saibal Mukhopadhyay, Swaroop Ghosh, Abhijit Chatterjee, and Sudhakar Yalamanchili.

4. International Test Conference (ITC), Austin, TX, USA, Oct 31-Nov 4, 2010, “Parameter Variations and Low-Power Design: Test Issues and On-chip Calibration/Repair Solutions,” by Rahul Rao, Saibal Mukhopadhyay, Praveen Elakkumanan, and Swarup Bhunia.

5. VLSI Test Symposium (VTS), Santa Cruz, CA, USA, April 19-22, 2010, “Parameter Variations and Low-Power Design: Test Issues and On-chip Calibration/Repair Solutions,” by Rahul Rao, Saibal Mukhopadhyay, Praveen Elakkumanan, and Swarup Bhunia.

6. International Test Conference (ITC), Austin, TX, USA, Nov 1-6, 2009, “Parameter Variations and Self-Calibration/Self-Repair Solutions in Nanometer Technologies,” by Saibal Mukhopadhyay, Rahul Rao, Praveen Elakkumanan, and Swarup Bhunia.

7. IEEE International On-Line Testing Symposium (IOLTS), Sesimbra-Lisbon, Portugal, June 24-26, 2009: “Parameter Variations and Self-Calibration/Self-Repair Solutions in Nanometer Technologies,” by Saibal Mukhopadhyay, Rahul Rao, Praveen Elakkumanan, and Swarup Bhunia

VI. SERVICE A. PROFESSIONAL CONTRIBUTIONS

A1. Editorial Board Memberships • Associate Editor for Elsvier Microelectronics Journal • Corresponding Guest Editor for December 2014 Special Issue in IEEE Journal of Emerging and Selected

Topics in Circuit and Systems (IEEE JETCAS) on “Computing with Emerging Technologies” • Corresponding Guest Editor for March 2015 Special Issue in IEEE Journal of Emerging and Selected

Topics in Circuit and Systems (IEEE JETCAS) on “Computing with Emerging Technologies”

A2. Society Offices, Activities, and Membership

• Senior Member of the Institute of Electrical and Electronics Engineers (IEEE). • IEEE Society Memberships:

o IEEE Electron Devices Society, IEEE Circuits and Systems Society, IEEE Components, Packaging, and Manufacturing Technology Society, and IEEE Solid-State Circuits Society

o IEEE Council on Electronic Design Automation, IEEE Sensors Council, and IEEE Nanotechnology Council

A3. Organization and Chairmanship of Technical Sessions, Workshops and Conferences

• Technical Program Chair for International Symposium on Quality Electronic Design (ISQED), 2016 • Technical Program Co-Chair for International Symposium on Quality Electronic Design (ISQED), 2015 • Organization of Special Sessions at Conferences


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o Design, Automation, and Test in Europe, 2014, Special Session organized by Saibal Mukhopadyay, “Hot Topic: Beyond CMOS Ultra-low-power Computing,”

o International Conference on VLSI Design, Pune, India, Jan 5-Jan 10, 2013, “Embedded Tutorial- Emerging Computing Technologies,”

o International Conference on VLSI Design, Pune, India, Jan 5-Jan 10, 2013, “Embedded Tutorial - Low Power Computing - Reducing the gap between the Physical and Practical Limits,”

• Member of Technical Program Committee of o International Symposium on Quality Electronic Design (ISQED), 2007-2014, Track Chair 2014. o International Symposium on Low Power Electronic Design (ISLPED), 2007, 2010-2014 o International Conference on Computer Aided Design (ICCAD), 2010, 2011, 2012 o IEEE Intl. Conf. on VLSI Design, 2010, 2011 (Track Chair), 2013 (Track Chair). o DAC/ISSCC Student Design Contest (DAC/ISSCC - SDC), 2011 o IEEE International On-Line Test Symposium (IOLTS), 2009-2013. o IEEE Computer Society Annual Symposium on VLSI, 2010, 2011, 2012.

A4. Technical Journal or Conference Referee Activities

• Paper Review for Journals o IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) o IEEE Transactions on VLSI Design (TVLSI) o IEEE Transactions on Electron Devices (TED) o IEEE Transactions on Circuits and Systems –I: Regular Papers (TCAS-I) o IEEE Transactions on Circuits and Systems –II: Express Briefs (TCAS-II) o IEEE Electron Device Letters (EDL) o IEEE Journal of Emerging Topics in Circuits and Systems (JETCAS) o IEEE Transactions on Semiconductor Manufacturing (TSM) o IEEE Transactions on Component, Packaging, and Manufacturing Technology (TCPMT) o IEEE Journal of Solid State Circuits (JSSC) o ACM Journal of Emerging Technologies in Computing

A5. Proposal Panels and Reviews

o Attended two (2) review panels for NSF Smart Health and Wellbeing program. o Attended two (2) review panels for NSF Small Business Innovation Research (SBIR) program

B. PUBLIC AND COMMUNITY SERVICE No data

C. INSTITUTE CONTRIBUTIONS C1. Institute Committee Service

No data


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C2. College Committee Service No data

C3. School Committee Service • ECE Graduate Committee – 2008-2009, 2009-2010 • ECE Graduate Student Recruiting Committee – 2010-2011, 2011-2012, 2012-2013 • ECE Faculty Recruitment Committee – 2014, 2015 • CmpE Undergraduate Curriculum Revision Committee – 2010 • Physics of Computing Committee – 2010-2011

C4. Program Development: Research

• Member of Interconnect and Packaging Center (IPC, since 2010), • Member of Interconnect Focus Center (IFC, 2010-2012), • Thrust leader for the consortium on Power Delivery in Electronics Systems currently being developed.

C5. Program Development: Academic

No data

C6. Other Institute Service Contributions No data

DR. SAIBAL MUKHOPADHYAY ASSOCIATE PROFESSOR SCHOOL...

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