DPSD LAB MANUAL

Digital Lab Manual

Department of ECE| VVCET |

VIDYAA VIKAS COLLEGE OF ENGINEERING AND TECHNOLOGY,

TIRUCHENGODE.

DIGITAL LAB MANUAL

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

Digital Lab Manual


DIGITAL LABORATORY

Digital Lab Manual


Digital Lab Manual


EXTRACT OF ANNA UNIVERSITY SYLLABUS

DIGITAL LABORATORY – CSE

LIST OF EXPERIMENTS

1. Verification of Boolean theorems using digital logic gates

2. Design and implementation of combinational circuits using basic gates for

arbitrary functions, code converters, etc.

3. Design and implementation of 4-bit binary adder / subtractor using basic

gates and MSI devices

4. Design and implementation of parity generator / checker using basic gates

and MSI devices

5. Design and implementation of magnitude comparator

6. Design and implementation of application using multiplexers/Demultiplexers

7. Design and implementation of Shift registers

8. Design and implementation of Synchronous counters

9. Design and implementation of Asynchronous counters

10. Simulation of combinational circuits using Hardware Description Language

(VHDL/ Verilog HDL software required)

11. Simulation of sequential circuits using HDL (VHDL/ Verilog HDL software

required)

Digital Lab Manual


Digital Lab Manual


LAB EXPERIMENTS

Digital Lab Manual


Digital Lab Manual


INTRODUCTION TO COMPONENTS USED

A “Bread-Board” is used in a laboratory for constructing the different circuits

and testing them. This is very useful since here; we do not have to solder the different

components. Soldering, as you know can be very time consuming. Further, we can reuse

the components again and again, since they are not cut and soldered. Let us learn below

how we can use the breadboard for such applications. The breadboard contains a

number of metal clips aligned beneath the array of holes so that when we insert the lead

of a component (say, resistor) inside a hole, the clip grips the lead tightly. Observe the

figure. Fig(a) shows a metal clip before a component inserted, while Fig(b) shows after

the lead inserted. Fig(c) shows a clip which is beneath an array of 5-holes. All the five

holes correspond to one node since all of them are connected together electrically by

the metal clip. That means up to 5 wires can be connected to this single node.

Digital Lab Manual


Multimeter :

A Multimeter is indeed a multiple meter. It measure dc and ac voltages, currents

and in addition resistances in some recent DMM’s we can measure even frequency,

capacitance, etc. Two long probes are used to connect the DMM to a circuit during a

measurement. The central dial knob is rotated to choose the parameter we wish to

measure. When not in use we keep the knob in OFF position.

Digital Lab Manual


Measuring DC Voltage by using Multimeter:

Measuring Resistance Value by using Multimeter:

Digital Lab Manual


Basic Logic Gates:

Digital Lab Manual


Pin Details of Digital Logic Gates:

Digital Lab Manual


Postulates and Theorems of Boolean algebra:

S. No Postulate/Theorem Duality Remarks

1. X + 0 = X X.1 = X -

2. X + X’ = 1 X.X’ = 0 -

3. X + X = X X.X = X -

4. X + 1 = 1 X.0 = 0 -

5. (X’)’ = X - Involution

6. X + Y = Y + X X.Y = Y.X Commutative

7. X + (Y + Z) = (X + Y) + Z X.(Y.Z) = (X.Y).Z Associative

8. X.(Y + Z) = X.Y + X.Z X + (Y.Z) = (X + Y)(X + Z) Distributive

9. (X + Y)’ = X’Y’ (XY)’ = X’ + Y’ DeMorgan’s

Theorem

10. X + XY = X X.(X + Y) = X Absorption

Bit Grouping:

Bit - A single, bivalent unit of binary.

Equivalent to a decimal "digit."

Crumb, Tydbit, or Tayste - Two bits.

Nibble or Nybble - Four bits.

Nickle - Five bits.

Byte - Eight bits.

Deckle - Ten bits.

Playte - Sixteen bits.

Dynner - Thirty-two bits.

Word - (system dependent).

Arithmetic Notations:

Augend + Addend = Sum

Minuend – Subtrahend = Difference

Multiplicand X Multiplier = Product

Dividend / Divisor = Quotient

Digital Lab Manual


Verification of Logic Gates:

Digital Lab Manual


Digital Lab Manual


EXP. NO: 1

VERIFICATION OF BOOLEAN THEOREMS USING DIGITAL LOGIC GATES

Aim:

To verify the truth table of basic Boolean algebric laws by using logic gates.

Components Required:

S.NO COMPONENTS RANGE QUANTITY

1 Digital IC trainer

kit - 1

2 IC

7400 1

7402 1

7404 1

7408 1

7432 1

7486 1

3 Bread board - 1

4 Connecting wires - As required

Theory:

Demorgan’s Theorems

First Theorem:

It states that the complement of a product is equal to the sum of the

complements.

(AB)′′′′ =A′′′′ +B′′′′

Second Theorem:

It states that the complement of a sum is equal to the product of the

complements.

(A+B)′′′′ =A′′′′.B′′′′

Boolean Laws:

Boolean algebra is a mathematical system consisting of a set of two or more

distinct elements, two binary operators denoted by the symbols (+) and (.) and

one unary operator denoted by the symbol either bar (-) or prime (‘). They satisfy

Digital Lab Manual


Digital Lab Manual


the commutative, associative, distributive and absorption properties of the

Boolean algebra.

Commutative Property:

Boolean addition is commutative, given by

A+B=B+A

Boolean algebra is also commutative over multiplication, given by

A.B=B.A

De-Morgan’s Theorem: 1

De-Morgan’s Theorem: 2

Digital Lab Manual


Digital Lab Manual


Associative Property:

The associative property of addition is given by

A+ (B+C) = (A+B) +C

The associative law of multiplication is given by

A. (B.C) = (A.B).C

Distributive Property:

The Boolean addition is distributive over Boolean multiplication, given by

A+BC = (A+B) (A+C)

Boolean multiplication is also distributive over Boolean addition given by

A. (B+C) = A.B+A.C

Realization of circuits for Boolean expression after simplification:

A binary variable can take the value of ‘0’ or ‘1’. A Boolean function is an

expression formed with binary operator OR, AND and a unary operator NOT,

parenthesis function can be 0 or 1.

For example, consider the function

The prime implicants are found by using the elimination of complementary

function. The circuit diagram for the function is drawn using AND.OR and NOT

gates. The output for the corresponding input of A1, A0, B1, BO is calculated and the

truth table is drawn.

Digital Lab Manual


Digital Lab Manual


Procedure:

1. Test the individual ICs with its specified verification table for proper

working.

2. Connections are made as per the circuit/logic diagram.

3. Make sure that the ICs are enabled by giving the suitable Vcc and ground

connections.

4. Apply the logic inputs to the appropriate terminals of the ICs.

5. Observe the logic output for the inputs applied.

6. Verify the observed logic output with the verification/truth table given.

Commutative Law:

Truth Table:

Input Output

A B A+B B+A

0 0 0 0

0 1 1 1

1 0 1 1

1 1 1 1

Associative Law:

Digital Lab Manual


Digital Lab Manual


Truth Table:

Input Output

A B C A+B (A+B)+C B+C A+(B+C)

0 0 0 0 0 0 0

0 0 1 0 1 1 1

0 1 0 1 1 1 1

0 1 1 1 1 1 1

1 0 0 1 1 0 1

1 0 1 1 1 1 1

1 1 0 1 1 1 1

1 1 1 1 1 1 1

Distributive Law:

Truth Table:

Input Output

A B C B+C A.(B+C) A.B A.C A.B+A.C

0 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0

0 1 0 1 0 0 0 0

0 1 1 1 0 0 0 0

1 0 0 0 0 0 0 0

1 0 1 1 1 0 1 1

1 1 0 1 1 1 0 1

1 1 1 1 1 1 1 1

Digital Lab Manual


Digital Lab Manual


Circuit of the IC’s Used:

Result:

Thus the verification of Boolean laws and theorems using digital logic gates

were performed.

Digital Lab Manual


Digital Lab Manual


EXP. NO: 2

DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS USING BASIC

GATES FOR ARBITRARY FUNCTIONS AND CODE CONVERTERS

Aim:

To design and implement a combinational circuit to convert gray code to

Binary and BCD to Excess-3 – vice versa.



1 Digital IC Trainer kit - 1

2 IC

7404 1

7408 2

7432 1

7486 1


4 Bread board - 1

Theory:

Binary to Gray – Vice versa:

The binary coded decimal (BCD) code is one of the early computer codes.

Each decimal digit is independently converted to a 4 bit binary number. A binary

code will have some unassigned bit combinations if the number of elements in the

set is not a multiple power of 2. The 10 decimal digits form such a set. A binary

code that distinguishes among 10 elements must contain at least four bits, but 6

out of the 16 possible combinations remain unassigned. Different binary codes

can be obtained by arranging four bits in 10 distinct combinations. The code most

commonly used for the decimal digits is the straight binary assignment. This is

called binary coded decimal.

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Digital Lab Manual


The gray code is used in applications where the normal sequence of binary

numbers may produce an error or ambiguity during the transition from one

number to the next. If binary numbers are used, a change from 0111 to 1100 may

produce an intermediate erroneous number 1001 if the rightmost bit takes

longer to change in value than the other three bits. The gray code eliminates this

problem since only one bit changes in value during any transition between two

numbers.

Truth Table (Binary to Gray):

Binary (Input) Gray (Output)

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

Digital Lab Manual


Digital Lab Manual


BCD to Excess 3 – Vice versa:

Excess 3 code is a modified form of a BCD number. The excess 3 code can be

derived from the natural BCD code by adding 3 to each coded number. For

example, decimal 6 can be represented in BCD as 0110. Now adding 3 to the given

number yield equivalent excess 3 code i.e., 6 + 3 = 9 �� 0110 + 0011 = 1001. Thus

for the entire sequence of BCD value (i.e., 0 to 9) excess 3 equivalent table should

be made so that the realization of Boolean expression for the circuit

implementation is feasible. In the reverse process of designing a code converter

from excess 3 to BCD the same procedure is followed. Here are the general steps

to be followed while going for a code converter design,

– start with the specification of the circuit to be designed.

– Identify the inputs and outputs

– Derive truth table

– Obtain simplified Boolean equations

– Draw the logic diagram

– Check the design to verify correctness with the truth/verification table.

Digital Lab Manual


Digital Lab Manual


Logic Diagram:

Pin Diagram:

Procedure:


working.



connections.




Digital Lab Manual


Digital Lab Manual


Truth Table (Gray to Binary):

Gray (Input) Binary (Output)

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

1 0 0 0 1 1 1 1

1 0 0 1 1 1 1 0

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 0 1 0

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Digital Lab Manual


Logic Diagram:

Truth Table:

Decimal

Value

BCD Input Excess 3 output

A B C D W X Y z

0 0 0 0 0 0 0 1 1

1 0 0 0 1 0 1 0 0

2 0 0 1 0 0 1 0 1

3 0 0 1 1 0 1 1 0

4 0 1 0 0 0 1 1 1

5 0 1 0 1 1 0 0 0

6 0 1 1 0 1 0 0 1

7 0 1 1 1 1 0 1 0

8 1 0 0 0 1 0 1 1

9 1 0 0 1 1 1 0 0

Digital Lab Manual


Digital Lab Manual


Realization of Boolean Expression for BCD to Excess 3 Converter:

Circuit Diagram:

Digital Lab Manual


Digital Lab Manual


Truth Table:

Decimal

Value

Excess 3 Input BCD Output

W X Y z A B C D

0 0 0 1 1 0 0 0 0

1 0 1 0 0 0 0 0 1

2 0 1 0 1 0 0 1 0

3 0 1 1 0 0 0 1 1

4 0 1 1 1 0 1 0 0

5 1 0 0 0 0 1 0 1

6 1 0 0 1 0 1 1 0

7 1 0 1 0 0 1 1 1

8 1 0 1 1 1 0 0 0

9 1 1 0 0 1 0 0 1

Realization of Boolean Expression for Excess 3 to BCD Converter:

Digital Lab Manual


Digital Lab Manual


Circuit Diagram:

Result:

Thus the combinational circuit for an arbitrary function, code converter

using logic gates was designed, implemented and tested its performance with

truth table.

Digital Lab Manual


Digital Lab Manual


EXP. NO: 3

DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER / SUBTRACTOR USING

MSI DEVICES

Aim:

To design and implement a four bit binary adder / subtractor using MSI

devices.



1 IC trainer kit - 1

2 IC’s 7483 1

7486 1

3 Connecting wires - -

Theory:

Digital computers perform a variety of information processing tasks.

Among the functions encountered are the various arithmetic operations. The

most basic arithmetic operation is the addition of two binary digits. This simple

addition consists of four possible elementary operations: 0+0=0, 0+1=1, 1+0=0

and 1+1=10.

A binary adder-subtractor is a combinational circuit that performs the

arithmetic operations of addition and subtraction with binary numbers. A

combinational circuit that performs the addition of two bits is called half adder.

One that performs the addition of three bits is a full adder. A binary adder is a

digital circuit that produces the arithmetic sum of two binary numbers.

Procedure:

1. Connect the circuit as per the circuit diagram.

2. Power supply is switched ON and a voltage of 5v is maintained.

3. Four bit binary number is given and verifies the sum result.

4. If the adder or subtractor signal is low addition is performed.

5. If the adder or subtractor signal is high subtractor result is verified.

Digital Lab Manual


Digital Lab Manual


Verification Table:

Terminology Input Variables Binary inputs

Augend A3 A2 A1 A0 1 0 0 1

Addend B3 B2 B1 B0 1 0 0 0

Results Cin Cout 1

Addition 0 1 0 1

Subtraction 0 0 0 1

Result:

Thus the 4 bit parallel adder/subtractor was implemented and tested using

the MSI device – IC 7483.

Digital Lab Manual


Digital Lab Manual


EXP. NO: 4

DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER

Aim:

To design and implement the parity generator and checker using logic

gates and verify its performance with the verification table.



1 Digital IC Trainer

kit - 1

2 IC

7486 1

7474 2

7404 1


4 Bread board - 1

Theory:

Parity generator:

A parity bit is a scheme of detecting error during transmitting of binary

information. A parity bit is an extra bit included with a binary message to make

the number of 1’s either odd or even.

Parity generators are used in digital transmission system for the errorless

transmission of digital data. A parity bit is added to the data before the

transmission and it will be checked for the correctness at the receiver end. There

are two types of parity systems, even parity and odd parity. In the even parity

system if the number of 1’s in the data word is odd, a 1 will be added as a parity

bit to the data to make total number of 1’s even. If the number of 1’s even, a 0 bit

will be added. In the odd parity system if the number of 1’s in the data word is

odd, a 0 will be added to make the number of 1’s odd. Otherwise, a 1 is added to

make it odd. The circuit shown in the figure is used as a parity generator as well

as a checker. ABCD is the 4-bit data word. Pi and Po are the parity input and parity

output respectively.

Digital Lab Manual


Digital Lab Manual


The working of the circuit can be concluded as follows,

Work as a Parity generator:

To generate an odd parity bit for ABCD, Pi must be made 0.

To generate an even parity bit for ABCD, Pi must be made1.

Work as a parity checker:

If the parity of ABCD Pi is odd, Po will be 0.

If the parity of ABCD Pi is even, Po will be 1.

Circuit Diagram:

Pin Diagrams:

Digital Lab Manual


Digital Lab Manual


The message, including the parity bit, is transmitted and then checked at

the receiving end for errors. An error detected if the checked parity does not

correspond with the one transmitted. The circuit that generates the parity bit in

the transmitter is called a parity generator. The circuit that checks the parity in

the receiver is called parity checker. In even parity the added parity bit will make

the total number of 1s an even amount. In odd parity the added parity bit will

make the total number of 1s an odd amount.

Procedure:


working.



connections.




Digital Lab Manual


Digital Lab Manual


Truth Table for Even Parity Checker:

4 – BIT DATA RECEIVED PARITY ERROR

CHECK

A B C D PEC

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0

Circuit Diagram:

Digital Lab Manual


Digital Lab Manual


K-Map Simplication for Even Parity Checker:

Result:

Thus the Parity Generator was designed, implemented using logic gates

and its performance was verified.

Digital Lab Manual


Digital Lab Manual


EXP. NO : 5

DESIGN AND IMPLEMENTATION OF 2 – BIT MAGNITUDE COMPARATOR

AIM:

To design and implement a 2-bit magnitude comparator using logic gates.

COMPONENTS REQUIRED:


1 Digital Trainer Kit - 1

2 IC’s

7404 1

7486 1

7408 3

7432 1

3 Connecting Wires /

Patch Cords -

As

required

4. Bread board - 1

THEORY:

The comparison of two numbers is an operation that determines if one

number is greater than, less than, or equal to the other number. A magnitude

comparator is a combinational circuit that compares the two numbers, A and B,

and determines their relative magnitude.

The circuit for comparing two n-bit numbers has 2n entries in the truth

table and becomes too cumbersome even with n=3. On the other hand

comparator circuits possess a certain amount of regularity. The algorithm is a

direct application of the procedure a person uses to compare the relative

magnitudes of two numbers. Consider two numbers, A and B, with four digits each

consider

A=A3A2A1A0

B=B3B2B1B0

The two numbers are equal if all pairs of significant digits are equal: A3=B3,

A2=B2, A1=B1 and A0=B0. When the numbers are binary, the digits are either 0 or 1,

and the equality relation of each pair of bits can be expressed logically with an EX-

OR function

xi =Ai Bi + Ai ′′′′ Bi

′′′′ for i=0,1,2,3

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Digital Lab Manual


The binary variables A=B=X1X0 =1.

A>B= Ai Bi′′′′ + X1 A0 B0

′′′′

A<B = Ai ′′′′ Bi + X1 A0 B0

Truth Table (2 – Bit magnitude Comparator):

Input Output

A1 A0 B1 B0 Ai = Bi Ai > Bi Ai < Bi

0 0 0 0 1 0 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 0 1 0

0 1 0 1 1 0 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 0 1 0

1 0 0 1 0 1 0

1 0 1 0 1 0 0

1 0 1 1 0 0 1

1 1 0 0 0 1 0

1 1 0 1 0 1 0

1 1 1 0 0 1 0

1 1 1 1 1 0 0

Digital Lab Manual


Digital Lab Manual


Procedure:


working.



connections.




RESULT:

Thus the 2 bit magnitude comparator was constructed using logic gates and

verified with its truth table.

Digital Lab Manual


Digital Lab Manual


EXP. NO: 6

DESIGN AND IMPLEMENTATION OF APPLICATION USING MULTIPLEXERS

Aim:

To design and implement the combinational logic using multiplexers

Components required:

S.

No Components Name Range Type Quantity

1 Digital IC trainer kit - - 1

2 IC - 7408 2

3 IC - 7404 1

4 IC - 7432 1

5 Bread Board - - 1

6 Connecting wires - - As required

Theory:

The Block diagram shows the implementation of Boolean function using

4:1 multiplexer. The implementation table is nothing but the list of the inputs of

the multiplexer and under them list of all the minterms in two columns. The first

column lists all the minterms where least significant variable is complemented

(C’), and the second column lists all the minterms with least significant variable is

un-complemented (C).

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Digital Lab Manual


The minterms given in the function are circled and then each row is

inspected separately as follows.

� If the two minterms in a row are not circled, 0 is applied to

corresponding multiplexer input.

� If the two minterms in a row are circled, 1 is applied to corresponding

multiplexer input.

� If the minterm in the column 1 is circled, least significant variable is

complemented (C’) and applied to the corresponding multiplexer

input.

� If the minterm in the column 2 is circled, least significant variable is

un-complemented (C) and applied to the corresponding multiplexer

input.

Procedure:


working.



connections.




Result:

Thus the implementation of the given Boolean function using multiplexer

was designed, implemented and verified with its truth table.

Digital Lab Manual


Digital Lab Manual


EXP. NO : 7

DESIGN AND IMPLEMENTATION OF SHIFT REGISTERS

Aim:

To design, implement and verify the functioning of shift right registers (all

types) using D flip-flop.




kit - 1

2 ICs

7474 2

7408 2

7404 1

7432 1

3 Connecting wires - -

4 Bread Board - 1

Theory:

A register that is used to store binary information is known as a memory

register. A register capable of shifting binary information either to the right or the

left is called a shift register. Shift registers are classified into four types,

1. Serial-in Serial-out (SISO)

2. Serial-in Parallel-out (SIPO)

3. Parallel-in Serial-out (PISO)

4. Parallel-in Parallel-out (PIPO)

Serial-in Serial-out (SISO):

This type of shift registers accepts data serially, i.e., one bit at a time on a

single input line. It produces the stored information on its single output and the

output also in serial form. Data may be shifted left (from low to high order bits)

using shift-left register or shifted right (from high to low order bits) using shift-

right register.

Digital Lab Manual


Digital Lab Manual


Serial-in Parallel-out (SIPO):

It consists of one serial input, and outputs are taken from all the flip-flop

simultaneously in parallel. In this register, data is shifted in serially but shifted

out in parallel. In order to shift the data out in parallel, it is necessary to have all

the data available at the outputs at the same time. Once the data is stored, each bit

appears on its respective output line and all the bits are available simultaneously,

rather than on a bit by bit basis as with the serial output.

Parallel-in Serial-out (PISO):

This type of shift register accepts data parallel, i.e., the bits are entered

simultaneously into their respective flip-flops rather than a bit-by-bit basis on

one line.

Circuit Diagram: Parallel-in Serial-out shift Register

Digital Lab Manual


Digital Lab Manual


Circuit Diagram: Parallel IN Parallel OUT shift Register

Parallel-in Parallel-out (PIPO):

In PIPO, data inputs can be shifted either in or out of the register in parallel.

Procedure:


working.



connections.




Pin Diagram:

Digital Lab Manual


Digital Lab Manual


Verification Table:

Result:

Thus the shift registers using D flip-flop were implemented and studied

their operation in 4 different modes.

Digital Lab Manual


Digital Lab Manual


EXP. NO: 8

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER

Aim:

To design and implement a 3-bit synchronous binary up and down counter

using JK flip-flop.



1 Digital Trainer Kit - 1

2 IC’s

7476 2

7408 1

7432 1


4 Bread Board - 1

Theory:

A Synchronous counter is also called parallel counter. In this counter the

clock inputs of all the flip-flops are connected together so that the input clock

signal is applied simultaneously to each flip-flop. Also, only the LSB flip-flop C has

its J and K inputs connected permanently to Vcc while the J and K inputs of the

other flip-flops are driven by some combination of flip-flop outputs.

3 – Bit Synchronous Binary UP Counter:

The J and K inputs of the flip-flop B are connected to with QC. The J and K

inputs of the flip-flop A, are connected with AND operated output of QC and QB.

The flip-flop C changes its state when with the occurrence of negative transition at

each clock pulse. The flip-flop B changes its state when QC = 1 and when there is

negative transition at clock input. Flip-flop A changes its state when QC = QB

= 1

and when there is negative transition at clock input.

3 – Bit Synchronous Binary DOWN Counter:

The J and K inputs of the flip-flop B are connected to with QC’. The J and K

inputs of the flip-flop A, are connected with AND operated output of QC’ and QB’.

The flip-flop C changes its state when with the occurrence of negative transition at

Digital Lab Manual


Digital Lab Manual


each clock pulse. The flip-flop B changes its state when QC’ = 1 and when there is

negative transition at clock input. Flip-flop A changes its state when QC’ = QB’ = 1

and when there is negative transition at clock input.

Circuit Diagram:

Digital Lab Manual


Digital Lab Manual


Procedure:


working.



connections.




Pin Diagram:

State Table (3 – bit synchronous binary DOWN counter)

Present State Next State JK Flip-Flop Inputs

A B C A+ B+ C+ JA KA JB KB JC KC

0 0 0 1 1 1 1 X 1 X 1 X

0 0 1 0 0 0 0 X 0 X X 1

0 1 0 0 0 1 0 X X 1 1 X

0 1 1 0 1 0 0 X X 0 X 1

1 0 0 0 1 1 X 1 1 X 1 X

1 0 1 1 0 0 X 0 0 X X 1

1 1 0 1 0 1 X 0 X 1 1 X

1 1 1 1 1 0 X 0 X 0 X 1

Digital Lab Manual


Digital Lab Manual


JK Excitation Table:

Qn Qn+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Circuit Diagram:

Digital Lab Manual


Digital Lab Manual


State Table:

Present State Next State ‘T’ input

D C B A D+ C+ B+ A+ TD TC TB TA

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 1 0 0 1 0 0 0 1 1

0 0 1 0 0 0 1 1 0 0 0 1

0 0 1 1 0 1 0 0 0 1 1 1

0 1 0 0 0 1 0 1 0 0 0 1

0 1 0 1 0 1 1 0 0 0 1 1

0 1 1 0 0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 0 1 1 1 1

1 0 0 0 1 0 0 1 0 0 0 1

1 0 0 1 0 0 0 0 1 0 0 1

Result:

Thus the synchronous up and down counters were constructed and tested

the operations with the help of their verification tables.

Digital Lab Manual


Digital Lab Manual


EXP. NO: 9

DESIGN AND IMPLEMENTATION OF ASYNCHRONOUS COUNTER

Aim:

To design and implement a 4-bit asynchronous binary up and down

counter using JK flip-flop.




kit - 1

2

IC

7476 2

3 7400 1

4 - 1

5 Bread board - 1


Theory:

A counter, by function, is a sequential circuit consisting of a set of flip-flops

connected in a suitable manner to count the sequence of the input pulses

presented to it digital form. An asynchronous counter, each flip-flop is triggered

by the output from the previous flip-flop which limits its speed of operation. The

settling time in asynchronous counters, is the cumulative sum of the individual

settling times of flip-flops. It is also called a serial counter.

The asynchronous counter is the simplest in terms of logical operations,

and is therefore the easiest to design. In this counter, all the flip-flops are not

under the control of a single clock. Here, the clock pulse is applied to the first flip-

flop, i.e. the least significant bit stage of the counter, and the successive flip-flop is

triggered by the output is constructed using clocked JK flip-flops. The system

clock, a square wave, drives flip-flop A (LSB). The output of A drives flip-flop B,

the output of B drives flip-flop C. all the J and K inputs connected to Vcc (High (1)),

which means that each flip-flop toggles on the edge (-ve) clock pulse.

Consider initially all flip-flops to be in the logical 0 state (i.e.

QA=QB=QC=QD=0). A negative transition in the clock input which drives flip-flop A

Digital Lab Manual


Digital Lab Manual


causes QA to change from 0 to 1. Flip-flop B doesn’t change its state since it is also

requires negative transition at its clock input, i.e. it requires its clock input (QA) to

change from 1 to 0. With arrival of second clock pulse to flip-flop A, QA goes from 1

to 0. This change of state creates the negative going edge needed to trigger flip-

flop B, and thus QB goes from 0 to 1. Before the arrival of the 16th clock pulse, all

the flip-flops are in the logical 1 state. Clock pulse 16 causes QA, QB, QC and QD to go

logical 0 state in turn.

Verification Table (4 bit binary ripple down counter):

Clock

Pulse Q3 Q2 Q1 Q0

0 1 1 1 1

1 1 1 1 0

2 1 1 0 1

3 1 1 0 0

4 1 0 1 1

5 1 0 1 0

6 1 0 0 1

7 1 0 0 0

8 0 1 1 1

9 0 1 1 0

10 0 1 0 1

11 0 1 0 0

12 0 0 1 1

13 0 0 1 0

14 0 0 0 1

15 0 0 0 0

Digital Lab Manual


Digital Lab Manual


Circuit Diagram:

Procedure:


working.



connections.




Digital Lab Manual


Digital Lab Manual


Pin Diagram:

Verification Table (BCD ripple up counter):

Clock

Pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

Digital Lab Manual


Digital Lab Manual


Circuit Diagram:

Result:

Thus the asynchronous up, down and BCD counters were constructed and

tested the operations with the help of their verification tables.

Digital Lab Manual


Digital Lab Manual


EXP. NO: 10

HDL FOR COMBINATIONAL LOGIC

Aim:

To write a VHDL code for the combinational circuits given below and

simulate the result using EDA tool.

1. Logic Gates (OR , NAND and EX-OR)

2. Half adder and Full adder


S.No Component Name Range / Type Quantity

1 Personal Computer - 1

2 EDA Tool

(ModelSim 5.5e) - -

Theory:

The basic steps involved in the Digital System Design are,

1. Specify the desired behavior of the circuit. 2. Synthesize the circuit.

3. Implement the circuit.

4. Test the circuit to check whether the desired specifications meet.

But as the size and complexity of digital system increase, they cannot be

designed manually because their design becomes highly complex. At their most

detailed level, they may consist of millions of elements (Transistors or logic

gates). So, Computer aided design (CAD) tools are used in design of digital

systems. One such a tool is a Hardware Description Language (HDL).

HDL describes the hardware of digital systems. This description is in

textual form. The Boolean expressions, logic diagrams and digital circuits (Simple

and Complex) can be represented using HDL.

� The HDL provides the digital designer with a means of describing a digital

system at a wide range of levels of abstraction and at the same time,

provides access to computer aided design tools to aid in the design process

at these levels.

� The HDL represents digital systems in the form of documentation which

can understand by human as well as computers.

� It allows hardware designers to express their design with behavioral

constructs. An abstract representation helps the designer explore

Digital Lab Manual


Digital Lab Manual


architectural alternatives through simulations and to detect design

bottlenecks before detailed design begins.

� The HDL makes it easy to exchange the ideas between the designers.

� It resembles a programming language, but the orientation of the HDL is

specifically towards describing hardware structures and behavior. The

storage, retrieval and processing of programs written using HDL can be

performed easily and efficiently.

� HDL‘s are used to describe hardware for the purpose of simulation,

modelling, testing and documentation.

VHDL for full adder – Structural Model

-- Library Declaration

library ieee;

use ieee.std_logic_1164.all;

use work.all;

-- Entity Declaration

entity fa is

port (a,b,c:in std_logic;

sum,cout: out std_logic);

end fa;

-- Architecture Declaration – Structural Model

architecture arc_fa of fa is

component ha

port(a,b:in std_logic;

s,c:out std_logic);

end component;

component gor

port(a,b:in std_logic;

c:out std_logic);

end component;

Digital Lab Manual


Digital Lab Manual


signal s1,c1,c2:std_logic;

begin

ha1:ha port map(a,b,s1,c1);

ha2:ha port map(s1,c,sum,c2);

or1:gor port map(c1,c2,cout);

end arc_fa;

VHDL for half adder – Data Flow Model

library ieee;

use ieee.std_logic_1164.all;

entity ha is

port ( a,b: in std_logic;

s,c: out std_logic);

end ha;

architecture arc_ha of ha is

begin

s <= a xor b;

c <= a and b;

end arc_ha;

Procedure:

1. Click the ModelSim SE 5.5e icon to start the simulation of VHDL code.

2. Select create a project options given on the welcome screen in order to

create a new project otherwise choose open a project to open the existing

project.

3. Proper project name should be given along with the location to save the

project in the create project window.

4. In the main window go to file �� New �� Source �� VHDL to get in to the

source editor window.

Digital Lab Manual


Digital Lab Manual


5. Enter the VHDL source code on that source editor window and save with

the extension .vhd in the project (project created) folder and location

specified previously.

6. Select file �� compile in the source editor window for compiling the written

code. If there is an error debug the error, save and compile again.

7. Load the design by selecting Design �� load design in the main window

after successful compilation of the VHDL codes.

8. Select signals from the view menu of the main window for selecting the

signals.

9. In signal window, choose edit �� force / clock for applying the appropriate

input levels for the signals selected.

10. Select view �� wave �� signals in design to view the response of the design

(Wave form) with the help of run option from the signal window.

11. Continue the simulation for different input levels with the procedure stated

above.

Result:

Thus the VHDL Code for the Combinational circuits was developed and

simulated using Electronic Design Automation tool.

Digital Lab Manual


Digital Lab Manual


EXP. NO : 11

HDL FOR SEQUENTIAL LOGIC

Aim:

To write a VHDL code for the sequential circuits given below and simulate

the result using EDA tool.

1. D flip – flop 2. Synchronous UP / DOWN Counter


S.No Component Name Range / Type Quantity

1 Personal Computer - 1

2 EDA Tool

(ModelSim 5.5e) - -

Theory:

The basic steps involved in the Digital System Design are,

1. Specify the desired behavior of the circuit.

2. Synthesize the circuit.

3. Implement the circuit.

4. Test the circuit to check whether the desired specifications meet.

But as the size and complexity of digital system increase, they cannot be

designed manually because their design becomes highly complex. At their most

detailed level, they may consist of millions of elements (Transistors or logic

gates). So, Computer aided design (CAD) tools are used in design of digital

systems. One such a tool is a Hardware Description Language (HDL).

HDL describes the hardware of digital systems. This description is in

textual form. The Boolean expressions, logic diagrams and digital circuits can be

represented using HDL.

� The HDL provides the digital designer with a means of describing a digital

system at a wide range of levels of abstraction and at the same time,

provides access to computer aided design tools to aid in the design process

at these levels.

� The HDL represents digital systems in the form of documentation which

can understand by human as well as computers.

� It allows hardware designers to express their design with behavioral

constructs. An abstract representation helps the designer explore

Digital Lab Manual


Digital Lab Manual


architectural alternatives through simulations and to detect design

bottlenecks before detailed design begins.

� The HDL makes it easy to exchange the ideas between the designers.

� It resembles a programming language, but the orientation of the HDL is

specifically towards describing hardware structures and behavior. The

storage, retrieval and processing of programs written using HDL can be

performed easily and efficiently.

� HDL‘s are used to describe hardware for the purpose of simulation,

modelling, testing and documentation.

Procedure:

1. Click the ModelSim SE 5.5e icon to start the simulation of VHDL code.

2. Select create a project options given on the welcome screen in order to

create a new project otherwise choose open a project to open the existing

project.

3. Proper project name should be given along with the location to save the

project in the create project window.

4. In the main window go to file �� New �� Source �� VHDL to get in to the

source editor window.

5. Enter the VHDL source code on that source editor window and save with

the extension .vhd in the project (project created) folder and location

specified previously.

6. Select file �� compile in the source editor window for compiling the written

code. If there is an error debug the error, save and compile again.

7. Load the design by selecting Design �� load design in the main window

after successful compilation of the VHDL codes.

8. Select signals from the view menu of the main window for selecting the

signals.

9. In signal window, choose edit �� force / clock for applying the appropriate

input levels for the signals selected.

10. Select view �� wave �� signals in design to view the response of the design

with the help of run option from the signal window and continue.

Result:

Thus the VHDL Code for the Sequential circuits was developed and

simulated using EDA tool.

DPSD LAB MANUAL

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