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Downscaling of self-aligned, all-printedpolymer thin-film transistors

YONG-YOUNG NOH, NI ZHAO, MARIO CAIRONI AND HENNING SIRRINGHAUS*Cavendish Laboratory, University of Cambridge, JJ Thomson Avenue, Cambridge CB3 0HE, UK

*e-mail: hs220@cam.ac.uk

Published online: 18 November 2007; doi:10.1038/nnano.2007.365

Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it has the disadvantages of poorresolution, large overlap capacitances, and film thickness limitations, resulting in slow circuit speeds and high operating voltages.Here, we demonstrate a self-aligned printing approach that allows downscaling of printed organic thin-film transistors tochannel lengths of 100 –400 nm. The use of a crosslinkable polymer gate dielectric with 30 – 50 nm thickness ensures that basicscaling requirements are fulfilled and that operating voltages are below 5 V. The device architecture minimizes contact resistanceeffects, enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes parasiticoverlap capacitance to values as low as 0.2 –0.6 pF mm21, and allows transition frequencies of fT 5 1.6 MHz to be reached. Ourself-aligned process provides a way to improve the performance of printed organic transistor circuits by downscaling, whileremaining compatible with the requirements of large-area, flexible electronics manufacturing.

Manufacturing of organic thin-film transistors (OTFTs) by acombination of low-cost, large-area solution-processing and direct-write printing is emerging as a powerful enabling solution toembedding electronic functionality into flexible plastic substrates.Applications requiring modest transistor performance, such asflexible active-matrix displays, are entering the advanced stages ofindustrial commercialization1. However, for more demandingcircuit applications, such as standard compatible radio-frequency(RF) identification tags (RFID) printed directly onto productpackaging, a level of transistor performance is required that cannotbe achieved using currently available materials and manufacturingtechnology. This is in spite of significant enhancements in recentyears of the field-effect mobility of organic semiconductors tolevels of 0.1–1 cm2 V21 s21 (refs 2–4). Although a relatively fastswitching operation has been demonstrated in model circuitsmade by high-resolution photolithography5,6, the relatively poorresolution of volume printing techniques such as inkjet printing7,offset printing8, and gravure or flexographic printing9 haslimited the channel lengths achievable in all-printed OTFTs toL ¼ 10–100 mm, resulting in much lower (and insufficient) speedsof 1–100 Hz and high operating voltages of 20–100 V.

One approach to overcoming these serious limitations is toimitate the approach of improving performance by downscaling,which the silicon industry has adopted for the last 40 yearsand that has led to the channel length of silicon metal-oxide/semiconductor field-effect transistors (MOSFETs)shrinking in size from around 1 mm in 1985 to 60 nm in 2007,with associated dramatic improvements in integration density,power dissipation per transistor and circuit speed10. However, thedownscaling of OTFTs is challenging, not only because thescaling physics of sub-micrometre TFT architectures is much lesswell understood than that of MOSFETs11. Although, in principle,techniques for defining sub-micrometre channel lengths L byprinting are available12,13, these will have to be integrated into aprinting process capable of scaling down the dimensions of all

critical layers and feature sizes, such as gate dielectric thicknessand overlap dimensions that determine the transition frequencyfT of the transistors. To remain compatible with large-areasolution-based manufacturing, the fabrication process for aprinted downscaled OTFT will have to be entirely self-aligned;that is, it will need to be insensitive to any layer-to-layermisalignments that are inevitable in large-area manufacturing onflexible substrates. Here, we demonstrate downscaled, high-performance printed OTFTs with thin-polymer gate insulators(�30 nm) operating below 5 V, fabricated by a fully self-alignedinkjet printing process. In this work, we focus on improving thefT of the transistors by downscaling, but make no attempt toreduce the substrate area per transistor. In fact, in contrast withsilicon integrated circuits, many applications of printedelectronics are large-area applications in which the number oftransistors needing to be integrated within a certain substratearea (defined, for example, by the size of the RF antenna in thecase of an RFID tag) is small and the cost of the substrate is low.

We use a top-gate TFT architecture with source–drainelectrodes fabricated by the recently reported self-aligned printing(SAP) technique12. With this method, sub-micrometre channellengths can be defined by inkjet printing gold nanoparticles ontothe surface of a previously printed or otherwise defined firstelectrode pattern and causing the ink to flow off the surface of thefirst electrode pattern by modifying its surface with a hydrophobicself-assembled monolayer (SAM) such as 1H,1H,2H,2H-perfluorodecanethiol (PFDT) (Fig. 1a; see Methods). After inkflow-off and drying, a small gap is formed between the twoconducting electrodes. The length L of the gap can be controlledin a range between 60 and 400 nm by varying the processconditions, such as the rate of solvent evaporation or therepulsive force between the ink and modified surface14 (Fig. 1b,c).The patterning yield and uniformity is high12 (see SupplementaryInformation, Fig. S1a). The conductivity of the gold nanoparticleelectrodes exceeded �104 S cm21 after sintering at 250 8C for 1 h

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(see Supplementary Information, Fig. S1e). Devices are completedby solution-deposition of the polymer semiconductor, thepolymer gate dielectric and a top gate electrode.

One of the most important requirements for a sub-micrometreTFT is a gate dielectric layer that can be made sufficiently thin tomeet basic scaling requirements. Insufficient scaling of gatedielectric thickness leads to severe degradation of deviceperformance due to short-channel effects, such as loss of current

saturation (as seen in our previously reported SAP devices12,14;see Supplementary Information, Fig. S1c,d). Several researchgroups have reported robust crosslinkable polymers with lowfree volume as thin gate insulators (.15 nm) in a bottom-gatestructure15–18. There are problems in applying these polymers tothe top-gate architecture needed here. First they require a highcuring temperature (typically over 150 8C for 30 min) that resultsin damage to the underlying semiconductor film. Second, it is

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F-SAMBare AuH-SAMOCH3-SAMCN-SAM

SiSiCl

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Figure 2 Thin polymer gate dielectrics and device scaling. a, A difunctional chlorosilane compound (blue, left) reacts with water to form a siloxane network

(blue, right) that physically—rather than chemically—crosslinks chains of poly(methyl methacrylate), PMMA (red), to give a crosslinked composite material.

b, Leakage current density versus applied voltage of C-PMMA polymer films sandwiched between gold electrodes. c, Output characteristics of SAP poly(dioctylfluorene-co-

bithiophene) (F8T2)/PMMA (gate dielectric thickness, d ¼ 100 nm) FET with different channel lengths (L � 100 nm (black line), 300 nm (red line) and 400 nm (green

line)). The measured drain current is scaled by multiplying by the channel length. We also show the scaled output characteristics of a 20-mm channel length F8T2

transistor for comparison (blue line). The source and drain gold electrodes were modified with 4-(trifluoromethyl)thiophenol (F-SAM) to reduce contact resistance.

d, Transfer characteristics (VD ¼ 210 V) of SAP F8T2/PMMA transistors (W ¼ 500 mm, L ¼ 200 nm) with various SAM-modified source and drain electrodes.

First goldelectrode

Second goldelectrode

SAM

Glass substrate

Printed goldelectrode

Evaporated goldelectrode

1 μm

Figure 1 Self-aligned inkjet printing (SAP). a, Schematic of the SAP process. The dashed line indicates the initial position of the printed gold nanoparticle ink

before dewetting from the hydrophobic surface layer on the first electrode. b,c, Atomic force microscopy (2 mm � 2 mm) (b) and scanning electron microscopy

(c) images of the short channel between a printed second and an evaporated first gold electrode (as shown in the Supplementary Information, Fig. S1a). In b the

channel length L between the two electrodes is on the order of 50 nm. In c print conditions were selected to produce a wider channel L ¼ 400 nm.

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necessary to use an orthogonal solvent that avoids swelling anddissolution of the underlying semiconducting polymer. Toovercome these problems we selected a crosslinked polymerblend gate dielectric (C-PMMA) with poly(methylmethacrylate)(PMMA) as a base polymer, 1,6-bis(trichlorosilyl)hexane as acrosslinker and n-butyl acetate as the orthogonal solvent16

(Fig. 2a; see Methods). The main advantage of this system is that

the crosslinking takes place spontaneously at room temperaturein the presence of oxygen and moisture in air. Comparing anumber of different base polymers including poly(styrene) orpoly(hydroxylstyrene), PMMA exhibited the best results, with ahigh breakdown strength (.3 MV cm21) and a low leakagecurrent (10–100 nA mm22 at 2 MV cm21) for gate dielectricthickness d down to 30–50 nm. This performance is comparable

Photosensitivedielectric

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Figure 3 Self-aligned gate (SAG) architecture. a, Schematic of the process to form a SAG structure. Top panel: deposition of a photosensitive second dielectric on top

of the semiconducting (SC) and gate dielectric (GD) layer and UV irradiation through the back of substrate. Middle panel: development of the second dielectric to remove the

exposed regions. Bottom panel: inkjet printing of gate electrode. b, Cross-sectional view of the SAG structure measured by FIB-SEM. c, Capacitance–voltage characteristics

of an F8T2/C-PMMA FET with self-aligned printed source–drain electrodes and unconfined poly(3,4-ethylenedioxythiophene) doped with polystyrene sulfonic acid

(PEDOT:PSS) top-gate electrodes (black line). The first of the source–drain electrodes was defined by evaporation and photolithography (evaporated electrode), and the

second electrode was defined by SAP (printed electrode). Overlap capacitances were measured between the gate and printed (blue line) or evaporated (red line) electrodes in

the SAG architecture and in a normal SAP device in which the PEDOT:PSS was printed directly on the PMMA gate dielectric layer (black).

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to that of thermal SiO2 on Si (ref. 19; Fig. 2b). Further reductioncan be expected from patterning the semiconductor to minimizecrosstalk between transistors and from reducing the surfaceroughness of the semiconducting layer underneath. Weemphasize that the leakage current is already low enough topermit operating the device at high frequency (see Fig. 4c). Usingthe semiconducting polymer poly(dioctylfluorene-co-bithiophene) (F8T2) and a C-PMMA gate dielectric allowedfabrication of fully downscaled printed TFTs operating at voltagesbelow 5–8 V.

We have investigated the scaling behaviour of TFTs as afunction of the ratio of d/L to determine experimentally themaximum gate dielectric thickness that can be tolerated for agiven channel length while still retaining long-channel behaviour(Fig. 2c). For a given dielectric thickness d ¼ 100 nm, we variedthe channel length from 400 nm to 100 nm. F8T2 transistorswith d/L ¼ 1 exhibit severely degraded characteristics withpronounced short-channel effects manifesting themselves as asuperlinear increase of drain current ID with source–drainvoltage VD. In contrast, devices with d/L ¼ 0.25 exhibit long-channel behaviour with a clear linear as well as saturation region.Our results show that a ratio of d/L � 0.25 is required to meetbasic scaling requirements in an OTFT structure. This isconsistent with recent findings on pentacene transistors withcontacts fabricated by electron-beam lithography20. Interestingly,we observe unusually large drain current even after normalizationby the channel length (ID � L) in the shortest channel deviceswith L ¼ 100 nm. The origin of this current enhancement is notclear at present; it might partly be attributable to channel lengthshortening effects21, but might also reflect the channel lengthbecoming comparable to the length scale over which chargecarriers diffuse into the organic semiconductor near the injectingcontacts, or the length scale of ordered polymer domains.

To observe the above clean scaling behaviour it was necessary tomodify the surface of the source–drain contacts with a thiol self-assembled monolayer (SAM) to optimize charge injection andminimize contact resistance22–24. In sub-micrometre devices,contact resistance is a critical parameter. If the contact resistancebecomes comparable to or exceeds the channel resistance, theapparent mobility decreases for short channel length, and thebenefit of reducing the channel length is at least partially lost25.This is a particularly difficult challenge because environmentallystable polymers such as F8T2 tend to exhibit a significantmismatch between their highest occupied molecular orbital(HOMO) level (5.5 eV) and the Fermi level of the gold electrode(5.1 eV). We used SAMs to modify the work function of the goldsource–drain electrodes through alignment of surface dipoles22.Different thiols were investigated with work functions rangingfrom 5.7 eV to 4.2 eV (see Supplementary Information,Fig. S2a,b). A systematic correlation was observed between theapparent mobility and threshold voltage and the work function(Fig. 2d). The best performance was achieved with a4-(trifluoromethyl)thiophenol SAM (F-SAM), which resulted inan increase in the gold work function by �0.6 eV. We alsobelieve that the selected top-gate configuration is beneficial forminimizing contact resistance effects because it allows adistributed injection due to current crowding26. As a result,a mobility of 0.005 cm2 V21 s21 was observed in sub-micrometre devices (L ¼ 200 nm) that meet scaling requirements(d ¼ 30–50 nm). This mobility value is typical of F8T2 and isvery similar to that extracted from longer channel devices(L ¼ 20 mm; see Fig. 2c). This suggests that in our configurationthe contact resistance is sufficiently low such that a severereduction of apparent mobility in sub-micrometre devices asobserved in other systems13,20,25 can be avoided.

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Figure 4 Fully downscaled SAG pBTTT transistor and switching speed.

Output (a) and transfer (b) characteristics of a SAP pBTTT/C-PMMA (d � 30 nm)

FET with SAG structure. c, Root-mean-square value of drain (filled circles) and

gate (open circles) currents versus frequency of a micro channel length F8T2

transistor (black: L ¼ 5 mm, W ¼ 1 mm), a SAP pBTTT transistor without SAG

(red: L � 200 nm, W ¼ 500 mm), and a SAP pBTTT transistor with SAG (blue:

L � 200 nm, W ¼ 500 mm). Transistors are all biased in the trans-diode regime

(VG ¼ VD) and the a.c. signal Vgs has an amplitude in the 120–250 mV range.

From the interception (dashed lines) between drain and gate current curves the

frequency of transition (fT) can be extracted; in the case of the pBTTT transistor

with SAG, this frequency needs to be extrapolated due to the 100 kHz

measurement limit of the setup.

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To remain compatible with large-area manufacturing it isimportant that not only the channel length, but the entire devicestructure, is defined in a self-aligned manner. We have developed aself-aligned gate architecture to minimize the parasitic overlapcapacitances, Cgs and Cgd, that would otherwise be associated withthe 50–100 mm wide printed gate line overlapping with the sourceand drain electrodes, respectively. With state-of-the-art volumeprinting on large-area flexible substrates, it is presently not possibleto significantly reduce linewidths because of the difficulties ofdispensing small liquid volumes, nor is it possible precisely to aligngate and source–drain patterns with respect to each other. Thisleads to undesirably large and variable Cgs and Cgd, and is one ofthe key reasons for the relatively poor performance of fully printedTFTs reported in the literature7–9. The fabrication process of ourself-aligned gate structure comprises the steps of (1) depositing athick (1 mm), second UV photosensitive dielectric layer (Shipley1813 positive UV photoresist) on top of the thin (30–50 nm) gatedielectric layer; (2) irradiating the structure with light throughthe back of the substrate to selectively expose the channel regionwith the optically opaque source and drain electrodes acting as ashadow mask; (3) developing the photoresist into a trenchstructure self-aligned with respect to the edges of the source anddrain electrodes; and (4) depositing a wide gate electrode by inkjetprinting. In this structure the overlap capacitance is minimized inspite of the wide printed linewidth. The gate dielectric is thin onlyover the channel where this is required, and the overlap capacitancebecomes insensitive to variations of the position of the gateelectrode (Fig. 3a).

Figure 3b shows cross-sectional scanning electron microscopy(SEM) images of a test structure in which the first source–drainelectrode was defined by photolithography, and the second SAPelectrode was inkjet printed. Interestingly, we found that theoverlap of the trench with the printed gold electrode (�1 mm)was larger than the overlap with the photolithographically definedelectrode (�200–300 nm). The printed electrode has a smooththickness profile dropping continuously to zero near its edge, andas a result some light passes through it in the vicinity of the edge,leading to a small widening of the trench structure on the side ofthe printed electrode. This is desirable, because it provides amethod for controlling the source/drain-to-gate overlap lengthwith the edge profile of the printed electrode. As discussed above,it is in fact not desirable to have strictly zero overlap length in asub-micrometre, self-aligned gate OTFT, as this would put verystringent limitations on the injection of charges from the source–drain contacts into the channel12,26. In the presence of a small,but finite overlap length, contact resistance effects can beminimized by current crowding27 while maintaining a smalloverlap capacitance. The overlap capacitance between a printedPEDOT:PSS gate and a lithographically defined gold source–drain electrode was measured to be 0.1–0.3 pF mm21. Consistentwith focused ion beam SEM (FIB-SEM) measurements, theoverlap capacitance between the PEDOT:PSS gate and the printedgold source–drain electrode is slightly higher (0.6–0.8 pF mm21).These values are at least a factor of 5–10 lower than those ofreference devices without the self-aligned gate structure (Fig. 3c).The overlap capacitance in the self-aligned gate structure isdetermined by two contributions, one from the narrow trenchregion where the gate dielectric is thin, and one from thesurrounding regions where the gate electrode is spaced away fromthe source–drain electrodes by the second dielectric layer. Weestimate that the contribution of the latter region to the totalcapacitance is about 90%, and a further reduction of overlapcapacitance is therefore possible by increasing the thickness ofthe photosensitive dielectric layer using established thick-filmphotoresist technology28.

The self-aligned device architecture is compatible withhigh-mobility, state-of-the-art polymer semiconductors, such asF8T2 or poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene(pBTTT)4. No degradation in device performance during the UVphoto-exposure (see Supplementary Information, Fig. S4) and thesubsequent trench development step in alkaline developer wasobserved with pBTTT or F8T2 and 30-nm C-PMMA gatedielectric (Fig. 4a,b; also see Supplementary Information,Fig. S5a,b). Using pBTTT we have realized high-performanceself-aligned devices operating below 5–8 V with mobilities of�0.1–0.2 cm2 V21 s21. In spite of the short channel length(L ¼ 200 nm), clean current saturation is observed in the outputcharacteristics. To the best of our knowledge this is the bestperformance reported to date for inkjet-printed polymertransistors. The clean current saturation has allowed us to fabricatelogic inverters in a simple resistor load configuration. Thesedevices operate below 25 V and exhibit a voltage gain of 2 (seeSupplementary Information, Fig. S5c). To estimate the switchingspeed that could be achieved with such devices we have measuredthe transition frequency fT of the discrete transistors in a numberof different configurations (Fig. 4c). fT is determined as thecrossover point at which the AC modulated channel current inresponse to a gate voltage modulation becomes equal to theparasitic current flowing through the capacitance between the gateand source–drain. The combination of shortening the channel bySAP and the higher mobility of pBTTT (pBTTT SAP) results in asignificant improvement compared with a standard micrometre-scale F8T2 device (F8T2, L ¼ 5 mm), but the transition frequencyremains limited to the relatively small value of 40 kHz. However,the self-aligned gate architecture allows reducing the parasiticcurrent through the gate significantly while retaining a hightransconductance/channel current modulation, and achieving fTvalues around 1.6 MHz (pBTTT SAG). The high frequencyoperation is also a manifestation of the relatively low leakagecurrent through the thin-polymer gate dielectric.

We have developed a printing process for sub-micrometrepolymer TFTs that allows basic scaling requirements to be metfor downscaling and at the same time remains compatible withthe manufacturing requirements for large-area, flexibleelectronics. The process is self-aligned, and it allows the use ofcoarse-definition printing techniques such as inkjet printing orother graphic arts printing techniques to define fully downscaledsub-micrometre TFTs operating at 5 V with low parasitic overlapcapacitance of less than 0.6 pF mm21. The use of a self-alignedgate architecture is crucial for achieving fast switching speeds inprinted transistors. Our downscaling approach provides a pathfor achieving the performance level that is necessary to meetapplication requirements for printed circuits in RFID or otherambient intelligent devices. The technique also allows fabricationof properly downscaled polymer FETs with channel lengths onthe order of 100 nm for probing the electrical transportproperties on the length scale of self-organized, crystalline,polymer domains.

METHODS

SELF-ALIGNED PRINTING PROCESS

Corning 7059 glass slides were used as substrates after they were cleanedsequentially in an ultrasonic bath with deionized water, acetone and isopropanol.After formation of the first electrode by inkjet printing of a gold colloidal ink orconventional photolithography, the gold surface was modified by PFDT(Fluorochem) to achieve SAP. The gold nanoparticle ink was obtained fromHarima and was diluted with xylene and filtered with a 0.2-mm syringe filterbefore printing. A home-built inkjet printing setup with a standard single-nozzle, drop-on-demand piezoelectric print head (Microdrop GmbH) was used.

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The gold electrodes were then sintered on a hot plate (250 8C, 1 h). Thecompleted patterns were investigated by optical microscopy (Olympus BX-51),atomic force microscopy (Dimension 3100, Digital Instrument) and SEM (FEIPhilips XL30 sFEG) to determine the channel length. The source–drainelectrodes of some F8T2 devices were subsequently modified by another SAM toimprove the charge injection. 4-(Trifluoromethyl)thiophenol (F-SAM, AcroOrganics), benzenethiol (H-SAM, Acro Organics), 4-methoxybenzenethiol(OCH3-SAM, Acro Organics) and 4-mercaptobenzonitrile (CN-SAM, ApinChemicals) were investigated.

FORMATION OF SEMICONDUCTOR, INSULATOR AND GATE ELECTRODE

The semiconducting polymer F8T2 (Dow Chemical Company) or pBTTT (MerckChemicals) were dissolved in anhydrous xylene (0.7 wt%) or dichlorobenzene(0.5 wt%), respectively. For the case of F8T2, the film was annealed at 80 8C for20 min to remove the solvent after spinning (2,000 r.p.m., 1 min) in a glove boxwith low oxygen and moisture level (,5 p.p.m.). pBTTT films were annealed at100 8C for 30 min to remove the solvent and at 170 8C for 10 min to improvemolecular order in the same glove box after spinning (2,000 r.p.m., 90 s). Beforespinning of pBTTT, the glass substrate and source–drain gold electrode weremodified by octadecyltrichlorosilane and PFDT, respectively.

For thin-polymer gate dielectrics, PMMA (Aldrich, Mw ¼ 120,000) wasused as received. The crosslinking agent, 1,6-bis(trichlorosilyl)hexane (AcroOrganics), was purified by distillation under an inert atmosphere. For films of30–50 nm thickness, PMMA (15–20 mg ml21 in anhydrous n-butyl acetate)was blended with 1,6-bis(trichlorosilyl)hexane (�5–7 ml) in the glove box andthen the mixture was spin-coated at 4,000–6,000 r.p.m. onto the semiconductorsurface in a fume hood in a clean room. The film was annealed on a hot plate at100 8C for 10 min to remove the solvent. Top-gated transistors were completedby formation of the gate electrode through inkjet printing of PEDOT:PSS orevaporation of thin aluminium films with a shadow mask (see SupplementaryInformation, Fig. S1b). The channel width of all SAP transistors was 500 mm.The relative work function of bare or SAM-modified metal source–drainelectrodes was measured using non-contact scanning Kelvin probe microscopy29.

FORMATION OF SELF-ALIGNED GATE STRUCTURE

For the self-aligned gate structure, a second photosensitive dielectric(Shipley 1813, MicroChem) was spin-coated at 4,000–6,000 r.p.m. (thicknesst ¼ 1–1.5 mm) over the first gate dielectric layer and then annealed at 120 8C.The substrate was exposed to UV light (i-line) through the back of the substrateto define a trench pattern of the second dielectric materials with edges aligned tothe edges of the source–drain electrodes. The UV light exposure time was kept asshort as possible to minimize potential damage to the semiconducting polymer.The exposed photosensitive material was then developed in MF319 developingsolution (MicroChem) to remove the material in the exposed regions of thesubstrate. The samples were washed with a flow of deionized water and driedwith a flow of nitrogen gas. The FETs were completed by formation of a gateelectrode on top of the trenches. Cross-sectional views of samples were observedthrough a FIB-SEM (FEI Quanta 3D Dual Beam ESEM).

ELECTRICAL CHARACTERISTIC OF POLYMER TRANSISTORS

The electrical characteristics were measured with an HP 4155B semiconductorparameter analyser and an HP 4192A impedance analyser in nitrogenatmosphere. The transistor parameters such as charge carrier mobility werecalculated in the saturation or linear regime using the standard formalism forFETs11. The transition frequency fT was measured in the following way. The d.c.bias voltages to source, drain and gate were independently applied by means ofan Agilent 4156C Semiconductor Parameter Analyser, and the transistors werekept in the trans-diode regime for fT measurements. A gate–source a.c. voltagesignal (Vgs) was applied through an a.c. coupler using an HP33120A functiongenerator with an amplitude of 50–250 mV. The a.c. components of both thedrain and the gate currents were simultaneously measured using two SR830lock-in amplifiers30.

Received 22 March 2007; accepted 8 October 2007;

published 18 November 2007.

References1. Sanderson, K. Display of flexibility. Nature 445, 473 (2007).2. Ong, B. S., Wu, Y. L., Liu, P. & Gardner, S. High-performance semiconducting polythiophenes for

organic thin-film transistors. J. Am. Chem. Soc. 126, 3378–3379 (2004).3. Heeney, M. et al. Stable polythiophene semiconductors incorporating thieno[2,3-b]thiophene.

J. Am. Chem. Soc. 127, 1078–1079 (2005).4. McCulloch, I. et al. Liquid-crystalline semiconducting polymers with high charge-carrier mobility.

Nature Mater. 5, 328–333 (2006).5. Fix, W., Ullmann, A., Ficker, J. & Clemens, W. Fast polymer integrated circuits. Appl. Phys. Lett. 81,

1735–1737 (2002).6. Steudel, S. et al. Comparison of organic diode structures regarding high-frequency rectification

behavior in radio-frequency identification tags. J. Appl. Phys. 99, 114519 (2006).7. Sirringhaus, H. et al. High-resolution inkjet printing of all-polymer transistor circuits. Science 290,

2123–2126 (2000).8. Zielke, D. et al. Polymer-based organic field-effect transistor using offset printed source/drain

structures. Appl. Phys. Lett. 87, 123508 (2005).9. Knobloch, A., Manuelli, A., Bernds, A. & Clemens, W. Fully printed integrated circuits from solution

processable polymers. J. Appl. Phys. 96, 2286–2291 (2004).10. Weste, N. H. E. & Harris, D. CMOS VLSI Design, Ch. 1 (Pearson Education, Boston, 2005).11. Sze, S. M. Physics of Semiconductor Devices, Ch. 8 (John Wiley & Sons, New York, 1981).12. Sele, C. W., von Werne, T., Friend, R. H. & Sirringhaus, H. Lithography-free, self-aligned inkjet

printing with sub-hundred-nanometer resolution. Adv. Mater. 17, 997–1001 (2005).13. Austin, M. D. & Chou, S. Y. Fabrication of 70 nm channel length polymer organic thin-film

transistors using nanoimprint lithography. Appl. Phys. Lett. 81, 4431–4433 (2002).14. Zhao, N. et al. Self-aligned inkjet printing of highly conducting gold electrodes with submicron

resolution. J. Appl. Phys. 101, 064513 (2007).15. Chua, L. L. et al. General observation of n-type field-effect behaviour in organic semiconductors.

Nature 434, 194–199 (2005).16. Yoon, M. H., Yan, H., Facchetti, A. & Marks, T. J. Low-voltage organic field-effect transistors and

inverters enabled by ultrathin cross-linked polymers as gate dielectrics. J. Am. Chem. Soc. 127,10388–10395 (2005).

17. Jang, Y. et al. Low-voltage and high-field-effect mobility organic transistors with a polymer insulator.Appl. Phys. Lett. 88, 072101 (2006).

18. Yang, S. Y., Kim, S. H., Shin, K., Jeon, H. & Park, C. E. Low-voltage pentacene field-effect transistorswith ultrathin polymer gate dielectrics. Appl. Phys. Lett. 88, 173507 (2006).

19. Frank, D. J. et al. Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE89, 259–288 (2001).

20. Tulevski, G. S., Nuckolls, C., Afzali, A., Graham, T. O. & Kagan, C. R. Device scaling in sub-100 nmpentacene field-effect transistors. Appl. Phys. Lett. 89, 183101 (2006).

21. Shur, M., Hack, M. & Shaw, J. G. A new analytic model for amorphous-silicon thin-film transistors.J. Appl. Phys. 66, 3371–3380 (1989).

22. Campbell, I. H. et al. Controlling Schottky energy barriers in organic electronic devices using self-assembled monolayers. Phys. Rev. B 54, 14321–14324 (1996).

23. de Boer, B., Hadipour, A., Mandoc, M. M., van Woudenbergh, T. & Blom, P. W. M. Tuning of metalwork functions with self-assembled monolayers. Adv. Mater. 17, 621–625 (2005).

24. Ashkenasy, G., Cahen, D., Cohen, R., Shanzer, A. & Vilan, A. Molecular engineering ofsemiconductor surfaces and devices. Acc. Chem. Res. 35, 121–128 (2002).

25. Tulevski, G. S. et al. Chemical complementarity in the contacts for nanoscale organic field-effecttransistors. J. Am. Chem. Soc. 128, 1788–1789 (2006).

26. Maitra, K. & Bhat, N. Impact of gate-to-source/drain overlap length on 80-nm CMOS circuitperformance. IEEE Trans. Electron. Devices 51, 409–414 (2004).

27. Chiang, C. S. et al. Top-gate staggered amorphous silicon thin-film transistors: Series resistance andnitride thickness effects. Jpn J. Appl. Phys. 37, 5914–5920 (1998).

28. Shaw, J. M., Gelorme, J. D., LaBianca, N. C., Conley, W. E. & Holmes, S. J. Negative photoresists foroptical lithography. IBM J. Res. Dev. 41, 81–94 (1997).

29. Burgi, L., Richards, T. J., Friend, R. H. & Sirringhaus, H. Close look at charge carrier injection inpolymer field-effect transistors. J. Appl. Phys. 94, 6129–6137 (2003).

30. Wagner, V., Wobkenberg, P., Hoppe, A. & Seekamp, J. Megahertz operation of organic field-effecttransistors based on poly(3-hexylthiopene). Appl. Phys. Lett. 89, 243515 (2006).

AcknowledgementsThe research was supported by the Engineering and Physical Sciences Research Council (EPSRC) and theEU Integrated Project NAIMO (No NMP4-CT-2004-500355). The authors thank the Dow ChemicalCompany and Merck for providing F8T2 and pBTTT, D.J. Stokes (FEI Company) for FIB-SEMmeasurement, A. Facchetti (Northwestern University) for helpful discussions, R. Peterson (CavendishLaboratory) for inverter measurements, X. Cheng (Cavendish Laboratory) for helpful support, andM. Tello (Cavendish Laboratory) for performing the Kelvin probe work function measurements.Correspondence and requests for materials should be addressed to H.S.Supplementary information accompanies this paper on www.nature.com/naturenanotechnology.

Author contributionsY.Y.N. and H.S. conceived and designed the experiments. Y.Y.N. performed the experiments. N.Z.contributed to self-aligned inkjet printing. M.C. measured the transition frequency of transistors. Y.Y.N.and H.S. analysed the data and co-wrote the paper.

Competing financial interestsThe authors declare competing financial interests: details accompany the full-text HTML version of thepaper at www.nature.com/naturenanotechnology.

Reprints and permission information is available online at http://npg.nature.com/reprintsandpermissions/

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