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n 2 GVHD: Nguy n Thanh Th o

Ch ng I: KHI QUT TI

I/ Tm t t ti:

1/ Gi i thi u s l c cc modul c a m ch:

-Tn ti n 2:L p trnh PIC16F877A i u khi n t c ng c DC

-Yu c u t ra: L p trnh C cho Pic 16F877A i u khi n t c cho ng c DC c

g n encoder h i ti p t c .T c c ci t t bn phm v t c t c th i h i

ti p t encoder c hi n th trn mn hnh LCD 16x2.

-Tm t t h ng th c hi n ti:

S d ng Pic 16F877A l vi i u khi n trung tm. Dng ch ng trnh CCS l p

trnh C v bin d ch ch ng trnh. Xy d ng kh i bn phm g m 16 phm nh p t c v i u khi n ng c

DC:

10 phm t 0 n 9 ci t t c (vng /phc).

1 phm SET (hay ENTER) l u t c ci t.

1 phm CLEAR xa t c ci t.

1 phm SAVE l u t c vo epprom.

3 phm i u i u khi n: quay thu n (FORWARD), quay nghich

(REVERSE), d ng (STOP).

Hi n th t c dng mn hnh LCD 16x2, l p trnh ch 4 bit (s d ng 4

chn nh n d li u t Pic).

S d ng m ch c u H l IC L298N o chi u ng c .

S d ng 2 knh PWM c a vi i u khi n Pic thay i gi tr p trung bnh t

vo ng c i u khi n t c . i t ng i u khi n l ng c DC 12V c g n Encoder.

Ngoi ra trn m ch cn c 1 phm ngu n (POWER) c p i n t adapter cho

m ch v 1 phm RESET cho pic 16F877A.

c p ngu n cho m ch ta dng adapter AC/DC (220V/12V) v kh i ngu n s

d ng IC 7805 n p i n p 5V cung c p cho Pic.

SVTH: Tr n T ng Bng V Vn Chnh 1

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2/ S nguyn l m ch:

3/Cch v n hnh m ch:

B c 1:

B t ngu n (nh n nt POWER), ch cho Pic v mn hnh LCD kh i ng, mn hnh

hi n th : CH N CH :

Ch ng trnh c 2 ch lm vi c: ch 1 l bm t c t, c l u t c vo

epprom; ch 2 l bm t c c nh th i gian thay i chi u quay.

B c 2:

Nh p t c t bn phm cc phm t 0 n 9.N u nh p sai ta nh n phm CLEAR

con tr trn LCD s xa h t cc s nh p, ta ph i nh p l i t u.Sau khi nh p

xong, nh n phm ENTER l u t c t, t c t c tnh theo n v

vng/pht.


b2

a7

b0b1

a4a5

a6

p0

p1

p2

p3

p0

p3

p1p2

a7

a4

a5

a6

b0

b2

b1

CCP2CCP1

RA0/AN02

RA1/AN13

RA2/AN2/VREF-/CVREF4

RA4/T0CKI/C1OUT6

RA5/AN4/SS/C2OUT7

RE0/AN5/RD8

RE1/AN6/WR9

RE2/AN7/CS10

OSC1/CLKIN13

OSC2/CLKOUT14

RC1/T1OSI/CCP216

RC2/CCP117

RC3/SCK/SCL18

RD0/PSP019

RD1/PSP120

RB7/PGD40

RB6/PGC39

RB538

RB437

RB3/PGM36

RB235

RB134

RB0/INT33

RD7/PSP730

RD6/PSP629

RD5/PSP528

RD4/PSP427

RD3/PSP322

RD2/PSP221

RC7/RX/DT26

RC6/TX/CK25

RC5/SDO24

RC4/SDI/SDA23

RA3/AN3/VREF+5

RC0/T1OSO/T1CKI15

MCLR/Vpp/THV1

U1

PIC16F877A

C1

30pF

C2

30pF

X1CRYSTAL

R910k

R15k

R25k

R35k

R45k

VCC

VCC

C310uF

R5

2k2

CCP1

CCP2

CLK

1 2 3

4 5 6

7 8 9

0 (10)

FW(16) RV(15) STOP (14)

CLEAR (11)

set (12)

13

D7

14

D6

13

D5

12

D4

11

D3

10

D2

9

D1

8

D0

7

E

6

RW

5

RS

4

VSS

1

VDD

2

VEE

3

LCD116_X_2_LCD

RV1

1K

VI1

VO3

GND

2

U27805

321

J1

JACK C4100uF

C5100nF

C6100uF

C7100nF

D8LED

R26

1k

+12V +5V

12

J2

TERMINAL2

IN15

IN27

ENA6

OUT12

OUT23

ENB11

OUT313

OUT414

IN310

IN412

SENSA1

SENSB15

GND

8

VS

4

VCC

9 U1

L298

+12V

R10.5

R20.5

M1

M2CLK

123

45

J3

SIL-100-05+88.8

D11N4007

D21N4007

D31N4007

D41N4007

+12V

M1 M2

CLK

RESET

Hnh 1: S nguyn l m ch

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N u l ch 2 th ta ph i nh p them th i gian, sau nh n phm ENTER

B c 3:

i u khi n ng c ta nh n phm: quay thu n (FORWARD), quay ngh ch

(REVERSE), d ng (STOP).

B c 4:

nh p l i t c ta nh n phm CLEAR r i ti n hnh t t c nh b c 2.

-T c t c th i c a ng c s c c p nh t m i 0,5s v s c so snh v i t c

t a ra tnh hi u i u khi n, ng th i c m i 0,5s t c s hi n th trn

mn hnh LCD.

4/ Khuy t i m c a m ch:

-Do khng p d ng cc ph ng php i u khi n (v d nh : PID, i u khi n m ,) nn t c ng c ch a c n nh.

-M ch c u H s d ng IC L298 ch i u khi n c ng c DC c cng su t nh .

- i v i kh i hi n th , do tnh ch t c a mn hnh LCD nn b h n ch quan st gi tr

hi n th kho ng cch xa.

5/ H ng pht tri n ti:

- C i thi n n nh t c ng c b ng ph ng php PID hay i u khi n m .

- Tnh ton thi t k m ch cng su t c th i u khi n c ng c c cng

su t l n h n.

- S d ng led 7 o n tng kh nng quan st c a kh i hi n th .

- K t n i v i my tnh, s dung visual basic l p trnh i u khi n t c ng c

DC.


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CH NG II:

GI I THI U V CC LINH KI N PH N T S D NG TRONG M CH

I.Vi i u khi n PIC16F877A

1. Khi qut v vi i u khi n PIC16F877A

a/ Khi qut:

- PIC l tn vi t t t c a Programmable Intelligent computer do hng General

Instrument t tn cho con vi i u khi n u tin c a h .Hng Micrchip ti p t c pht tri n s n ph m ny v cho n hng t o ra g n 100 lo i s n ph m khc

nhau.

- PIC16F887A l dng PIC kh ph bi n, kh y tnh nng ph c v cho h u

h t t t c cc ng d ng th c t . y l dng PIC kh d cho ng i m i lm quen

v i PIC c th h c t p v t o n n t n v h vi i u khi n PIC c a mnh.

- PIC 16F877A thu c h vi i u khi n 16Fxxx c cc t tnh sau:

Ngn ng l p trnh n gi n v i 35 l nh c di 14 bit.

T t c cc cu l nh th c hi n trong 1 chu k l nh ngo i tr 1 s cu l nh r

nhnh th c hi n trong 2 chu k l nh. Chu k l nh b ng 4 l n chu k dao ng

c a th ch anh.

B nh ch ng trnh Flash 8Kx14 words, v i kh nng ghi xo kho ng 100

ngn l n.

B nh Ram 368x8bytes. B nh EFPROM 256x8 bytes.

Kh nng ng t (ln t i 14 ngu n c ng t trong v ng t ngoi).

Ngn nh Stack c chia lm 8 m c.

Truy c p b nh b ng a ch tr c ti p ho c gin ti p.

D i i n th ho t ng r ng: 2.0V n 5.5V.

Ngu n s d ng 25mA.


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Cng su t tiu th th p:

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Hnh 2: S nguyn l PIC 16F877A

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b/S chn v s nguyn l c a PIC16F877A

S chn

S nguyn l


Hnh 3: S chn c a PIC 16F877A

Hnh 4: S nguyn l cc Port c a PIC 16F877A

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c/Nh n xt:T s chn v s nguyn l trn, ta rt ra cc nh n xt ban u nh sau :

- PIC16F877A c t t c 40 chn

- 40 chn trn c chia thnh 5 PORT, 2 chn c p ngu n, 2 chn GND, 2

chn th ch anh v m t chn dng RESET vi i u khi n.

- 5 port c a PIC16F877A bao g m :

+ PORT B: 8 chn

+ PORT D: 8 chn

+ PORT C: 8 chn

+ PORT A: 6 chn

+ PORT E: 3 chn

2. T ch c b nh :

C u trc b nh c a vi i u khi n

PIC16F877A bao g m b nh ch ng trnh (Program memory) v

b nh d li u (Data Memory).

2.1. B nh ch ng trnh:

B nh ch ng trnh c a vi i u

khi n PIC16F877A l b nh flash,

dung l ng b nh 8K word (1 word

= 14 bit) v c phn thnh nhi u

trang (t page0 n page 3) . Nh

v y b nh ch ng trnh c kh

nng ch a c 8*1024 = 8192 l nh

(v m t l nh sau khi m ha s c

dung l ng 1 word (14 bit). m ha c a ch c a 8K word b nh ch ng

trnh, b m ch ng trnh c dung l ng 13 bit (PC). SVTH: Tr n T ng Bng

V Vn Chnh 8Hnh 5: C u trc b nh ch ng trnh PIC

16F877A

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Khi vi i u khi n c reset, b m ch ng trnh s ch n a ch 0000h (Reset

vector).Khi c ng t x y ra, b m ch ng trnh s ch n a ch 0004h (Interrupt

vector). B nh ch ng trnh khng bao g m b nh stack v khng c a ch ha

b i b m ch ng trnh.

2.2. B nh d li u: - B nh d li u c a PIC16F877A c chia thnh 4 bank. M i bank c d ng

l ng 128 byte.

- N u nh 2 bank b nh d li u c a 8051 phn chia ring bi t : 128 byte u tin

thu c bank1 l vng Ram n i ch ch a d li u, 128 byte cn l i thu c bank 2 l

cng cc thanh ghi c ch c nng c bi t SFR m ng i dng khng c ch a

d li u khc, cn 4 bank b nh d li u c a PIC16F877A c t ch c theo cch

khc.

- M i bank c a b nh d li u PIC16F877A bao g m c cc thanh ghi c ch c

nng c bi t SFR n m cc cc nh a ch th p v cc thanh ghi m c ch

dng chung GPR n m vng a ch cn l i c a m i bank thanh ghi. Vng nh

cc thanh ghi m c ch dng chung ny chnh l n i ng i dng s l u d li u

trong qu trnh vi t ch ng trnh. T t c cc bi n d li u nn c khai bo ch a

trong vng a ch ny. - Trong c u trc b nh d li u c a PIC16F877A, cc thanh ghi SFR no m

th ng xuyn c s d ng (nh thanh ghi STATUS) s c t t t c cc

bank thu n ti n trong vi c truy xu t. S d nh v y l v, truy xu t m t

thanh ghi no trong b nh c a 16F877A ta c n ph i khai bo ng bank ch a

thanh ghi , vi c t cc thanh ghi s d ng th ng xuyn gip ta thu n tin h n

r t nhi u trong qu trnh truy xu t, lm gi m l nh ch ng trnh.

D a trn s 4 bank b nh d li u PIC16F877A ta rt ra cc nh n xt nh sau :

-Bank0 g m cc nh c a ch t 00h n 77h, trong cc thanh ghi dng chung

ch a d li u c a ng i dng a ch t 20h n 7Fh. Cc thanh ghi PORTA,

PORTB, PORTC, PORTD, PORTE u ch a bank0, do truy xu t d li u cc

thanh ghi ny ta ph i chuy n n bank0. Ngoi ra m t vi cc thanh ghi thng d ng

khc ( s gi i thi u sau) cng ch a bank0


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- Bank1 g m cc nh c a ch t 80h n FFh. Cc thanh ghi dng chung c a ch

t A0h n Efh. Cc thanh ghi TRISA, TRISB, TRISC, TRISD, TRISE cng c

ch a bank1

- T ng t ta c th suy ra cc nh n xt cho bank2 v bank3 d a trn s trn.

Cng quan st trn s , ta nh n th y thanh ghi STATUS, FSR c m t trn c 4

bank. M t i u quan tr ng c n nh c l i trong vi c truy xu t d li u c a

PIC16F877A l : ph i khai bo ng bank ch a thanh ghi .N u thanh ghi no m 4

bank u ch a th khng c n ph i chuy n bank.


Hnh 6: C u trc b nh d li u c a PIC 16F877A

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2.2a/ Thanh ghi ch c nng c bi t SFR: (Special Function Register)

- y l cc thanh ghi c s d ng b i CPU ho c c dng thi t l p v i u

khi n cc kh i ch c nng c tch h p bn trong vi i u khi n. C th phn

thanh ghi SFR lm hai l ai: thanh ghi SFR lin quan n cc ch c nng bn trong

(CPU) v thanh ghi SRF dng thi t l p v i u khi n cc kh i ch c nng bn

ngoi (v d nh ADC, PWM, ).

- M t s thanh ghi c c nng c bi t:

Thanh ghi STATUS (03h, 83h, 103h, 183h):thanh ghi ch a k t qu th c hi n

php ton c a kh i ALU, tr ng thi reset v cc bit ch n bank c n truy xu t

trong b nh d li u.

Thanh ghi OPTION_REG (81h, 181h): thanh ghi ny cho php c v ghi, cho

php i u khi n ch c nng pull-up c a cc chn trong PORTB, xc l p cc

tham s v xung tc ng, c nh tc ng c a ng t ngo i vi v b m

Timer0.

Thanh ghi INTCON (0Bh, 8Bh,10Bh, 18Bh): thanh ghi cho php c v

,ch a cc bt i u khi n v cc c hi u khi timer0 b trn, ng t ngo i vi

RB0/INT v ng t interrput-on-change t i cc chn c a PORTB.

Thanh ghi PIE1 (8Ch): ch a cc bit i u khi n chi ti t cc ng t c a cc kh i ch c nang ngoai vi.

Thanh ghi PIR1 (0Ch) ch a c ng t c a cc kh i ch c nng ngo i vi, cc

ng t ny c cho php b i cc bit i u khi n ch a trong thanh ghi PIE1.

Thanh ghi PIE2 (8Dh): ch a cc bit i u khi n cc ng t c a cc kh i ch c

nng CCP2, SSP bus, ng t c a b so snh v ng t ghi vo b nh EEPROM.

Thanh ghi PCON (8Eh): ch a cc c hi u cho bi t tr ng thi cc ch reset

c a vi i u khi n.

2.2b/ Thanh ghi muc ch chung GPR: (General Purpose Register)

Cc thanh ghi ny c th c truy xu t tr c ti p ho c gin ti p thng qua thanh

ghi FSG (File Select Register).y l cc thanh ghi d li u thng th ng, ng i s

d ng c th ty theo m c ch ch ng trnh m c th dng cc thanh ghi ny

ch a cc bi n s , h ng s , k t qu ho c cc tham s ph c v cho ch ng trnh.


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2.3. Stack

- Stack khng n m trong b nh ch ng trnh hay b nh d li u m l m t

vng nh c bi t khng cho php c hay ghi. Khi l nh CALL c th c hi n hay

khi m t ng t x y ra lm ch ng trnh b r nhnh, gi tr c a b m ch ng trnh

PC t ng c vi i u khi n c t vo trong stack. Khi m t trong cc l nh RETURN,

RETLW hat RETFIE c th c thi, gi tr PC s t ng c l y ra t trong stack,

vi i u khi n s th c hi n ti p ch ng trnh theo ng qui trnh nh tr c.

- B nh Stack trong vi i u khi n PIC h 16F87xA c kh nng ch a c 8

a ch v ho t ng theo c ch xoay vng. Nghia l gi tr c t vo b nh Stack l n

th 9 s ghi ln gi tr c t vo Stack l n u tin v gi tr c t vo b nh Stack

l n th 10 s ghi ln gi tri6 c t vo Stack l n th 2.

- C n ch l khng c c hi u no cho bi t tr ng thi stack, do ta khng bi t c khi no stack trn. Bn c nh t p l nh c a vi i u khi n dng PIC cng

khng c l nh POP hay PUSH, cc thao tc v i b nh stack s hon ton c i u

khi n b i CPU.

3. Khi qut v ch c nng c a cc port trong vi i u khi n PIC16F877A

a/PORTA:

-PORTA (RPA) bao g m 6 I/O pin.y l cc chn hai chi u (bidirectional

pin), ngha l c th xu t v nh p c.Ch c nng I/O ny c i u khi n b i

thanh ghi TRISA ( a ch 85h). Mu n xc l p ch c nng c a m t chn trong PORTA

l input, ta set bit i u khi n t ng ng v i chn trong thanh ghi TRISA v

ng c l i, mu n xc l p ch c nng c a m t chn trong PORTA l output, ta clear

bit i u khi n t ng ng v i chn trong thanh ghi TRISA. Thao tc ny hon ton

t ng t i v i cc PORT v cc thanh ghi i u khi n t ng ng TRIS ( i v i

PORTA l TRISA, i v i PORTB l TRISB, i v i PORTC l TRISC, i v i


Hnh 7: C u trc thanh ghi ch c nng chung c a PIC 16F877A

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PORTD l TRISD v i v i PORTE l TRISE).

-Ngoi ra, PORTA cn c cc ch c nng quan tr ng sau :

Ng vo Analog c a b ADC : th c hi n ch c nng chuy n t Analog

sang Digital

Ng vo i n th so snh

Ng vo xung Clock c a Timer0 trong ki n trc ph n c ng : th c hi n

cc nhi m v m xung thng qua Timer0

Ng vo c a b giao ti p MSSP (Master Synchronous Serial Port)

- Cc thanh ghi SFR lin quan n PORTA bao g m:

PORTA ( a ch 05h) : ch a gi tr cc pin trong PORTA.

TRISA ( a ch 85h) : i u khi n xu t nh p. CMCON ( a ch 9Ch) : thanh ghi i u khi n b so snh.

CVRCON ( a ch 9Dh) : thanh ghi i u khi n b so snh i n p.

ADCON1 ( a ch 9Fh) : thanh ghi i u khi n b ADC.

b/PORTB:

- PORTB (RPB) g m 8 pin I/O. Thanh ghi i u khi n xu t nh p t ng ng l

TRISB.

- Bn c nh m t s chn c a PORTB cn c s d ng trong qu trnh n p

ch ng trnh cho vi i u khi n v i cc ch n p khc nhau. PORTB cn lin

quan n ng t ngo i vi v b Timer0. PORTB cn c tch h p ch c nng i n

tr ko ln c i u khi n b i ch ng trnh.

- Cc thanh ghi SFR lin quan n PORTB bao g m:

PORTB ( a ch 06h, 106h) : ch a gi tr cc pin trong PORTB

TRISB ( a ch 86h, 186h) : i u khi n xu t nh p

OPTION_REG ( a ch 81h, 181h): i u khi n ng t ngo i vi v b Timer0.

c/PORTC:

PORTC c 8 chn v cng th c hi n c 2 ch c nng input v output d i s i u

khi n c a thanh ghi TRISC t ng t nh hai thanh ghi trn.

Ngoi ra PORTC cn c cc ch c nng quan tr ng sau :

- Ng vo xung clock cho Timer1 trong ki n trc ph n c ng


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- B PWM th c hi n ch c nng i u xung l p trnh c t n s , duty cycle:

s d ng trong i u khi n t c v v tr c a ng c v.v.

- Tch h p cc b giao ti p n i ti p I2C, SPI, SSP, USART

d/PORTD:

-PORTD c 8 chn. Thanh ghi TRISD i u khi n 2 ch c nng input v output c a

PORTD t ng t nh trn.PORTD cng l c ng xu t d li u c a chu n giao ti p

song song PSP (Parallel Slave Port).

-Cc thanh ghi lin quan n PORTD bao g m:

Thanh ghi PORTD: ch a gi tr cc pin trong PORTD.

Thanh ghi TRISD: i u khi n xu t nh p.

Thanh ghi TRISE: i u khi n xu t nh p PORTE v chu n giao ti p PSP.

e/PORTE:

-PORTE c 3 chn.Thanh ghi i u khi n xu t nh p t ng ng l TRISE.Cc chn

c a PORTE c ng vo analog Bn c nh PORTE cn l cc chn i u khi n c a

chu n giao ti p PSP.

-Cc thanh ghi lin quan n PORTE bao g m:

PORTE: ch a gi tr cc chn trong PORTE.

TRISE: i u khi n xu t nh p v xc l p cc thng s cho chu n giao ti p PSP. ADCON1: thanh ghi i u khi n kh i ADC.

4. Cc v n v Timer

PIC16F877A c t t c 3 timer : timer0 (8 bit), timer1 (16 bit) v timer2 (8 bit).

4.1. Timer0

a/ L b nh th i ho c b m c nh ng u i m sau:

8 bit cho b nh th i ho c b m.

C kh nng c v vi t.

C th dng ng bn trong ho c bn ngoi.

C th ch n c nh xung c a xung ng h .

C th ch n h s chia u vo (l p trnh b ng ph n m n).

Ng t trn.

b/ Ho t ng c a Timer 0:


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Timer 0 c th ho t ng nh m t b nh th i ho c m t b m.Vi c ch n

b nh th i ho c b m c th c xc l p b ng vi c xo ho c t bt

TOCS c a thanh ghi OPTION_REG.

N u dng h s chia xung u vo th xo bit PSA c a thanh ghi

OPTION_REG.

Trong ch b nh th i c l a ch n b i vi c xo bit T0CS (OPTION

REG), n s c tng gi tr sau m t chu k l nh n u khng ch n h s

chia xung u vo.V gi tr c a n c vi t t i thanh ghi TMR0.

Khi dng xung clock bn ngoi cho b nh th i Timer0 v khng dng h s

chia clock u vo Timer0 th ph i p ng cc i u ki n c n thi t c th

ho t ng l ph i b o m xung clock bn ngoi c th ng b v i xung

clock bn trong (TOSC).

H s chia dng cho Timer 0 ho c b WDT. Cc h s nay khng c kh nng

c v kh nng vi t. ch n h s chia xung cho b ti n nh c a Timer0

ho c cho b WDT ta ti n hnh xo ho c t bt PSA c a thanh ghi

OPTION_REG

Nh ng bt PS2, PS1, PS0 c a thanh ghi OPTION_REG dng xc l p

cc h s chia. B ti n nh c gi tr 1:2 ch ng h n, c ngha l : bnh th ng khng s d ng

b ti n nh c a Timer0 ( ng ngha v i ti n nh t l 1:1) th c khi c tc

ng c a 1 xung clock th timer0 s tng thm m t n v . N u s d ng b

ti n nh 1:4 th ph i m t 4 xung clock th timer0 m i tng thm m t n v .

V hnh chung, gi tr c a timer0 (8 bit) lc ny khng cn l 255 n a m l

255*4=1020.

c/ Ng t c a b Timer0 Ng t c a b Timer 0 c pht sinh ra khi thanh ghi TMR0 b trn t c

t FFh quay v 00h.Khi bt T0IF c a thanh ghi INTCON s c

t. Bt ny ph i c xa b ng ph n m m n u cho php ng t bit

T0IE c a thanh ghi INTCON c set.Timer0 b d ng ho t ch

SLEEP ng t Timer 0 khng nh th c b x l ch SLEEP.

d/ Cc thanh ghi lin quan n Timer0 bao g m: SVTH: Tr n T ng Bng

V Vn Chnh 15

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- Thanh ghi OPTION_REG : i u khi n ho t ng c a Timer0

bit 5 TOCS l a ch n ngu n clock 1=Clock ngoi t chn T0CKI

0=Clock trong Focs/4

bit 4 T0SE bit l a chon s n xung clock 1=Timer 0 tng khi chn T0CKI t cao xu ng th p(s n xu ng) 0=Timer 0 tng khi chn T0CKI t th p ln cao(s n xu ng)

bit 3 PSA bit gn b chia xung u vo 1=gn b chia Prescaler cho WDT0=gn b chia Prescaler cho Timer 0

bit 2:0 PS2:PS1 l a ch n h s chia h s xung theo b ng sau:

PS2:PS0 Timer0 WDT

000 1:2 1:1

001 1:4 1:2

010 1:8 1:4

011 1:16 1:8

100 1:32 1:16

101 1:64 1:32110 1:128 1:64

111 1:256 1:128

- Thanh ghi TMR0 i ch 01h v 101h : ch a gi tr c a b nh th i Timer0

- Thanh ghi INTCON : cho php ng t ho t ng

Thanh ghi ch a cc bit i u khi n v cc bt c hi u khi timer0 b trn, ng t ngo i

vi RB0/INT v ng t interrupt_on_change t i cc chn c a PORTB.


Hnh 8: C u trc thanh ghi OPTION_REG REGISTERi u khi n ho t ng c a Timer0

Hnh 9: C u trc thanh ghi INTCON cho php ng t Timer0 ho t ng

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Bit 7 GIE Global Interrupt Enable bit

GIE = 1 cho php t t c cc ng t.

GIE = 0 khng cho php t t c cc ng t.

Bit 6 PEIE Pheripheral Interrupt Enable bit

PEIE = 1 cho php t t c cc ng t ngo i vi.

PEIE = 0 khng cho php t t c cc ng t ngo i vi.

Bit 5 TMR0IE Timer0 Overflow Interrupt Enable bitTMR0IE = 1 cho php ng t Timer0.

TMR0IE = 0 khng cho php ng t Timer0.

Bit 4 RBIE RB0/INT External Interrupt Enable bit

RBIE = 1 cho php t t c cc ng t ngo i vi RB0/INT

RBIE = 0 khng cho php t t c cc ng t ngo i vi RB0/INT

Bit 3 RBIE RB Port change Interrupt Enable bit

RBIE = 1 cho php ng t RB Port changeRBIE = 0 khng cho php ng t RB Port change

Bit 2 TMR0IF Timer0 Interrupt Flag bit

TMR0IF = 1 thanh ghi TMR0 b trn (ph i xa c hi u b ng ch ng

trnh).

TMR0IF = 0 thanh ghi TMR0 ch a b trn.

Bit 1 INTF BR0/INT External Interrupt Flag bit

INTF = 1 ng t RB0/INT x y ra (ph i xa c hi u b ng ch ng trnh).

INTF = 0 nga t RB0/INT ch a xa y ra.

Bit 0 RBIF RB Port Change Interrupt Flag bit

RBIF = 1 t nh t c m t chn RB7:RB4 c s thay i tr ng thi. Bt

ny ph i c xa b ng ch ng trnh sau khi ki m tra l i cc gi tr

chn t i PORTB.

RBIF = 0 khng c s thay i tr ng thi cc chn RB7:RB4. SVTH: Tr n T ng Bng

V Vn Chnh 17

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4.2.TIMER1

a/Timer1 l b nh th i 16 bit, gi tr c a Timer1 s c l u trong hai thanh ghi 8

bit TMR1H:TMR1L. C ng t c a Timer1 l bit TMR1IF, bit i u khi n c a Timer1 l

TRM1IE.C p thanh ghi c a TMR1 s tng t 0000h ln n FFFFh r i sau trn v

0000h. N u ng t c cho php, n s x y ra khi khi gi tr c a TMR1 trn t FFFFh

r i v 0000h, lc ny TMR1IF s b t ln.

b/ Timer1 c 3 ch ho t ng :

Ch ho t ng nh th i ng b : Ch c l a ch n b i bit

TMR1CS. Trong ch ny xung c p cho Timer1 l Fosc/4, bit T1SYNC

khng c tc d ng.

Ch m ng b : trong ch ny, gi tr c a timer1 s tng khi c xung

c nh ln vo chn T1OSI/RC1. Xung clock ngo i s c ng b v i xung

clock n i, ho t ng ng b c th c hi n ngay sau b ti n nh t l xung

(prescaler).

Ch m b t ng b :ch ny x y ra khi bit T1SYNC c set. B

nh th i s ti p t c m trong su t qu trnh ng (Sleep) c a vi i u khi n

v c kh nng t o m t ng t khi b nh th i trn v lm cho vi i u khi n

thot kh i tr ng thi ng . c/ Cc thanh ghi lin quan n Timer1 bao g m:

INTCON ( a ch 0Bh, 8Bh, 10Bh, 18Bh): cho php ng t ho t ng (2 bit GIE

v PEIE).

PIR1 ( a ch 0Ch): ch a c ng t Timer1 (TMR1IF).

PIE1 ( a ch 8Ch): cho php ng t Timer1 (TMR1IE).

Ba thanh ghi v a nu trn s c trnh by ph n ch ng trnh ngt c a PIC

TMR1L ( a ch 0Eh): ch a gi tr 8 bt th p c a b m Timer1.

TMR1H ( a ch 0Eh): ch a gi tr 8 bt cao c a b m Timer1.

Hai thanh ghi TMR1L v TMR1H l 2 thanh ghi ch a d li u 16 bit (l n l t

ch a 4 bit th p v 4 bit cao) c a b m Timer1

T1CON ( a ch 10h): xc l p cc thng s chi Timer


Hnh 10: C u trc thanh ghi T1CON i u khi n ho t ng c a Timer1

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- bit 7,6 khng s d ng

- bit 5,4 T1CKPS1: T1CKPS0 l a ch n h s chia xung vo.

T1CKPS1 T1CKPS000 1:101 1:210 1:4

11 1:8- bit 3 T1OSCEN bit i u khi n b dao ng Timer1

1= B dao ng ho t ng 0= B dao ng khng ho t ng

- bit 2 bit i u khi n xung clock ngoi ng b

khi TMR1CS=1

- bit2=0 c ng clock ngoai

=1 khng ng b clock ngoi

khi TMR1CS=0 bit ny khng c tc d ng- bit 1 TMR1CS bit l a ch n ngu n xung clock vo

TMR1CS=1 clock t chn RC0/T1OSO/T1CKI (s n ln)

TMR1CS=0 clock trong Fosc/4

- bit 0 bit b t t t Timer

1= Timer 1 enable

0=Timer 1 Disable

4.3.Timer 2

a/ Timer2: l b nh th i 8 bit bao g m m t b ti n nh (prescaler), m t b h u

nh Postscaler v m t thanh ghi chu k vi t t t l PR2. Vi c k t h p timer2 v i 2 b

nh t l cho php n ho t ng nh m t b inh th i 16 bit. Module timer2 cung

c p th i gian ho t ng cho ch i u bi n xung PWM n u module CCP c

ch n.


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b/ Ho t ng c a b Timer2

- Timer2 c dng ch y u ph n i u ch xung c a b CCP, thanh ghi

TMR2 c kh nng c v vi t, n c th xa b ng vi c reset l i thi t b . u vo c a xung c th ch n cc t s sau; 1:1; 1:4 ho c 1:16 vi c l a

ch n cc t s ny c th i u khi n b ng cc bit sau T2CKPS1 v bit

T2CKPS0.

- B Timer2 c 1 thanh ghi 8 bt PR2 . Timer 2 tng t gi tr 00h cho n

kh p v i PR2 v ti p theo n s reset l i gi tr 00h v l nh k ti p th c

hi n.Thanh ghi PR2 l m t thanh ghi c kh nng c v kh nng vi t.

c/ Thanh ghi T2CON: i u khi n ho t ng c a Timer2

- bit 7 khng s d ng SVTH: Tr n T ng Bng

V Vn Chnh 20

Hnh 11: S kh i Timer2

Hnh 12: C u trc thanh ghi T2CON i u khi n ho t ng c a Timer2

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- bit 6-3 TOUTPS3: TOUTPS0 bit l a ch n h s u ra Timer 2 0000=1:10001=1:20010=1:3

1111=1:16- bit 2 TMR2ON bit b t t t ho t ng Timer 2 1= enable0= disable

- bit 1- 0 T2CKPS1:T2CKPS0 ch n h chia u vo 00 = 1:101 = 1:41x=1:16

5. NG T (INTERRUPT):

- PIC16F877A c n 14 ngu n t o ra ho t ng ng t c i u khi n b i thanh

ghi INTCON (bit GIE). Bn c nh m i ng t cn c m t bit i u khi n v c ng t

ring. Cc c ng t v n c set bnh th ng khi th a mn i u ki n ng t x y ra

b t ch p tr ng thi c a bit GIE, tuy nhin ho t ng ng t v n ph thuc vo bit

GIE v cc bit i u khi n khc. Bit i u khi n ng t RB0/INT v TMR0 n m trong

thanh ghi INTCON, thanh ghi ny cn ch a bit cho php cc ng t ngo i vi PEIE. Bit

i u khi n cc ng t n m trong thanh ghi PIE1 v PIE2.C ng t c a cc ng t n m trong thanh ghi PIR1 v PIR2.

- Trong m t th i i m ch c m t ch ng tr nh ng t c th c thi, ch ng trnh

ng t c k t thc b ng l nh RETFIE. Khi ch ng trnh ng t c th c thi, bit

GIE t ng c xa, a ch l nh ti p theo c a ch ng trnh chnh c c t vo

trong b nh Stack v b m ch ng trnh s ch n a ch 0004h. L nh RETFIE

c dng thot kh i ch ng trnh ng t v quay tr v ch ng trnh chnh,

ng th i bit GIE cng s c set cho php cc ng t ho t ng tr l i. Cc c

hi u c dng ki m tra ng t no ang x y ra v ph i c xa b ng ch ng

trnh tr c khi cho php ng t ti p t c ho t ng tr l i ta c th pht hi n c

th i i m ti p theo m ng t x y ra.

- i v i cc ng t ngo i vi nh ng t t chn INT hay ng t t s thay i tr ng thi

cc pin c a PORTB (PORTB Interrupt on change), vi c xc nh ng t no x y ra

c n 3 ho c 4 chu k l nh ty thu c vo th i i m x y ra ng t.


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- C n ch l trong qu trnh th c thi ng t, ch c gi tr c a b m ch ng

trnh c c t vo trong Stack, trong khi m t s thanh ghi quan tr ng s khng c

c t v c th b thay i gi tr trong qu trnh th c thi ch ng trnh ng t.i u ny

nn c x l b ng ch ng trnh trnh hi n t ng trn x y ra.

- Cc ngu n ng t c a Pic 16F877A: 1) RTCC ho c TIMER0: ng t trn Timer0.

2) RB: ng t khi c s thay i tr ng thi 1 trong cc chn t RB4 n RB7

c a PORTB.

3) EXT: (External Interrupt) ng t ngoi khi c s thay i tr ng thi chn

RB0 ca PORTB.

4) AD: ng t khi b chuy n i tnh hi u t ng t sang tnh hi u s chuy n

i hon t t 1 tnh hi u.

5) TBE: ng t khi b m c a c ng RS232 r ng.

6) RDA: ng t khi c ng RS232 nh n tnh hi u.

7) TIMER1: ng t khi timer1 b trn.

8) TIMER2: ng t khi timer2 b trn.

9) CCP1; CCP2: ng t khi b capture ho c b Compare (b so snh i n p)

ho t ng; knh 1 ho c 2. 10) SSP: ng t khi SPI ho c I2C ho t ng.

11) PSP: ng t khi truy n nh n d li u song song.

12) BUSCOL: ng t khi xung t ng truy n.

13) EEPROM: ng t khi ghi xong d li u.

14) COMP: ng t sau khi th c hi n so snh tnh hi u.


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V i ti i u khi n t c ng c DC chng em s d ng hai lo i ngu n ng t l ng t ngoi khi c s thay i tr ng thi chn RB0 c a PORTB v ng t trn

Timer1, v th chng em s trnh by c th h n v nguyn l ho t ng v cc ci

t c a hai lo i ng t ny trong ph n d i y:

a/ Ng t ngoi (External Interrupt):

- Ng t ny d a trn s thay i tr ng thi c a pin RB0/INT. C nh tc ng gy

ra ng t c th l c nh ln hay c nh xu ng v c i u khi n b i bit

INTEDG (thanh ghi OPTION_ REG ). Khi c c nh tc ng thch h p xu t

hi n t i pin RB0/INT, c ng t INTF c set b t ch p tr ng thi cc bit i u

khi n GIE v PEIE. Ng t ny c kh nng nh th c vi i u khi n t ch

sleep n u bit cho php ng t c set tr c khi l nh SLEEP c th c thi.

- Thanh ghi OPTION_REG: a ch 81h, 181h

Thanh ghi ny cho php i u khi n ch c nng pull-up c a cc pin trong PORTB, xc


Hnh 13: S ho t ng ng t c a PIC 16F877A

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l p cc tham s v xung tc ng, c nh tc ng c a ng t ngo i vi RB0 (External

Interrupt) v b m Timer0.

Bit 7 PORTB pull-up enable bit

= 1 khng cho php ch c nng pull-up c a PORTB

= 0 cho php ch c nng pull-up c a PORTB

Bit 6 INTEDG Interrupt Edge Select bit

INTEDG = 1 ng t x y ra khi c nh d ng chn RB0/INT xu t hi n.

INTEDG = 0 ng t x y ra khi c nh m chn BR0/INT xu t hi n.

Bit 5 TOCS Timer0 Clock Source select bit

TOSC = 1 clock l y t chn RA4/TOCK1. TOSC = 0 dng xung clock bn trong (xung clock ny b ng v i xung clock

dng th c thi l nh).

Bit 4 TOSE Timer0 Source Edge Select bit

TOSE = 1 tc ng c nh ln.

TOSE = 0 tc ng c nh xu ng.

Bit 3 PSA Prescaler Assignment Select bit

PSA = 1 b chia t n s (prescaler) c dng cho WDT

PSA = 0 b chia t n s c dng cho Timer0

Bit 2:0 PS2:PS0 Prescaler Rate Select bit

Cc bit ny cho php thi t l p t s chia t n s c a Prescaler.


Hnh 14: C u trc thanh ghi OPTION_REG cho php ng t ngo i v ng t timer0

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b/ Ng t trn Timer1:

- C p thanh ghi TMR1H v TMR1L ch a gi tr m c a Timer1, chng tng t

ga tr 0000h n ga tr FFFFh n gi tr ny ti p t c tng th timer1 trn v

quay l i gi tr 0000h.V ng t xu t hi n khi trn qu gi tr FFFFh khi ny c

ng t TMR1IF s c t.Ng t c th ho t ng ho c khng ho t ng nh

vi c t ho c xa bt TMR1IE.

- Thanh ghi i u khi n Timer1 T1CON:

bit 7,6 khng s d ng

bit 5,4 T1CKPS1:T1CKPS0 l a ch n h s chia xung vo

T1CKPS1:T1CKPS0 t l chia u vo 00 1:1

01 1:2

10 1:4

11 1:8

bit 3 T1OSCEN bit i u khi n b dao ng Timer1

1= B dao ng ho t ng

0= B dao ng khng ho t ng

bit 2 bit i u khi n xung clock ngoi ng b

khi TMR1CS=1

bit2=0 c ng clock ngoi

=1 khng ng b clock ngoi

khi TMR1CS=0 bit ny khng c tc d ng

bit 1 TMR1CS bit l a ch n ngu n xung clock vo

TMR1CS=1 clock t chn RC0/T1OSO/T1CKI (s n ln)

TMR1CS=0 clock trong Fosc/4


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bit 0 bit b t t t Timer

1= Timer 1 enable

0=Timer 1 Disable

6. Ph ng php i u ch xung PWM: i u khi n t c ng c DC ng i ta c th dng nhi u ph ng php khc

nhau trong c m t ph ng php h t s c quan tr ng v thng d ng l ph ng php

i u ch r ng xung kch (PWM).

6.1. i u ch PWM l g?

Ph ng php i u ch r ng xung PWM (Pulse Width Modulation) l ph ng php

i u ch nh i n p ra t i hay ni cch khc l ph ng php i u ch d a trn s thay i r ng c a chu i xung kch i u khi n linh ki n ng ng t (SCR hay

Transistor) d n n s thay i i n p ra t i.

th d ng xung i u ch PWM

6.2. Nguyn l c a PWM:y l ph ng php c th c hi n theo nguyn t c dng ng t ngu n c t i m t

cch c chu k theo lu t i u ch nh th i gian ng ng t.Ph n t th c hi n nhi m v

ng c t l cc van bn d n.S nguyn l i u khi n t i dng PWM.


Hnh 15: th d ng xung i u ch PWM

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Trong kho ng th i gian 0 - to ta cho van Q1 m ton b i n p ngu n Ud c a ra t i.

Cn trong kho ng th i gian t t0 n T cho van Q1 kha, c t ngu n cung c p cho t i.V

v y v i th i gian t0 thay i t 0 cho n T ta s cung c p ton b , m t ph n hay kha hon ton i n p cung c p cho t i.

Cng th c tnh gi tr trung bnh c a i n p ra t i l:

Ud = Umax . (t0/T) hay Ud = Umax.D

Trong Ud: l i n p trung bnh ra t i.

Umax: l i n p ngu n.

t0: l th i gian xung s n d ng (van kha m )

. T: th i gian c th i gian xung s n d ng v s n m. D = t0/T: h s i u ch nh hay PWM c tnh b ng %

V d : i n p ngu n l 12V.

N u h s i u ch nh l 20% => U d = 12.20% = 2.4 V

N u h s i u ch nh l 50% => U d = 12.50% = 6 V

V v y, trong ti: i u khi n tc ng c DC chng em s d ng ph ng

php i u ch r ng xung PWM thay i i n p DC c p cho ng c t


Q1NPN

Q1(B)

PWM xung vung

TAI

NGUON

Hnh 16: S nguyn l dng PWM i u khi n i n p t i (tri) S xung van i u khi n v u ra (ph i)

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thay i t c c a ng c DC. i v i PIC16F877A s d ng ph ng php ny

ta c th s d ng b i u ch r ng xung (PWM) tch h p s n bn trong PIC v i 2

ng ra xung t i hai chn CCP1 (17) v CCP2 (16).T i cc chn ny khi ho t ng s

xu t chu i xung vung v i r ng i u ch nh c d dng.Xung ra ny dng

t o tn hi u ng ng t Trasistor trong m ch ng l c, v i r ng xc nh s t o ra

m t i n p trung bnh xc nh.

6.3. Cch thi t l p ch PWM cho PIC16F877A

- Khi ho t ng ch PWM (Pulse Width Modulation _ kh i i u ch

r ng xung), tnh hi u sau khi i u ch s c a ra cc pin c a kh i CCP

(c n n nh cc pin ny l output ). s d ng ch c nng i u ch ny

tr c tin ta c n ti n hnh cc b c ci t sau:

Thi t l p th i gian c a 1 chu k c a xung i u ch cho PWM (period) b ng

cch a gi tr thch h p vo thanh ghi PR2.

Thi t l p r ng xung c n i u ch (duty cycle) b ng cch a gi tr vo

thanh ghi CCPRxL v cc bit CCP1CON.

i u khi n cc pin c a CCP l output b ng cch clear cc bit t ng ng trong

thanh ghi TRISC.

Thi t l p gi tr b chia t n s prescaler c a Timer2 v cho php Timer2 ho t ng b ng cch a gi tr thch h p vo thanh ghi T2CON.

Cho php CCP ho t ng ch PWM.

- Trong gi tr 1 chu k (period) c a xung i u ch c tnh b ng cng th c:

- o rong cua xung ieu che (duty cycle) c tnh theo cong

thc:


PWM period = [(PR2) +1]*4*TOSC

*(gia tr bo chia tan socua TMR2).

PWM duty cycle = (CCPRxL:CCPxCON)*TOSC

*(gia tr bo chia tanso TMR2)

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- Khi gia tr thanh ghi PR2 bang vi gia tr thanh ghi TMR2 th

qua trnh sau xay ra: Thanh ghi TMR2 t ng c xa.

Pin c a kh i CCP c set.

Gi tr thanh ghi CCPR1L (ch a gi tr n nh r ng xung i u ch duty

cycle) c a vo thanh ghi CCPRxH.

II. M ch c u H ( H-Bridge Circuit ).

1/ Cng d ng v nguyn l ho t ng: M ch c u H l m t m ch i n gip o chi u dng i n qua m t i

t ng . i t ng l ng c DC m chng ta c n i u khi n .M c ch i u khi n

l cho php dng i n qua i t ng theo chi u A n B ho c B n A .T gip

i chi u quay c a ng c .

Hi n nay, ngoi lo i m ch c u H c thi t k t cc linh ki n r i nh : BJT

cng su t, Mosfet, Cn c cc lo i m ch c u H c tch h p thnh cc IC nh :

L293D v L298D. Do i t ng i u khi n trong ti ny l ng c DC c i n


Hnh 17: S kh i CCP (PWMmode)(tri) Cc tham s c a PWM (ph i)

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p 12V v cng sut nh nn chng em dng m ch c u H o chi u ng c l IC

L298.

Hnh 18: M ch c u H

Kh o st ho t ng c a m ch c u H

Hnh19: Nguyn l ho t ng c a m ch c u H


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2/ M ch c u H L298D:

L298D l m t chip toch1 h p 2 m ch trong gi 15 chn. L298D c i n p danh

ngha cao (l n h n 50V) v dng i n danh ngha l n h n 2A nn r t thch h p cho

cc ng d ng cng su t nh nh cc ng c DC lo i v a v nh .


Hnh 20: S chn c a IC L298D (ph i) IC L298D (tri)

Hnh 21: S nguyn l c a IC L298D

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C 2 m ch c u H trn m i chip L298D nn c th i u khi n 2 i t ng ring v i 1

chip ny. M i m ch c u H bao g m 1 ng ngu n Vs (th t ra l ng chung cho 2

m ch c u), m t chn current sensing (c m bi n dng) ph n cu i c a m ch c u H,

chn ny khng c n i t m b tr ng cho ng i dng n i 1 i n tr nh g i

l sensing resistor.B ng cacch1 o i n p r i trn i n tr ny chng ta c th tnh

c dng qua i n tr , cng l dng qua ng c , m c ch c a vi c ny l xc

nh dng qu t i. N u vi c o l ng l khng c n thi t th ta c th n i chn ny

v i GND. ng c s c n i v i 2 chn OUT1, OUT2 ho c OUT3, OUT4.Chn

EN (ENA v ENB) cho php m ch c u ho t ng, khi chn ny c ko ln m c

cao.

L298D khng ch c dng o chi u ng c m cn i u khi n v n t c ng

c b ng PWM.Trong th c t , cng su t th c ma L298D c th t i nh h n gi tr

danh ngha c a n (U =50V, I =2A). tng dng t i c a chp ln g p i, chng ta

c th n i hai m ch c u H song song v i nhau (cc chn c ch c nng nh nhau c a 2

m ch c u c n i chung).

III/LCD

1/Ch c nng v hnh d ng LCD. Ngy nay, thi t b hi n th LCD (Liquid Crystal Display) c s d ng trong r t

nhi u cc ng d ng c a vi i u khi n.LCD c r t nhi u u i m so v i cc d ng

hi n th khc: n c kh nng hi n th k t a d ng, tr c quan (ch , s v k t

h a), d dng a vo m ch ng d ng theo nhi u giao th c giao ti p khc nhau, t n

r t t ti nguyn h th ng v gi thnh r


Hnh 22: LCD v s chn

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2/ Ch c nng cc chnB ng Ch c nng cc chn c a LCD

* Ghi ch: ch c, ngha l MPU s c thng tin t LCD thng qua cc chn DBx.

Cn khi ch ghi,ngha l MPU xu t thng tin i u khi n cho LCD thng qua

cc chn DBx.


Chns Tn Ch c nng

1 VSS

Chn n i t cho LCD, khi thi t k m ch ta n i chn ny v i GND c a m ch i u khi n

2 VDD

Chn c p ngu n cho LCD, khi thi t k m ch ta n i chn ny v i VCC=5V c a m ch i u khi n

3 Vee Chn ny dng i u ch nh t ng ph n c a LCD.

4 RS

Chn ch n thanh ghi (Register select). N i chn RS v i logic 0 (GND) ho c logic 1 (V CC) ch n thanh ghi. + Logic 0: Bus DB0-DB7 s n i v i thanh ghi l nh IR c a LCD

( ch ghi - write) ho c n i v i b m a ch c a LCD ( ch c - read) . + Logic 1: Bus DB0-DB7 s n i v i thanh ghi d li u DR bn

trong LCD

5 R/W

Chn ch n ch c/ghi (Read/Write). N i chn R/W v i logic 0

LCD ho t ng ch ghi, ho c n i v i logic 1 LCD ch c.

6 E

Chn cho php (Enable). Sau khi cc tn hi u c t ln bus DB0- DB7, cc l nh ch c ch p nh n khi c 1 xung cho php c a chn E.+ ch ghi: D li u bus s c LCD chuy n vo (ch p

nh n) thanh ghi bn trong khi pht hi n m t xung (high-to-low transition) c a tn hi u chn E. + ch c: D li u s c LCD xu t ra DB0-DB7 khi pht

hi n c nh ln (low-to-high transition) chn E v c LCD gi bus n khi no chn E xu ng m c th p.

7-14DB0-

DB7

Tm ng c a bus d li u dng trao i thng tin v i MPU. C 2 ch s d ng 8 ng bus ny : + Ch 8 bit: D li u c truy n trn c 8 ng, v i bit MSB

l bit DB7.

+ Ch 4 bit: D li u c truy n trn 4 ng t DB4 t i DB7, bit MSB l DB7.

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3/ c tnh i n c a cc chn giao ti p:

LCD s b h ng nghim tr ng, ho c ho t ng sai l ch n u b n vi ph m kho ng c tnh i n sau y:

Chn c p ngu n (Vcc-GND) Min:-0.3V , Max+7VCc chn ng vo (DBx, E, ) Min:-0.3V , Max:

(Vcc+0.3V)

Nhi t ho t ng Min:-30C , Max:+75CNhi t b o qu n Min:-55C , Max:+125C

4/ T p l nh c a LCD:

Cc l nh c a LCD c th chia thnh 3 nhm nh sau:

Cc l nh v ki u hi n th . VD: Ki u hi n th (1 hng / 2 hng), chi u di d li u (8 bit / 4 bit),

Ch nh a ch RAM n i.

Nhm l nh truy n d li u trong RAM n i. V i m i l nh, LCD c n m t kho ng th i gian hon t t, th i gian ny c th kh

lu i v i t c c a MPU, nn ta c n ki m tra c BF ho c i (delay) cho LCD

th c thi xong l nh hi n hnh m i c th ra l nh ti p theo.

Tn l nh Ho t ng Texe

(max)Clear

Display

M l nh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

DBx = 0 0 0 0 0 0 0 1

L nh Clear Display (x a hi n th ) s ghi m t kho ng tr ng-

blank (m hi n k t 20H) vo t t c nh trong DDRAM,

sau tr b m a AC=0, tr l i ki u hi n th g c n u n

b thay i. Ngha l : T t hi n th , con tr d i v g c tri (hng

u tin), ch tng AC. SVTH: Tr n T ng Bng

V Vn Chnh 34

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Return

home


DB0

DBx = 0 0 0 0 0 0 1 *

L nh Return home tr b m a ch AC v 0, tr l i ki u hi n th g c n u n b thay i. N i dung c a DDRAM khng

thay i.

1.52

ms

Entry

mode set


DB0

DBx = 0 0 0 0 0 1 [I/D] [S]

I/D : Tng (I/D=1) ho c gi m (I/D=0) b m a ch hi n th

AC 1 n v m i khi c hnh ng ghi ho c c vng

DDRAM. V tr con tr cng di chuy n theo s tng gi m ny.

S : Khi S=1 ton b n i dung hi n th b d ch sang ph i

(I/D=0) ho c sang tri (I/D=1) m i khi c hnh ng ghi vng

DDRAM. Khi S=0: khng d ch n i dung hi n th .

N i dung hi n th khng d ch khi c DDRAM ho c c/ghi

vng CGRAM.

37 us

Display

on/off

control


DB0

DBx = 0 0 0 0 1 [D] [C] [B]

D: Hi n th mn hnh khi D=1 v ng c l i. Khi t t hi n th ,

n i dung DDRAM khng thay i.

C: Hi n th con tr khi C=1 v ng c l i. V tr v hnh d ng

con tr , xem hnh 8

B: Nh p nhy k t t i v tr con tr khi B=1 v ng c l i.

Xem thm hnh 8 v ki u nh p nhy. Chu k nh p nhy

kho ng 409,6ms khi m ch dao ng n i LCD l

250kHz

37 us

Cursor or

display


DB0

37 us


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shift DBx = 0 0 0 1 [S/C] [R/L] * *

L nh Cursor or display shift d ch chuy n con tr hay d li u

hi n th sang tri m khng c n hnh ng ghi/ c d li u.

Khi hi n th ki u 2 dng, con tr s nh y xu ng dng d i khi

d ch qua v tr th 40 c a hng u tin. D li u hng u v

hng 2 d ch cng m t lc.

Function

set


DB0

DBx = 0 0 1 [DL] [N] [F] * *

DL: Khi DL=1, LCD giao ti p v i MPU b ng giao th c 8 bit (t bit DB7 n DB0).

Ng c l i, giao th c giao ti p l 4 bit (t bit DB7 n bit

DB0). Khi ch n giao th c 4 bit, d li u c truy n/nh n

2 l n lin ti p. v i 4 bit cao g i/nh n tr c,

4 bit th p g i/nh n sau.

N: Thi t l p s hng hi n th . Khi N=0: hi n th 1 hng, N=1:

hi n th 2 hng.

F: Thi t l p ki u k t . Khi F=0: ki u k t 5x8 i m nh,

F=1: ki u k t 5x10 i m

* Ch :

Ch th c hi n thay i Function set u ch ng trnh. V sau khi c th c

thi 1 l n, l nh thay i Function set khng c LCD

ch p nh n n a ngo i tr thi t l p chuy n i giao

th c giao ti p.

Khng th hi n th ki u k t 5x10 i m nh ki u hi n th 2 hng

37 us

Set

CGRAM


DB0

37 us


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address DBx = 0 1 [ACG][ACG][ACG][ACG][ACG]

[ACG]

L nh ny ghi vo AC a ch c a CGRAM. K hi u [ACG] ch

1 bit c a chu i d li u

6 bit. Ngay sau l nh ny l l nh c/ghi d li u t CGRAM

t i a ch c ch nh

Set

DDRAM

address


DB0

DBx = 1 [AD] [AD] [AD] [AD] [AD] [AD]

[AD]

L nh ny ghi vo AC a ch c a DDRAM, dng khi c n thi t

l p t a hi n th mong mu n. Ngay sau l nh ny l l nh

c/ghi d li u t DDRAM t i a ch c ch nh.

Khi ch hi n th 1 hng: a ch c th t 00H n 4FH.

Khi ch hi n th 2 hng, a ch t 00h n 27H cho

hng th nh t, v t 40h n 67h cho hng th 2.

Xem chi ti t hnh 4.

37 us

Read BF

and

address


DB0

DBx = [BF] [AC] [AC] [AC] [AC] [AC] [AC]

[AC] (RS=0, R/W=1)

Nh c p tr c y, khi c BF b t, LCD ang lm

vi c v l nh ti p theo (n u

c) s b b qua n u c BF ch a v m c th p. Cho nn, khi

l p trnh i u khi n, b n ph i ki m tra c BF tr c khi ghi

d li u vo LCD.

Khi c c BF, gi tr c a AC cng c xu t ra cc bit

[AC]. N l a ch c a

CG hay DDRAM l ty thu c vo l nh tr c c

0 us

Write M l nh : DBx = DB7 DB6 DB5 DB4 DB3 DB2 DB1 37 us


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data to

CG or

DDRAM

DB0

DBx = [Write data]

(RS=1, R/W=0)

Khi thi t l p RS=1, R/W=0, d li u c n ghi c a vo cc chn DBx t m ch

ngoi s c LCD chuy n vo trong LCD t i a ch c

xc nh t l nh ghi a ch tr c (l nh ghi a ch cng

xc nh lun vng RAM c n ghi)

Sau khi ghi, b m a ch AC t ng tng/gi m 1 ty

theo thi t l p Entry mode.

L u l th i gian c p nh t AC khng tnh vo th i gian th c

thi l nh.

Read

data from

CG


DB0

DBx = [Read data] (RS=1, R/W=1)

37 us

IV. i t ng i u khi n: ng c DC

- y l ng c s d ng trong ti:


Hnh 23: ng c DC c g n encoder s d ng trong n

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- Bn trong ng c c g n m t encoder ng tr c v i n dng xc nh t c

v v tr c a ng c .

- Cc thng s c a ng c nh sau:

+ i n p DC c p cho ng c : 12VDC

+ T c t i a 2000 vng/pht

+ S xung c a encoder 60xung/vng

+ i n c m L=102mH

- ng c c t t c 5 dy ra:

+ 2 dy cung c p ngu n 12 V cho ng c + 2 dy ngu n 5V cung c p ngu n cho encoder

+ 1 dy tn hi u a xung encoder ra ngoi

- Ph ng php i u khi n : Thay i t c ng c b ng cch thay i p c p vo

cho ng c .

- Nguyn l ho t ng c a c m bi n encoder: c nhi u lo i encoder khc nhau.

M i lo i l i c m t nguyn l ho t ng khc nhau, trong khun kh bo co

n, em xin trnh by ph n nguyn l lo i encoder trong ti m em s d ng:

incremental encoder.

-

M hnh th 1


Hnh 24: Encoder

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Incremental encoder v c b n l m t a trn quay quanh m t tr c c c l

nh hnh trn.

2 bn m t c a ci a trn , s c m t b thu pht quang. Trong qu trnh

encoder quay quanh tr c, n u g p l r ng th nh sng chi u qua c, n u g p

mnh ch n th tia sng khng chi u qu c. Do tn hi u nh n c t sensor

quang l m t chu i xung.M i encoder c ch t o s bi t s n s xung trn m t

vng. Do ta c th dng vi i u khi n m s xung trong m t n v th i gian

v tnh ra t c ng c .

Encoder m em s d ng trong n c a mnh, hon ton gi ng v i m hnh trn.

Tuy nhin, m hnh trn c nh c i m l n l: ta khng th xc nh c ng c

quay tri hay quay ph i, v c quay theo chi u no i n a th ch c m t d ng xung

a ra. Ngoi ra i m b t u c a ng c , ta cng khng th no bi t c.

C i ti n m hnh 1 b ng m hnh 2 nh sau: SVTH: Tr n T ng Bng

V Vn Chnh 40

B thupht quang

a kh cv ch

Hnh 25: C u t o Encoder

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M hnh th 2

Trong m hnh ny, ng i ta c t t c l 2 vng l . Vng ngoi cng gi ng

nh m hnh 1, vng gi a l ch pha so v i vng ngoi l 90 . Khi , d ng xung ra

t 2 vng trn nh sau :

Hai xung a ra t 2 vng l ch nhau 90 , n u vng ngoi nhanh pha h n vng

trong th ch c ch n ng c quay t tri sang ph i v ng c l i.


Hnh 27: th xung c a encoder c 2 vng v ch l nh pha nhau 90 0

Hnh 26: a kh c 2 cng v ch l ch pha nhau 90 0

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L vng trong cng dng pht hi n i m b t u c a ng c .C th vi t

ch ng trnh cho vi i u khi n nh n bi t: n u c m t xung pht ra t vng trong

cng ny, t c l ng c quay ng m t vng.

V i nh ng c tnh trn, encoder dng r t ph bi n trong vi c xc nh v tr gc

c a ng c .. M t lo i encoder th 2 cng ph bi n hi n nay, l: absolute encoder.

M hnh a quang c a lo i ny nh sau:

CH NG 3:

THI T K M CH PH N C NG

CODE CH NG TRNH V L U GI I THU T

I/ THI T K M CH PH N C NG:


Hnh 28: a kh c nhi u vng v ch khc nhau

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M ch c thi t k g m c cc kh i nh sau: kh i ngu n, kh i bn phm, kh i hi n

th , kh i m ch cng su t, kh i i u khi n.

1/Kh i ngu n:

M ch l y ngu n xoay chi u qua adapter AC/DC 220VAC/12VDC , v c n p nh

IC 7805.S nguyn l m ch:

Ch c nng c a cc ph n t trong m ch:

- IC 7805: ch c nng n p i n p 5V

- C4 t ha (c phn c c) n p ng vo, i n dung c a t ny cng l n th i n

p vo IC 7805 cng ph ng.

- C5 v C7 t gi y (khng phn c c) l hai t l c nhi u t ng s cao ng vo

v ng ra.

- C6 t ha c tc d ng d p dao ng t kch khi s d ng IC n p dng 78xx.

2/ Kh i m ch bn phm:

M ch bn phm g m 16 phm, c b tr thnh 4 hng v 4 c t nh hnh v :


VI1

VO3

GND

2

U2

7805

3

2

1

J1

JACK C4

100uF

C5

100nF

C6

100uF

C7

100nF

D8

LED

R26

1k

+12V +5V

1

2

J2

TERMINAL2

Hnh 29: Kh i m ch n p

Hnh 30: IC7805

B4B5

B6

B7

A0A1

A2

A3

1 2

PHIM 1

BUTTON

1 2

PHIM 4

BUTTON

1 2

PHIM 7

BUTTON

1 2PHIM 16

0

1 2

PHIM 2

BUTTON

1 2

PHIM 5

BUTTON

1 2

PHIM 8

BUTTON

1 2PHIM 15

SAVE

1 2

PHIM 3

BUTTON

1 2

PHIM 6

BUTTON

1 2

PHIM 9

BUTTON

1 2PHIM 14

CLEAR

1 2

PHIM 10

FW

1 2

PHIM 11

RV

1 2

PHIM 12

STOP

1 2PHIM 13

ENTER

1

2

3

4

56

7

8

J1

SIL-100-08

1

23

J2

SIL-100-03

R1

10k

R2

10k

R3

10k

R4

10k

Hnh 31: Kh i m ch bn

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B n hng c n i v i Port B (t B4 n B7) c a vi x l, b n c t c n i v i Port

A (t A0 n A3) c a vi x l v c n i v i ngu n VCC qua i n tr (ngha l cc

chn c a Port A t A0 n A3 s lun nh n m c 1 khi khng c phm nh n), vi c

lm ny nh m ph c v cho gi i thu t qut phm s c trnh by ph n sau.

Trong s 16 phm c 10 phm nh p d li u s t 0 n 9, 6 phm i u khi n (FW,

RV, STOP, ENTER, CLEAR, SAVE).

Ngu n VCC trong s m ch bn phm l 5V, c c p t kh i m ch n p trn.V m ch bn phm truy n nh n d li u tr c ti p v i PIC nn c n i n p n

nh.

3/Kh i m ch hi n th :

M ch hi n th bao g m mn hnh LCD giao ti p v i PIC qua Port D v i giao th c 4

bit, ngoi ra cn c bi n tr i u ch nh sng c a LCD.

Ngoi ra, cn c kh i hi n th g m 8 led n c h n dng b ng i n tr 220, c

tc d ng text ch ng trnh,cc kh i khc v cng c dng bo hi u o

chi u trong ch c ci t th i gian.


D7

14

D6

13

D5

12

D4

11

D3

10

D2

9

D1

8

D0

7

E

6

RW

5

RS

4

VSS

1

VDD

2

VEE

3

K

16

A

15

LCD1

RT1602C

D0D1D2

D7

D6

D5

D4

48%

RV1

10k

Hnh 32: Kh i m ch LCD v LED n

1 2 3 4 5 6 7 8

J5

SIL-100-08

D2

LED

D3

LED

D4

LED

D5

LED

D6

LED

D7

LED

D9

LED

D10

LED

R2

330

R3

330

R4

330

R5

330

R6

330

R7

330

R8

330

R9

330

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4/Kh i m ch cng su t:

M ch cng su t s d ng IC c u H L298, v i 2 knh A v B,m i knh v i i n p

nh m c 50V v dng nh m c cho t i l 2A.Khi u song song 2 knh ta c dng c p cho t i ln n 4A (g p i).i n p i u khi n 5V.

C u Diode dng ch ng dng i n ng c, do t i ng c c tnh ch t c m

khng.Ngu n c p cho ng c 12V

S dung IC c u H ny, khng nh ng dng o chi u ng c m cn i u

khi n t c ng c b ng ph ng php bm xung (PWM). SVTH: Tr n T ng Bng

V Vn Chnh 45

IN15

IN27

ENA6

OUT12

OUT23

ENB11

OUT313

OUT414

IN310

IN412

SENSA1

SENSB15

GND

8

VS

4

VCC

9 U1

L298

+12V

+88.8

R1

0.5

R2

0.5

D11N4007

D21N4007

D31N4007

D41N4007

+12V

1

2

3

J1

Encoder

M1

M2

M1 M2

1

2

J2

Motor

M1

M2

CLK

CLK1

2

J4

Motor

+12V

1

2

3

4

5

J3

SIL-100-05

Hnh 33: Kh i m ch cng su t s s ng IC L298

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5/ Kh i m ch i u khi n:

Vi i u khi n trung tm l PIC 16F877A.V i ch c nng c a cc port nh sau:

Port A (t A0 n A3) c set l ng vo nh n tnh hi u t 4 c t c a bm

phm.

Port B (t B3 n B7) l ng ra xu t tnh hi u ra 4 hng c a kh i bn phm,

chn RB0 nh n tnh hi u xung t Encoder (v ng t ngoi x y ra khi tnh hi u

thay i trn chn RB0);

Ta s dung 2 chn RC1(CCP2) v RC2 (CCP1) c a Port C xu t tnh hi u

PWM i u khi n ng c .

Port D (tr chn RD3) g i tnh hi u n kh i hi n th LCD.Ba chn t RD0

n RD2 n i v i 3 chn i u khi n c a LCD.B n chn t RD4 n RD7 n i v i 4 bt cao c a cc chn nh n d li u c a LCD.

Th ch anh dng trong m ch gi tr 20MHz, v i 2 t C1,C2 l t gi y v i i n dung

33uF. Pic reset khi chn s 1 MCLR n i mass.T C3 c tc d ng ch ng nhi u chn

s 1.

II/ Gi i thi u v ch ng trnh vi t code v bin d ch:

Trong n ny nhm chng em s d ng ch ng trnh vi t code CCS, ch ng trnh

cho php l p trnh ngn ng C cho vi i u khi n PIC c a Microchip. SVTH: Tr n T ng Bng

V Vn Chnh 46

RA0/AN02

RA1/AN13

RA2/AN2/VREF-/CVREF4

RA4/T0CKI/C1OUT6

RA5/AN4/SS/C2OUT7

RE0/AN5/RD8

RE1/AN6/WR9

RE2/AN7/CS10

OSC1/CLKIN13

OSC2/CLKOUT

14

RC1/T1OSI/CCP216

RC2/CCP117

RC3/SCK/SCL18

RD0/PSP019

RD1/PSP120

RB7/PGD40

RB6/PGC39

RB538

RB437

RB3/PGM36

RB2 35RB1

34RB0/INT

33

RD7/PSP7 30RD6/PSP6

29RD5/PSP5

28RD4/PSP4

27RD3/PSP3

22RD2/PSP2

21

RC7/RX/DT26

RC6/TX/CK25

RC5/SDO24

RC4/SDI/SDA23

RA3/AN3/VREF+5

RC0/T1OSO/T1CKI15

MCLR/Vpp/THV1

U1

PIC16F877A

RSRW

E

D7D6

D5

D4

12

34

5

J3

SIL-100-05

X1

20M

C2

33

C1

33

1

2

34

56

7

8

J4

SIL-100-08

R1R2

R3R4

C1

C2

C3

C4

C1

C2

C3

C4

R4

R3

R2

R1

C3

10uF

R1

10k

SW1

BUTTON

D1

1N4148

1

2

3

45

67

8

J6

SIL-100-08

1

2

34

56

7

8

J7

SIL-100-08

1

2

345

67

8

J8

SIL-100-08

12

3

J9

SIL-100-03

1

2

34

56

J10

SIL-100-06

R10

10k

Hnh 34: Kh i m ch i u khi n PIC 16F877A

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Ch ng trnh ny c cc cu l nh n gi n, d hi u, h tr bin d ch v i ch c nng

hi n th l i v c nh bo ch ng trnh khng kh d ng. Ngoi ra n cn c th bin

d ch t code C ra file.hex v c code Assemble.

C u trc 1 ch ng trnh trong CCS:

- u tin l cc ch th ti n x l : ( # . . . ) c nhi m v bo cho CCS c n s

d ng nh ng g trong ch ng trnh C nh dng vi x l g , c dng giao ti p PC

khng , ADC khng , DELAY khng , c s d ng ng t hay khng

- Cc khai bo bi n.

- Cc hm con.

- Cc hm ph c v ng t theo sau b i 1 ch th ti n x l cho bi t dng ng t no. - Ch ng trnh chnh.

V d v c u trc 1 ch ng trnh trong CCS:

//------khai bo ti n x l-------

#include

#device PIC16F877 *=16 ADC=10

#use delay (clock=20000000)

// khai bo them n u c

//------khai bo bi n-------

Int a,b;

Int16 x,y;

..

//----------cc ch ng trnh con-------SVTH: Tr n T ng Bng

V Vn Chnh 47

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Void xu_ly_ADC ()

{

}

Int cai_dat_PWM ()

{.

Return(bi n);}

//------hm ng t-------

#INT_TIMER1

Void xu_ly_ngt()

{

}

//-------ch ng trnh chnh--------

Void main()

{

..}

III/ L u gi i thu t:

L u gi i thu t g m: l u ch ng trnh chnh, ch ng trnh qut phm, ch ng trnh ng t c a timer1. Ch ng trnh chnh l 1 vng l p v h n c nh ng ch ng trnh con nh :

qut phm, check phm, ch n ch , tnh PWM, nh p d li u t c , nh p d li u th i gian, save vo epprom.

Ch ng trnh qut phm th hi n gi i thu t nh n phm nh n v nh n bi t gi tr c a phm (phm nh n l phm no) .

Ch ng trnh ng t timer 1 c tc d ng c p nh t gi tr t c , tnh ton gi tr PWM, v xu t tnh hi u n kh i hi n th .


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CODE CH NG TRNH#include"E:/TL/DOAN2\cauH\MACH\15\main.h"#include

//#include //dung cac ham toan hoc#use delay(clock=20000000)

#use fast_io(a)#use fast_io(b)#use fast_io(c)#use fast_io(d)

//==================khai bao ham con=============int quetphim();

int checkphim(b);void pwm();

void ghi_tocdo();void ghi_thoigian();

void clear();void read_rom();//==================khai bao bien================int8 i,t,a,b,c,d,sttphim,duty,ct,l,m;

int16 s_xung,s_vong,setpoint,error,luu,tg,tg1,dem;//================ bien luu eeprom==============

int8 e0,e1,e2,e3,j,k;int16 e;//================chuong trinh quet phim==========//quet phim so

int quetphim(){

output_b(0xe0);// B4=0a=0;b=1;checkphim(b);

if (a!=0){delay_ms(200);

return (sttphim);}output_b(0xd0);// B5=0

a=0;b=2;

checkphim(b);if (a!=0){delay_ms(200);return (sttphim);}

output_b(0xb0);// B6=0a=0;

b=3;checkphim(b);

if (a!=0)


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{delay_ms(200);return (sttphim);}

output_b(0x70);// B6=0a=0;

b=4;checkphim(b);

if (a!=0){delay_ms(200);return (sttphim);}}

//============chuong trinh check phim=============int checkphim(b)

{switch (b){case 1:

if(!input(pin_a0)){sttphim=1;

a=1;}else if(!input(pin_a1)){sttphim=2;a=1;}

else if(!input(pin_a2)){sttphim=3;

a=1;}else if(!input(pin_a3))

{ sttphim=10;//thuana=1;}

else {}break;

case 2:

if(!input(pin_a0)){sttphim=4;

a=1;}

else if(!input(pin_a1)){sttphim=5;a=1;}


a=1;}else if(!input(pin_a3)){sttphim=11;//nghicha=1;}

else {}

break;


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case 3:if(!input(pin_a0))

{sttphim=7;a=1;}


a=1;}else if(!input(pin_a2)){sttphim=9;a=1;}

else if(!input(pin_a3)){sttphim=12;//stop

a=1;}else {}break;

case 4:if(!input(pin_a0))

{sttphim=0;//0a=1;}else if(!input(pin_a1)){sttphim=15;//save

a=1;}else if(!input(pin_a2))

{sttphim=14;//cleara=1;}

else if(!input(pin_a3)){sttphim=13;//set

a=1;}else {}break;}return (sttphim);

}// chuong trinh nhan xung tu encoder

//ngat ngoai, nhan xung tu encoder

#int_extvoid RB0_isr(){

s_xung++;//dem so xung o chan RB0}

//ngat timer1, tinh toan pwm va hien thi#int_timer1void timer1_isr(){

set_timer1(-62500);

if (t==5){


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S_vong=s_xung*2;//xung tren phut//ht

lcd_gotoxy(1,1);printf(lcd_putc," ");

if(ct==1){

lcd_gotoxy(1,1);printf(lcd_putc,"TD_dat=%lu v/p",luu);}else {lcd_gotoxy(1,1);

printf(lcd_putc,"TG_dat=%lu s",tg);}lcd_gotoxy(1,2);

printf(lcd_putc," ");if (d==2){lcd_gotoxy(1,2);printf(lcd_putc,"TD_tt=-%luv/p",s_vong);}

if (d==1){lcd_gotoxy(1,2);

printf(lcd_putc,"TD_tt= %luv/p",s_vong);}//=========================//xuat pwmpwm();

//========================s_xung=0;

s_vong=0;t=0;

set_timer1(-62500);}

elset++;set_timer1(-62500);}

//ngat timer0, dat thoi gian#int_timer0

void time0_irs()

{set_timer0(-235);if (dem>=tg1)

{output_high(pin_e0);

delay_us(100);output_low(pin_e0);dem=0;if (d==1)

{d=2;}

else if (d==2)


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{d=1;}else{}

set_timer0(-235);}

else {dem++;

set_timer0(-235);}}//chuong trinh chinhvoid main()

{i=0;

sttphim=0;setpoint=0;tg=0;duty=0;c=0;

d=0;ct=0;l=0;m=0;

e0=0;e1=0;e2=0;e3=0;e=0;k=0;//============================================================//1:ngo vao;0: la ngo ra

set_tris_b(0b00001111);//4 chan RB4-RB7 xuat du lieu ra ban phimset_tris_a(0b00001111);//4 chan RA0-RA3 nhan du lieu tu ban phim

set_tris_c(0b00000000);//2 chan RC0 va RC1 xuat PWMset_tris_D(0b00000000);//port D la port xuat du lieu ra LCD

//============================================================

setup_timer_1(T1_INTERNAL|T1_DIV_BY_8);/* timer1 la bo dinh thoi su dung xung noi,bo chia 1:8 thay doi moi1600nsDung timer1 de ngat moi 0.1s do vay ta dat gia tri cho timer1 la :

0.1s/1600ns=62500(D)=F424(H) =>gia tri nap la FFFF-F424=BDB*/setup_timer_0(RTCC_INTERNAL|RTCC_DIV_256);

enable_interrupts(int_ext);//khoi dong ngat ngoai

ext_int_edge(H_TO_L); // xung tu cao xuong thapenable_interrupts(global);// khoi dong bit ngat GIEsetup_timer_2(T2_DIV_BY_4,249,1);

/*timer2 dung dinh thoi cho bo PWMmode: bo chia thoi gian (prescale) cua timer2 1:4

period: gia tri nap chi thanh ghi PR2postscale : bo chi ra,chon 1:1 PWM khong dungThach anh 20MHz, PWM fre: 10000Hz, thay doi duty cycle(%) dethay doi toc do*/

setup_ccp1(CCP_PWM);

setup_ccp2(CCP_PWM);


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set_pwm1_duty(0);set_pwm2_duty(0);

//===========================================================

lcd_init()lcd_send_byte(0,0x01);

lcd_gotoxy(1,1);printf(lcd_putc,"CHUONG TRINH DK ");lcd_gotoxy(1,2);printf(lcd_putc," TD DONG CO DC ");

delay_ms(1000);lcd_gotoxy(1,1);

printf(lcd_putc," ");lcd_gotoxy(1,2);printf(lcd_putc," ");read_rom();

lcd_gotoxy(1,1);printf(lcd_putc,"CHON CHE DO :_ ");

while (true){while (c==0){

quetphim();if (a!=0)

{if (sttphim==1)

{ ct=1;c=1;

lcd_gotoxy(1,1);printf(lcd_putc,"CHON CHE DO :_%u",ct);}if (sttphim==2){ ct=2;

c=1;lcd_gotoxy(1,1);

printf(lcd_putc,"CHON CHE DO :_%u",ct);}

}}if (ct==1)

{lcd_gotoxy(1,1);printf(lcd_putc,"TD_dat=_ v/p");

lcd_gotoxy(1,2);printf(lcd_putc,"TD_luu=%lu v/p",e);}else {lcd_gotoxy(1,1);

printf(lcd_putc,"TD_dat=_ v/p");

lcd_gotoxy(1,2);


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printf(lcd_putc,"TG_dat=_ s");}While (c==1)

{quetphim();

if (a!=0)

{if (sttphim>=0 && sttphim9{if (m==0)

{ghi_tocdo();}if((ct==2)&&(m==1))

{ghi_thoigian();}}if (sttphim==14){clear();}

if ((sttphim==13)&&(i==0)&&(e==0)){

lcd_gotoxy(1,1);printf(lcd_putc," ");lcd_gotoxy(1,1);printf(lcd_putc,"Phai nhap TD_dat");

delay_ms(1000);lcd_gotoxy(1,1);

printf(lcd_putc," ");lcd_gotoxy(1,1);

printf(lcd_putc,"TD_dat=_");}

if ((sttphim==15)&&(i!=0)) //luu vao eeprom{write_eeprom(0,e0);delay_ms(100);

write_eeprom(1,e1);delay_ms(100);

write_eeprom(2,e2);

delay_ms(100);write_eeprom(3,e3);delay_ms(100);

write_eeprom(4,i);delay_ms(100);

lcd_gotoxy(1,2);printf(lcd_putc," ");lcd_gotoxy(1,2);printf(lcd_putc," LUU THANH CONG ");

}

if ((sttphim==13)&&((i!=0)||(e!=0)))


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{if (ct==1)

{c=2;

if (e!=0 && i==0)luu=e;}

if ((ct==2)&&(l>=2)){c=2;}m=1;

}}}while (c==2)

{quetphim();if(a!=0){

if(sttphim==10){

lcd_gotoxy(1,2);printf(lcd_putc," ");lcd_gotoxy(1,2);printf(lcd_putc," QUAY THUAN ");

if (ct==2){enable_interrupts(int_timer0);

set_timer1(-235);}enable_interrupts(int_timer1);

enable_interrupts(global);set_timer1(-62500);

set_pwm1_duty(duty);d=1;}if (sttphim==11)

{lcd_gotoxy(1,2);

printf(lcd_putc," ");

lcd_gotoxy(1,2);printf(lcd_putc," QUAY NGHICH ");if (ct==2)

{enable_interrupts(int_timer0);set_timer1(-235);}

enable_interrupts(int_timer1);enable_interrupts(global);set_timer1(-62500);set_pwm2_duty(duty);

d=2;

}


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if (sttphim==12)//stop{

disable_interrupts(int_timer0);set_timer0(0);

disable_interrupts(int_timer1);set_pwm1_duty(0);

set_pwm2_duty(0);lcd_gotoxy(1,2);printf(lcd_putc," ");lcd_gotoxy(1,2);

printf(lcd_putc," STOP ");duty=0;

d=0;}if (sttphim==14){

clear();c=0;

lcd_gotoxy(1,1);printf(lcd_putc," ");lcd_gotoxy(1,2);printf(lcd_putc," ");

lcd_gotoxy(1,1);printf(lcd_putc,"CHON CHE DO :_ ");

}}}}}

void pwm()

{if ((luu>s_vong)&& duty1000)

duty=duty+50;else if (error>100)

duty=duty+20;

else if (error>30){duty=duty+5;}else if (error>20)

duty=duty+1.5;else if (error>10)

duty=duty+(0.05*error);else {duty=duty+(0.025*error);}}if (luu0))

{error=s_vong-luu;

if (error>=10)


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duty=duty-(0.05*error);else (duty=duty-(0.02*error));

}if(luu==s_vong)

duty=duty;if((duty>=250)&&(luu>s_vong))

{ lcd_gotoxy(1,1);printf(lcd_putc," ");lcd_gotoxy(1,1);printf(lcd_putc," TD_tt=MAX ");}

if (d==0){set_pwm1_duty(0);

set_pwm2_duty(0);}else if (d==1){set_pwm1_duty(duty);set_pwm2_duty(0);}

else{set_pwm1_duty(0);

set_pwm2_duty(duty);}}//========chuong trinh con nhap toc do=======void ghi_tocdo()

{if(i>=0&&i

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lcd_gotoxy(1,1);printf(lcd_putc,"0

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lcd_gotoxy(1,2);printf(lcd_putc,"TG_dat=_");

}//=======chuong trinh con luu toc do vao epprom======

void read_rom(){

k=read_eeprom(4);for (j=0;j

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