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Bo co thc tp tt nghip

Li gii thiu

Vi iu khin l 1 lnh vc kh l th i vi chuyn ngnh in t-Vin thng.Cng vi s pht trin ca ngnh in t th nhiu h vi iu khin ln lt c cc

hng sn xut chip cho ra i nh: Z80 ca Zilog, AT89 ca Atmel, PIC ca Microchip,AVR ca Atmel...H vi iu khinAVR ca Atmel Corp l 1 bc pht trin trn nn ca Vi iu

khin AT89 kh quen thuc. Nu nh AT89 l vi iu khin c CPU CISC th AVRl RISC, vi kin trc Harvard do vy tc s nhanh hn (tc ti a l 16 triulnh/giy). Ngoi ra AVR cng tch hp sn ngay trong chip mch ADC, PWM,....cngnh h tr cc chun giao tip thng dng nh UART/USART, I2C, 2-wires,... nn victhit k v thc hin phn cng cho nhng ng dng rt thun tin, nhanh chng, nhgn.

V ngn ng lp trnh cho AVR th c rt nhiu: assembly, C, Basic, Pascal... Trong

nhng phn mm min ph do chnh Atmel cung cp, hay nhng hng khc l rtnhiu: avrasm, winasm (hp ng), CodeVisionAVR, Win-GCC(ngn ng C),BASCOM (ngn ng Basic).v.v.

Hn th vic m phng, debug cng c h tr cc t A-Z, nhiu phn mmsimulator, emulator nh: AVRStudio (min ph ca Atmel), Proteus, ...

Trong phm vi cun bo co ny ch nghin cu v vi iu khin ATmega16, phnmm m phng mch in Proteus 7.0 v s dng Proteus thit k my pht tri ph.

Trong qu trnh vit bo co, ngi vit c tham kho datasheet ca ATmega16 ttrang web ca hng Atmel (www.atmel.com) v mt s ti liu khc.

L Hi ng CTM5-k50-HUT

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Mc lc


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Bo co thc tp tt nghip Chng 1. Gii thiu chung

Phn 1. Vi iu khin ATmega16

Chng 1. Gii thiu chung

ATmega16 l vi iu khin 8 bit da trn kin trc RISC. Vi kh nng thc hinmi lnh trong vng mt chu k xung clock, ATmega16 c th t c tc 1MIPStrn mi MHz (1 triu lnh/s/MHz).

Di y l s khi ca ATmega16


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Bo co thc tp tt nghip Chng 1. Gii thiu chung

Hnh 1.1. S cu trc ATmega16ATmega16 c cc c im sau: 16KB b nh Flash vi kh nng c trong khi ghi,

512 byte b nh EEPROM, 1KB b nh SRAM, 32 thanh ghi chc nng chung, 32ng vo ra chung, 3 b nh thi/b m, ngt ni v ngt ngoi, USART, giao tipni tip 2 dy, 8 knh ADC 10 bit,....

ATmega 16 h tr y cc chng trnh v cng c pht trin h thng nh: trnhdch C, macro assemblers, chng trnh m phng/sa li, kit th nghim,...


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Chng 2. Cu trc nhn AVR


CPU ca AVR c chc nng bo m s hot ng chnh xc ca cc chng trnh.Do n phi c kh nng truy cp b nh, thc hin cc qu trnh tnh ton, iu

khin cc thit b ngoi vi v qun l ngt.

2.1.Cu trc tng qut

Hnh 2.1. S cu trc CPU ca ATmega16

AVR s dng cu trc Harvard, tch ring b nh v cc bus cho chng trnh v dliu. Cc lnh c thc hin ch trong mt chu k xung clock. B nh chng trnhc lu trong b nh Flash.

2.2. ALUALU lm vic trc tip vi cc thanh ghi chc nng chung. Cc php ton c

thc hin trong mt chu k xung clock. Hot ng ca ALU c chia lm 3 loi: is, logic v theo bit.

2.3. Thanh ghi trng thi

y l thanh ghi trng thi c 8 bit lu tr trng thi ca ALU sau cc php tnh shc v logic.


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Hnh 2.2. Thanh ghi trng thi SREG

C: Carry Flag ;c nh (Nu php ton c nh c s c thit lp)Z: Zero Flag ;C zero (Nu kt qu php ton bng 0)

N: Negative Flag (Nu kt qu ca php ton l m)V: Twos complement overflow indicator (C ny c thit lp khi trn s b 2)V, For signed tests (S=N XOR V) S: NH: Half Carry Flag (c s dng trong mt s ton hng s c ch r sau)T: Transfer bit used by BLD and BST instructions(c s dng lm ni chung

gian trong cc lnh BLD,BST).I: Global Interrupt Enable/Disable Flag (y l bit cho php ton cc ngt. Nu bit

ny trng thi logic 0 th khng c mt ngt no c phc v.)

2.4. Cc thanh ghi chc nng chung

Hnh 2.3. Thanh ghi chc nng chung

2.5. Con tr ngn xp (SP)L mt thanh ghi 16 bit nhng cng c th c xem nh hai thanh ghi chc nngc bit 8 bit. C a ch trong cc thanh ghi chc nng c bit l $3E (Trong b nhRAM l $5E). C nhim v tr ti vng nh trong RAM cha ngn xp.


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Hnh 2.4. Thanh ghi con tr ngn xp

Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vongn xp trong khi con tr ngn xp gim hai v tr. V con tr ngn xp s gim 1 khithc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 vkhi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh vy con tr ngnxp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chngtrnh con c gi hoc cc ngt c cho php phc v. V gi tr ngn xp t nhtcng phi ln hn hoc bng 60H (0x60) v 5FH tr li l vng cc thanh ghi.

2.6. Qun l ngtNgt l mt c ch cho php thit b ngoi vi bo cho CPU bit v tnh trng sn

xng cho i d liu ca mnh.V d:Khi b truyn nhn UART nhn c mt byte ns bo cho CPU bit thng qua c RXC,hc khi n truyn c mt byte th c TX

c thit lpKhi c tn hiu bo ngt CPU s tm dng cng vic ng thc hin li v lu v trang thc hin chng trnh (con tr PC) vo ngn xp sau tr ti vector phuc vngt v thc hin chng trnh phc v ngt ch ti khi gp lnh RETI (return frominterrup) th CPU li ly PC t ngn xp ra v tip tc thc hin chng trnh m trckhi c ngt n ang thc hin. Trong trng hp m c nhiu ngt yu cu cng mtlc th CPU s lu cc c bo ngt li v thc hin ln lt cc ngt theo mc utin .Trong khi ang thc hin ngt m xut hin ngt mi th s xy ra hai trng hp.Trng hp ngt ny c mc u tin cao hn th n s c phc v. Cn n m cmc u tin thp hn th n s b b qua.

B nh ngn xp l vng bt k trong SRAM t a ch 0x60 tr ln. truy nhpvo SRAM thng thng th ta dng con tr X,Y,Z v truy nhp vo SRAM theokiu ngn xp th ta dng con tr SP. Con tr ny l mt thanh ghi 16 bit v c truynhp nh hai thanh ghi 8 bit chung c a ch :SPL :0x3D/0x5D(IO/SRAM) vSPH:0x3E/0x5E.

Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vongn xp trong khi con tr ngn xp gim hai v tr.V con tr ngn xp s gim 1 khithc hin lnh push. Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 vkhi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2. Nh vy con tr ngnxp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chng

trnh con c gi hoc cc ngt c cho php phc v. V gi tr ngn xp t nhtcng phi ln hn 60H (0x60) v 5FH tr li l vng cc thanh ghi.

V d:char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */CLI();

EECR |= (1

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EECR |= (1

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Chng 3. Cu trc b nh

Chng 3. Cu trc b nh

AVR c 2 khng gian b nh chnh l b nh d liu vo b nh chng trnh.

Ngoi ra ATmega16 cn c thm b nh EEPROM lu tr d liu.

3.1. B nh chng trnh (B nh Flash)B nh Flash 16KB ca ATmega16 dng lu tr chng trnh. Do cc lnh ca

AVR c di 16 hoc 32 bit nn b nh Flash c sp xp theo kiu 8KX16. B nhFlash c chia lm 2 phn, phn dnh cho chng trnh boot v phn dnh chochng trnh ng dng.

Hnh 3.1. Bn b nh chng trnh

3.2. B nh d liu SRAM1120 nh ca b nh d liu nh a ch cho file thanh ghi, b nh I/O v b nh

d liu SRAM ni. Trong 96 nh u tin nh a ch cho file thanh ghi v b nhI/O, v 1024 nh tip theo nh a ch cho b nh SRAM ni.


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Chng 3. Cu trc b nh

Hnh 3.2. Bn b nh d liu SRAM

3.3. B nh d liu EEPROMATmega16 cha b nh d liu EEPROM dung lng 512 byte, v c sp xp

theo tng byte, cho php cc thao tc c/ghi tng byte mt.


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Bo co thc tp tt nghip Chng 4.Cc cng vo ra

Chng 4. Cc cng vo ra (I/O)

Vi iu khinATmega16c 32 ng vo ra chia lm bn nhm 8 bit mt. Cc

ng vo ra ny c rt nhiu tnh nng v c th lp trnh c. y ta s xt chngl cc cng vo ra s. Nu xt trn mt ny th cc cng vo ra ny l cng vo ra haichiu c th nh hng theo tng bit. V cha c in tr pull-up (c th lp trnhc). Mc d mi port c cc c im ring nhng khi xt chng l cc cng vo ras th dng nh iu khin vo ra d liu th hon ton nh nhau. Chng ta c thanhghi v mt a ch cng i vi mi cng, l : thanh ghi d liu cng (PORTA,PORTB, PORTC, PORTD), thanh ghi d liu iu khin cng (DDRA, DDRB, DDRC,DDRD) v cui cng l a ch chn vo ca cng (PINA, PINB, PINC, PIND).

4.1. Thanh ghi DDRx

y l thanh ghi 8 bit (ta c th c v ghi cc bit thanh ghi ny) v c tc dngiu khin hng cng PORTx (tc l cng ra hay cng vo). Nu nh mt bit trongthanh ghi ny c set th bit tng ng trn PORTx c nh ngha nh mt cngra. Ngc li nu nh bit khng c set th bit tng ng trn PORTx c nhngha l cng vo.

4.2.Thanh ghi PORTxy cng l thanh ghi 8 bit (cc bit c th c v ghi c) n l thanh ghi d liu

ca cng Px v trong trng hp nu cng c nh ngha l cng ra th khi ta ghi mtbit ln thanh ghi ny th chn tng ng trn port cng c cng mc logic. Trong

trng hp m cng c nh ngha l cng vo th thanh ghi ny li mang d liuiu khin cng. C th nu bit no ca thanh ghi ny c set (a ln mc 1) thin tr ko ln (pull-up) ca chn tng ng ca port s c kch hot. Ngc lin s trng thi hi-Z. Thanh ghi ny sau khi khi ng Vi iu khins c gi tr l0x00.

4.3. Thanh ghi PINxy l thanh ghi 8 bit cha d liu vo ca PORTx (trong trng hp PORTx c

thit lp l cng vo) v n ch c th c m khng th ghi vo c.

Tm li:1. c d liu t ngoi th ta phi thc hin cc bc sau: a d liu ra thanh ghi iu khin DDRxn t cho PORTx (hoc bit n trong

port) l u vo (xa thanh ghi DDRx hoc bit). Sau kch hot in tr pull-up bng cch set thanh ghi PORTx ( bit). Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit).

2. a d liu t vi iu khin ra cc cng cng c cc bc hon ton tng t.Ban u ta cng phi nh ngha l cng ra bng cch set bit tng ng ca cng.v sau l ghi d liu ra bit tng ng ca thanh ghi PORTx.

V d:unsigned char i;


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.../* Define pull-ups and set outputs high *//* Define directions for port pins */PORTB = (1

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Chng 5. B nh thi

Chng 5.B nh thi

B nh thi (timer/counter0) l mt module nh thi/m 8 bit, c cc c im

sau: B m mt knh Xa b nh thi khi trong mode so snh (t ng np) PWM To tn s B m s kin ngoi B chia tn 10 bit Ngun ngt trn b m v so snh

S cu trc ca b nh thi:

Hnh 5.1. S cu trc b nh thi

5.1. Cc thanh ghiTCNT0 v OCR0 l cc thanh ghi 8 bit. Cc tn hiu yu cu ngt u nm trong

thanh ghi TIFR. Cc ngt c th c che bi thanh ghi TIMSK.B nh thi c th s dng xung clock ni thng qua b chia hoc xung clock

ngoi trn chn T0. Khi chn xung clock iu khin vic b nh thi/b m s dngngun xung no tng gi tr ca n. Ng ra ca khi chn xung clock c xem lxung clock ca b nh thi (clkT0).

Thanh ghi OCR0 lun c so snh vi gi tr ca b nh thi/b m. Kt qu sosnh c th c s dng to ra PWM hoc bin i tn s ng ra ti chn OC0.

5.2. n v m


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Bo co thc tp tt nghip Chng 5.B nh thi

Phn chnh ca b nh thi 8 bit l mt n v m song hng c th lp trnhc. Cu trc ca n nh hnh di y:

Hnh 5.2. n v m

count: tng hay gim TCNT0 1direction: la chn gia m ln v m xungclear: xa thanh ghi TCNT0clkT0: xung clock ca b nh thiTOP: bo hiu b nh thi tng n gi tr ln nhtBOTTOM: bo hiu b nh thi gim n gi tr nh nht (0)

5.3. n v so snh ng ra

Hnh 5.3. S n v so snh ng ra

B so snh 8 bit lin tc so snh gi tr TCNT0 vi gi tr trong thanh ghi so snhng ra (OCR0). Khi gi tr TCNT0 bng vi OCR0, b so snh s to mt bo hiu.Bo hiu ny s t gi tr c so snh ng ra (OCF0) ln 1 vo chu k xung clock tiptheo. Nu c kch hot (OCIE0=1), c OCF0 s to ra mt ngt so snh ng ra v s

t ng c xa khi ngt c thc thi. C OCF0 cng c th c xa bng phnmm.


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5.4. M t cc thanh ghi5.4.1. Thanh ghi iu khin b nh thi/b m TCCR0

Hnh 5.4. Thanh ghi iu khin b nh thi

5.4.1.1. Bit 7-FOC0: So snh ng ra bt buc

Chng 5.B nh thi

Bit ny ch tch cc khi bit WGM00 ch nh ch lm vic khng c PWM. Khit bit ny ln 1, mt bo hiu so snh bt buc xut hin ti n v to dng sng.5.4.1.2. Bit 6, 3-WGM01:0: Ch to dng sng

Cc bit ny iu khin m th t ca b m, ngun cho gi tr ln nht ca bm (TOP) v kiu to dng sng s c s dng.5.4.1.3. Bit 5:4-COM01:0: Ch bo hiu so snh ng ra

Cc bit ny iu khin hot ng ca chn OC0. Nu mt hoc c hai bit COM01:0c t ln 1, ng ra OC0 s hot ng.5.4.1.4. Bit 2:0: CS02:0: Chn xung ng h

Ba bit ny dng la chn ngun xung cho b nh thi/b m.

5.4.2. Thanh ghi b nh thi/b m

Hnh 5.5. Thanh ghi b nh thiThanh ghi b nh thi/b m cho php truy cp trc tip (c c v ghi) vo b

m 8 bit.

5.4.3. Thanh ghi so snh ng ra-OCR0


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Hnh 5.6. Thanh ghi so snh ng ra

Chng 5.B nh thi

Thanh ghi ny cha mt gi tr 8 bit v lin tc c so snh vi gi tr ca b m.

5.4.4. Thanh ghi mt n ngt

Hnh 5.7. Thanh ghi mt n ngt TIMSK5.4.4.1. Bit 1-OCIE0: Cho php ngt bo hiu so snh5.4.4.2. Bit 0-TOIE0: Cho php ngt trn b m

5.4.5. Thanh ghi c ngt b nh thi

5.4.5.1. Bit 1-OCF0: C so snh ng ra 05.4.5.2. Bit 0-TOV0: C trn b m

Bit TOV0 c t ln 1 khi b m b trn v c xa bi phn cng khi vectorngt tng ng c thc hin. Bit ny cng c th c xa bng phn mm.


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Chng 6. USART

Chng 6. USART

B truyn nhn ni tip ng b v bt ng b l mt thit truyn thng ni tip c

cc chc nng chnh nh sau: Hot ng song cng (cc thanh ghi truyn v nhn ni tip c lp vi nhau). Hot ng ng b hoc bt ng b B to tc baud c chnh xc cao H tr khung truyn ni tip vi 5, 6, 7, 8, hoc 9 bit d liu v 1 hoc 2 bit stop Kim tra chn l Pht hin trn d liu Pht hin li khung Lc nhiu, bao gm pht hin bit start li v b lc thng thp s

Ngt khi kt thc truyn, thanh ghi truyn ht d liu v kt thc nhn Ch truyn thng a vi x l Ch truyn ng b tc caoS khi ca b USART nh sau:

Hnh 6.1. S khi b USART

USART bao gm 3 phn chnh: b to xung clock, b truyn v b nhn. Cc thanh

ghi iu khin c s dng chung gia cc phn ny.


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Chng 6. USART

B to xung clock to ra xung ng h cn bn cho b truyn v b nhn. USARTh tr 4 ch hot ng xung clock: bt ng b, bt ng b tc cao, truyn ng

b master v truyn ng b slave. S khi ca b to xung clock nh sau:

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Hnh 6.2. n v to xung clock.

txclk: xung ng h b truynrxclk: xung ng h b nhnxcki: tn hiu vo t chn XCK, s dng cho hot ng truyn ng b masterxcko: tn hiu xung clock ng ra ti chn XCK, s dng cho hot ng truyn ng

b slavefosc: tn s t chn XTAL

6.2. nh dng khung truynUSART chp nhn tt c 30 t hp ca cc nh dng khung truyn sau y: 1 bit start 5, 6, 7, 8, hoc 9 bit d liu C hoc khng c bit chn l 1 hoc 2 bit stop

Mt khung truyn bt u vi mt bit start, theo sau l bit c trng s thp nht

(LSB) ca d liu (c th ln ti 9 bit), kt thc bng bit c trng s ln nht (MSB) vbit stop.

Hnh 6.3. nh dng khung truyn

St: bit start (mc thp)(n): bit d liu (0 n 8)


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c cao)IDLE: khng c d liu truyn (mc cao trong sut thi gian idle)

6.3. Khi to USART

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Chng 6. USARTQu trnh khi to USART bao gm vic thit lp tc baud, thit lp nh dng

khung v kch hot b truyn v b nhn.V d di y thit lp hot ng truyn bt ng b s dng polling (khng dng

ngt) v nh dng khung truyn l c nh. Tc baud l mt tham s ca hm.

void USART_Init( unsigned int baud )

{/* Set baud rate */UBRRH = (unsigned char)(baud>>8);UBRRL = (unsigned char)baud;

/* Enable receiver and transmitter */UCSRB = (1

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/* Wait for empty transmit buffer */while ( !( UCSRA & (1

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Chng 6. USARTB nhn USART c kch hot bng cch t bit RXEN trong thanh ghi UCRSB

ln 1. Khi b nhn c kch hot, chn RxD hot ng nh ng vo ca b nhn nitip. Tc baud, ch hot ng v nh dng khung truyn phi c thit lptrc khi thc hin truyn d liu.

6.5.1. Nhn khung vi 5 n 8 bit d liu

B nhn bt u nhn d liu khi n pht hin mt bit start hp l. Mi bit theo saubit start s c ly mu ti tc baud hoc tc ng h XCK, v c dch votrong thanh ghi dch ca b nhn cho n khi pht hin mt bit stop u tin. Ni dungca thanh ghi dch sau c a vo b m. B m ca b nhn c th c c

bng cch c UDR.V d sau y l mt hm nhn USART da trn vic kim tra c kt thc truyn

(RXC).

unsigned char USART_Receive( void ){

/* Wait for data to be received */while ( !(UCSRA & (1

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resl;/* Wait for data to be received */while ( !(UCSRA & (1

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Chng 6.USART

Bo co thc tp ttnghip

Chng 7. B bin i

A/D

Chng 7. B bin i A/D

Vi iu khinATmega16 c mt b bin i ADC tch hp trong chip vi cc

cim: phn gii 10 bit Sai s tuyn tnh: 0.5LSB chnh xc +/-2LSB Thi gian chuyn i:65-260s 8 Knh u vo c th c la chn C hai ch chuyn i free running v single conversion C ngun bo ngt khi hon thnh chuyn i Loi b nhiu trong ch ng

Hnh 7.1. S b bin i A/D

Tm u vo ca ADC l tm chn ca PORTA v chng c chn thng

qua mtMUX.

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Bo co thc tp tt nghip Chng 7. B bin i A/D

iu khin hot ng vo ra d liu ca ADC v CPU chng ta c 3 thanhghi:

ADMUX l thanh ghi iu khin la chn knh u vo cho ADC, ADCSRA l thanh

ghi iu khin v thanh ghi trng thi ca ADC, ADCH v ADCL l 2 thanh ghidliu.

7.1. ADMUX: Multiplexer select registery l thanh ghi iu khin 8 bit.

Hnh 7.2. Thanh ghi ADMUX

Vi 4 bit c nh ngha l MUX3, MUX2, MUX1,v MUX0, ng vi cc

t hplogic ta c th chn knh u vo. C th:

Cc bit REFS1 v REFS0 dng chn gi tr in p tham kho cho ADC,

nhsau:

Ch : Nu nh ta thay i knh trong thi im m ADC ang chuyn i thkhi qutrnh chuyn i hon thnh th knh vo mi c thay i.7.2. ADCSR-ADC control and status register

y l thanh ghi iu khin v lu trng thi ca ADC.

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Hnh 7.3. Thanh ghi iu khin v trng thi ADC

7.2.1. Bit 7-ADEN:ADC enabley l bit iu khin hot ng ca ADC.Khi bit ny c set 1 th ADC cth

hot ng v ngc li.Nu nh ta ngng hot ng ca ADC trong khi n angchuyn i th n s kt thc qu trnh chuyn i.Mc d cha chuyn ixong.

7.2.2. Bit 6-ADSC: ADC start conversionTrong ch chuyn i n th bit ny phi c set ln 1 bt u chuyn

i.Trong ch chuyn i t do th bit ny cn c set ln 1 bt u ln chuyni u tin.Bit ny c gi st trong qu trnh chuyn i v c xa khi mchuyn i xong.

7.2.3. Bit 5-ADATE :ADC Auto Trigger enableKhi bit ny c set th ADC s bt u chuyn i mi khi c mt ngunkch hot

xut hin. Vic la chn ngun kch hot c thc hin bng cch set cc bit trong

thanh ghi SFIOR.

7.2.4. Bit 4-ADIF: ADC interrupt FlagBit ny c set ln 1 bi phn cng khi qu trnh chuyn i hon thnhv

thanh ghi d liu c cp nht. Bit ny c xa bng phn cng nu nhngt nyc php v c phc v. Hoc n c th c xa bng cch ghi gi tr logic0vo c ny. C th khi ngt b cm ta c th s dng cc lnh sbi v cbi tc dngln bit ny.

7.2.5. Bit 3-ADIE:ACD interrupt EnableNu bit ny set 1 v ngt ton cc c cho php th ngt ny c phpphc v

(khi chuyn i xong d liu) v nu b xa th ngc li.

7.2.6. Bit 2.1.0-ADPS2ADPS0: Bit la chn xung nhp(Tc )Ngun xung c ly t ngun xung ca Vi iu khin(XTAL) v c chiatn

thng qua b chia tn.Cc bit ADPS c nhim v chn s chia cho b chia tn theo bng sau:

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L Hi ng CTM5-

k50-HUT


7.3. Thanh ghi d liu ACDH v ADCL

Chng 7. B bin i A/D

Thanh ghi ny cha d liu chuyn i t tng t sang s, c sp xp nhhnhdi y.

Hnh 7.4. Thanh ghi d liu ADC

7.4. Nguyn tc hot ng v lp trnh iu khinADC c nhim v chuyn i tn hiu in p tng t thnh tn hiu s c phn

gii 10 bit.Vi gi tr nh nht ca in p t chn AGND v gi tr cc ica inp tng t c mc vo chn AREF. Tm knh tng t u vo c chnlathng qua ADMUX v ADMUX ny c iu khin bi thanh ghi ADMUX.

ADC ny c th hot ng c hai ch . l chuyn i n: chchuyn imt ln khi c lnh chuyn i v ch t chuyn i (Free running mode) y l ch m ADC t ng chuyn i khi c hot ng v cng vic chuyn i ctnhtun hon (ch cn khi ng mt ln).

ADC c php hot ng nh thit lp bit ADEN. Qu trnh chuyn ic bt

u bng vic ghi vo bit ADSC mc logic 1 v trong sut qu trnh chuyn ibit ny

lun c gi mc cao. Khi qu trnh chuyn i hon thnh th bit ny cxabng phn cng v c AIDF c bt ln.

D liu sau khi chuyn i c a ra thanh ghi d liu ADCL v ADCH,nhng

ch khi c d liu t hai thanh ghi ny th c ADCL trc ri mi c

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ADCH.

N

ucADCHtrcthdliuc

pn

htcthg

hil

n ADCL (Vi iu khin ngh rng c xong d liu). iu khin vo ra d liu vi ADC, cc bc thc hin nh sau:Bc 1: nh ngha cc cng vo cho tn hiu tng tXa bit tng ng vi chn trong thanh ghi DDRA. Sau loi b in trtreo

bng cch xa bit tng ng thanh ghi PORTA.


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Bc 2: Chn knh tng t vo (chn chn vo cho ADC) thng qua thanh ghiADMUX (c th thay i trong qu trnh hot ng).Bc 3: Thit lp cc thng s cho ADCTc chuyn i thng qua xung nhip chuyn i.Ch chuyn i : n hoc t ng.S dng ngt hoc khng.Bc 4: Bt u chuyn i v c d liu.

V d: (bin i ADC, ng vo analog PA2, hin th d liu trn led PORTB)#include #include

//ADC interrupt functionISR(ADC_vect){PORTB=ADCH;

}

int main(void){outp(0xFF, DDRB); //PORTB is outputoutp(0xFF, PORTB); //all PINs high (LEDs off)outp(0x22, ADMUX); //PINA2 as analog input (MUX0..2)

//left adjusted (ADLAR=1)//AREF as reference voltage (connected to VCC 5V) (REFS0..1)

outp(0xA5, ADCSR); //ADC enable, ADC auto trigger, ADC prescaler= 32outp((inp(SFIOR)&0x1F),SFIOR); //Trigger source = Free Running Modesbi(ADCSR,6);for(;;){

}return 1;

}


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Bo co thc tp tt nghip Phn 2. Phn mm m phng mch in Proteus

Phn 2. Phn mm m phng mch in Proteus 7.0


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1. Gii thiu v Proteus

Phn mm Proteus VSM c vit bi cng ty Labcenter Electronics . Proteus c s dng kh rng ri trn 35 quc gia. Proteus t khng nh th mnh ca nv m phng cc mch nguyn l st vi thc t, trn 12 nm cng ngy n cng chon thin v pht trin mnh. Protesu cung cp cho ngi s dng hu nh ton b cclinh kin in t ngi dng c th to ra c cc mch nguyn l v sau cng lchy th v so snh vi kt qu thc t. Chnh v Proteus c th to v chy c ccmch n gin cng nh cc mch phc tp nn c th dng n trong ging dy, trongcc phng th nhim in t cng nh trong thc hnh vi x l

Phn mm Proteus chy trong mi trng Window 32 bit, yu cu ca n v phncng cng n gin, CPU 300MHz tr ln.

2. Cc u im- D dng to ra mt s nguyn l n gin t cc mch in n gin n ccmch c b lp trnh vi x l .- D dng chnh sa cc c tnh ca linh kin trn s nguyn l : chnh sa s

bc ca ng c bc, chnh sa ngun nui cho mch ,thay i tn s hot ngc bn ca vi x l- Cng c h tr kim tra li thit k trn s nguyn l . Xem v lu li phn bo li.- Chy m phng v phn tch cc tnh cht ca mch in c bn. Cng c h tr

cho vic chy v m phng rt mnh v chnh xc. Cc cng c v th h trmnh cho vic phn tch tn s, sng, m thanh .. khng nhng th phn mm cnc thm cc my phn tch t n gin nh : ng h o Vn, Ampe, n cc myo dao ng ,my to sng dao ng - Ngoi ra Proteus cn cung cp cho ngi s dng cc cng c mnh m cc phnmm khc hu nh khng c. Chng hn th vin LED vi cc loi mu sc khc nhauk c led 7 on. Nhng phn hin th mnh nht m Proteus cung cp l LCD, n cth m phng cho rt nhiu LCD t n gin n phc tp.- Mt ci u im na ca Proteus l c th m phng cng c pht v thu tn hiut cc mch giao tip vi my tnh qua cng c RS232. Trong ngi s dung c th

iu khin c qu trnh truyn pht, tc Baud gip cho ngi lp trnh c thm phng cc mt truyn pht tn hiu .- Mt im mnh khc ca Proteus l cung cp cho ngi s dng cng c bin dchcho cc h vi x l nh MSC51, AVR, HC11 qua to ra cc tp tin HEX dng np cho vi x l v tp tin DSI dng xem v chy kim tra tng bc trong chngtrnh m phng.- i vi cc mch vi x l Proteus khng nhng cung cp hnh nh thc t ca cclinh kin xut m cn cung cp cho ngi lp trnh rt nhiu cc ca s thng bo ccni dung ca b nh, con tr, thanh ghi, - Proteus c mt th vin kh ln vi hn 6000 linh kin cc loi v cng ngy cng

c b sung. Ngoi ra cn c keypad (ma trn phm to n gin cho ngi thit kkhi cn thao tc trn cc ma trn phm ).


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3. Kh nng ng dng


- Kh nng ng dng chnh ca Proteus l m phng, phn tch cc kt qu t cc

mch nguyn l. Proteus gip cho ngi s dng c th thy trc mch thit kchy ng hay sai trc khi thit k trn bo mch.- Cc cng c phc v cho vic phn tch mch c chnh xc kh cao nh o vnhay ampe, my o dao ng.- Kh nng p dng chng trnh Proteus vo trong ging dy l rt tt cho cc thycng nh cho sinh vin hc tp k thut in t v hu nh Proteus cung cp gn nhy t c bn n phc tp cho ngi hc in t v vi x l.- i vi cc sinh vin th Proteus nu m c s dng rng di th n gn nh l thydy cho chnh h nh. N gip cho cc sinh vin t hc, t nhin cu v thit k thcc phn hc v chy xem kt qu v rt ra cc bi hc tt. iu c bn nht l tit

kim tin cho sinh vin khng c iu kin m li ham hc, ham nghin cu.

4. Kh nng phn tch- Phn tch mt mch n gin.- Phn tch cc mch cc h vi x l.- Phn tch mch qua cc th, cc my o v d :+ Phn tch Analogue+ Phn tch Digital+ Phn tch tn s+ Phn tch m thanh

+ Phn tch truyn pht d liu.Nhiu v cn rt nhiu phng php phn tch t n gin nht n kh nng phntch phc tp m ngoi thc t khi cn phn tch n th cn rt nhiu chi ph cngnh cng c s dng.- Phn tch qu ti, qu p, ti Proteus cung cp cho ngi s dng kh nng

phn tch qu ti gip ngi s dng hnh dung c khi qu ti th nh hng n cclinh kin nh th no m khng phi mt chi ph cng nh an ton tuyt i.- Lu li cc kt qu phn tch .


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Bo co thc tp tt nghip Chng 2. M phng v phn tch mch nguyn l

Chng 2. M phng v phn tch mch nguyn l

Ta s bt u bng vic phn tch cc v d. Xt mch nh hnh di y:


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+5V

U1


RbPN

RV1

10k

9 RESET

13 XTAL1

12 XTAL2

40 PA0/ADC0

39 PA1/ADC1

38 PA2/ADC2

37 PA3/ADC3

36 PA4/ADC4

35 PA5/ADC5

34 PA6/ADC633 PA7/ADC7

1 PB0/XCK/T0

2 PB1/T1

3 PB2/INT2/AIN0

4 PB3/OC0/AIN1

5 PB4/SS

6 PB5/MOSI

7 PB6/MISO

8 PB7/SCK ATMEGA16

PC0/SCL22

PC1/SDA23

PC2/TCK24

PC3/TMS25

PC4/TDO26

PC5/TDI27

PC6/TOSC128

PC7/TOSC229

PD0/RXD14

PD1/TXD15

PD2/INT016

PD3/INT117

PD4/OC1B18

PD5/OC1A19

PD6/ICP20

PD7/OC221

AVCC30

AREF32

+5V

R16100

C22100nF

RbPN

y l mch s dng vi iu khin ATmega16. Ta c th phn tch dng sng ng rabng hai cch: s dng Oscillocope hoc dng th (Graph).

Nu dng Oscillocope th ta thm vo mch nh hnh di y:

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+5V

U1


RbPN

RV1

10k

9 RESET

13 XTAL1

12 XTAL2

40 PA0/ADC0

39 PA1/ADC1

38 PA2/ADC2

37 PA3/ADC3

36 PA4/ADC4

35 PA5/ADC5

34 PA6/ADC6

33 PA7/ADC7

1 PB0/XCK/T02 PB1/T1

3 PB2/INT2/AIN0

4 PB3/OC0/AIN1

5 PB4/SS

6 PB5/MOSI

7 PB6/MISO

8 PB7/SCK ATMEGA16

PC0/SCL22

PC1/SDA23

PC2/TCK24

PC3/TMS25

PC4/TDO26

PC5/TDI27

PC6/TOSC128

PC7/TOSC229

PD0/RXD14

PD1/TXD15

PD2/INT016

PD3/INT117

PD4/OC1B18

PD5/OC1A19

PD6/ICP20

PD7/OC221

AVCC30

AREF32

+5V

R16100

C22100nF

Rb

A

B

C

D

PN

Nhn F12 chy m phng ta c kt qu nh hnh sau:

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Bo co thc tp tt nghip Chng 2. M phng v phn tch mch nguyn l

Nu s dng th, chn Graph mode, chn Digital v v mt th nh sau:

+5V

RV1

10k

U19 RESET

13 XTAL1

12 XTAL2

40 PA0/ADC0

39 PA1/ADC1

38 PA2/ADC2

37 PA3/ADC3

36 PA4/ADC4

35 PA5/ADC5

34 PA6/ADC6

33 PA7/ADC7

1 PB0/XCK/T0

2 PB1/T13 PB2/INT2/AIN0

PC0/SCL22

PC1/SDA23

PC2/TCK24

PC3/TMS25

PC4/TDO26

PC5/TDI27

PC6/TOSC128

PC7/TOSC229

PD0/RXD14

PD1/TXD15

PD2/INT0 16

PD3/INT1 17

PD4/OC1B

18

PD5/OC1A19

PD6/ICP20

PD7/OC221

+5V

R16

Rb

Rb

A

B

C

D

PN

PN

4 PB3/OC0/AIN1

5 PB4/SS

6 PB5/MOSI

7 PB6/MISO

8 PB7/SCK ATMEGA16

AVCC30

AREF32

100

C22100nF

Ko hai k hiu Rb v PN vo th v nhn phm Space bar ta c kt qu nh sau:

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Phn 3. Thit k my pht tri ph

Ta cn thit k s nguyn l my pht tri ph vi cc chc nng bin i A/D,to d liu, to m tri ph v nhn tn hiu to tn hiu tri ph. lm c iu

ta cn mt mch bin i A/D, b nhn v b to m tri ph. Vi mc ch lm ngin mch thit k ta s dng vi iu khin ATmega16 thc hin chc nng bin iA/D, to m tri ph v to d liu ra. S khi ca my pht tri ph nh hnh diy:

To chui PN

Nhn tn hiuTo d liu vo

Bin i A/D

1. Bin i A/D

D liu ra

Mch tin bin i A/D gm mt microphone, mt mch khuch i, cc b lc (lc4kHz). Chc nng bin i A/D c thc hin trong vi iu khin ATmega16.


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R121k

R10

10k

R1310k

3

+5V

U4:A

Out

R1112k

Voice_in C26

1uF

R9

1k

2

R1410k

1

LM324 C244.7nF

M phng bng th ta c kt qu nh sau:

2. Nhn tn hiu

Chc nng nhn tn hiu c thc hin bi IC 4070 v 7404 nh hnh sau:


4

11

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1ESET PC0/SCL22

PC1/SDA23

TAL1 PC2/TCK 24

TAL2 PC3/TMS25

PC4/TDO26

A0/ADC0PC5/TDI27

A1/ADC1PC6/TOSC128

A2/ADC2

PC7/TOSC229

Data_out

Data_out

PN_out

PN_out

U2:A1

2

4070

3 1

U3:A

7404

2U3:A(Y)

A3/ADC3

A4/ADC4PD0/RXD14

A5/ADC5PD1/TXD15

A6/ADC6PD2/INT016

A7/ADC7PD3/INT117

PD4/OC1B18

B0/XCK/T0PD5/OC1A1

B1/T1 PD6/ICP20

Tn hiu sau khi qua mch nhn c dng nh sau:

B2/INT2/AIN0

B3/OC0/AIN1

B4/SSB5/MOSI

21

B6/MISO AVCC30 3. To chui PN v to d liu vo

B7/SCK AREF32Vic to chui PN v d liu vo c thc hin bi vi iu khin ATmega16. Ta s

MEGA16 vit phn mm thc hin chc nng ny. y ta s dng ngn ng C lp trnhcho ATmega16. Di y l lu thut ton:

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Vng lp chnh:

Start

Setup port

Analogmode?

No

Processingdata

Yes

No

StartADC?

YesADC


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Vng lp ADC

Return

ADC

InitalizeADC

Start ADC

Wait for ADCcompletion


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Vng lp to chui PN, x l d liu v gi d liu ra:

Processing

data

Send dataout

Send PN senquenceout

Return

Chng trnh np vo vi iu khin:#include#include#include

//asminline void PN_out(int PN_sequence) //send PN sequence to PC1{for(int j=0;j

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}}

//sending data and PN sequence out to PC0inline void out_to_PC0(int m, int PN_sequence){if(m==1) {PORTC|=_BV(0);

PN_out(PN_sequence);}

else {PORTC&=~_BV(0);PN_out(PN_sequence);

}}

//sending AD result to PC0, transmision frame: 8 bits data, 1 start bit, 1 stop bit//generate PN sequence out to PC1//asminline void data_processing(uint8_t data_in){out_to_PC0(0,0x35);for(int i=0;i

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ADCSRA|=(1

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Cui cng ta c s nguyn l ca my pht tri ph nh sau:

+5V

R151k

SW_CODE

SW-SPST

C1

22pF

C2

22pF

R10

X1CRYSTAL

START_ADC

D_IN

+5V

D0D1

D2

U19 RESET

13 XTAL1

12 XTAL2

4 0 P A0/ AD C0

39 P A1 /AD C1

3 8 P A2 /AD C2

37 P A3 /AD C3

36 P A4 /AD C4

3 5 P A5/ AD C5

34 P A6 /AD C6

33 P A7 /AD C7

1 P B0 /XCK /T 0

2 PB1/T1

3 PB2/INT2/AIN0

PC0/SCL22

PC1/SDA23

PC2/TCK24

PC3/TMS25

PC4/TDO26

PC5/TDI 27

PC6/TOSC1 28

PC7/TOSC2 29

PD0/RXD 14

PD1/TXD 15

PD2/INT0 16

PD3/INT1 17

PD4/OC1B 18

PD5/OC1A 19

PD6/ICP20

PD7/OC2 21

D ata _out P N_ou t

U2:AData_out 1

2PN_out

4070

ToRX

ToTX

+5V

R16

3

U3:A1 2

7404

+5V

R8

U3:A(Y)

R12

10k

R13

+5V Out

R11

D3D4D5D6D7

4 P B3/OC0/AIN1

5 PB4/SS

6 PB5/MOSI

7 PB6/MISO

8 PB7/SCK ATMEGA16

AVCC30

AREF32

100

C22100nF

D0

R1R2R3R4R5R6R710k10k10k10k10k10k10k10k

Voice_in

1k

C26

1uF

R9

1k

10k

3

2

U4:A

1

12k D[0..7]

D[0..7]

D1D2D3D4D5D6D7

R1410k

LM324C244.7nF

DSW1DIPSW_8

Mch ny tuy m phng tt nhng vn cn ang trong thi gian th nghim. Vphn mm iu khin vn cn phi ti u bng cch nhng ngn ng assembly vo thc hin nhng tc v cn s chnh xc v thi gian. M iu ny thc s quan trng,quyt nh n nh v chnh xc ca mch.

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ON

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Do an At-Mega-16

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