DM74LS164 8-Bit Serial In/Parallel Out Shift...
7
Computer Science 237 Lab 6 Due: High noon next Tuesday This week I would like you to design and build a simple 8-bit random number generator using a linear feedback shift register . We review pertinent details, here, for implementing this interesting device in logic. In lab we will learn how to use the power supplies, breadboards, and TTL chips to build our device in hardware. Our implementation will make use of a logical device, the serial shift register : CLK Q3 Q2 Q1 Q0 SI Q7 Q6 Q5 Q4 This device contains 8 bits of memory that are used to remember the most recent sequence of values that have appeared on the pin SI (‘shift in’). Each time the clock (CLK) line rises from 0 to 1, the register moves all bits to the left (the value at Q0 moves to Q1, etc.), and the value at SI appears in the register at location Q0. The value once stored in the high bit, Q7, is shifted out and lost. As the clock cycles 8 times a byte of data read serially appears as the output of the register. Serial shift registers are a fundamental building block of all devices that communicate by receiving bits one at a time over a wire, through the air, or from a bit-serial store, like a hard disk. In our actual circuit we will use a TTL chip, the 74-164. It has the following pin configuration, or pinout : As with all integrated circuits, this chip is powered by two pins, Vcc and GND. The pins A and B are typically wired together 1 and provide ‘shift in’ bits: every bit that appears on these pins is captured when the clock goes high. Next, the outputs are labeled QA through QH. The standard for labeling pins in 7400 series of devices is, at best, inconsistent; in general you need to scour the TTL product description pages to learn about these details. Here, the QA pin is the least significant bit in the stored byte. Be careful: some devices do not have Vcc and GND in the corners or take ordered bits out of order. Reading the device documentation will save you time and reduce your sorrow. The CLOCK line works exactly as CLK described above: the A/B lines are strobed into the device on the rising edge of this signal. This edge-based triggering is always indicated by a little triangle at the entrance of the signal. If the TTL picture does not have that triangle, the action happens as long as the clock is high ; it is level-triggered . Finally, an appropriate signal on the CLEAR will clear the internal memory to zeros. Because there is an ‘inverter bubble’ on the pin, we say the signal is active low : the clear will happen as long as the CLEAR pin is grounded. 2 I leave it to you to determine if the register starts up in a cleared state. The 8-bit Linear Feedback Shift Register. Ideally, our 8-bit number generator would present an orbit of 256 random values 3 before any value is repeated. The linear feedback approach takes several bits from the serial shift 1 This is strange. You might read the device documentation to discover other ways the designers imagined this device would be used. 2 If you see both a inverter bubble and a edge-trigger triangle, the action occurs during the 1 to 0 or falling edge transition. 3 These values are not random, of course (the circuit is deterministic, after all), but for many purposes they sufficiently unpredictable.
Transcript of DM74LS164 8-Bit Serial In/Parallel Out Shift...
Computer Science 237Lab 6Due: High noon next Tuesday
This week I would like you to design and build a simple 8-bit random number generator using a linear feedback
shift register . We review pertinent details, here, for implementing this interesting device in logic. In lab we will learnhow to use the power supplies, breadboards, and TTL chips to build our device in hardware.
Our implementation will make use of a logical device, the serial shift register :A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
5 5
CLK
Q3 Q2 Q1 Q0SI
Q7 Q6 Q5 Q4
This device contains 8 bits of memory that are used to remember the most recent sequence of values that haveappeared on the pin SI (‘shift in’). Each time the clock (CLK) line rises from 0 to 1, the register moves all bits to theleft (the value at Q0 moves to Q1, etc.), and the value at SI appears in the register at location Q0. The value oncestored in the high bit, Q7, is shifted out and lost. As the clock cycles 8 times a byte of data read serially appears asthe output of the register. Serial shift registers are a fundamental building block of all devices that communicate byreceiving bits one at a time over a wire, through the air, or from a bit-serial store, like a hard disk.
In our actual circuit we will use a TTL chip, the 74-164. It has the following pin configuration, or pinout :
DM74LS1648-Bit Serial In/Parallel Out Shift RegisterGeneral DescriptionThese 8-bit shift registers feature gated serial inputs and anasynchronous clear. A low logic level at either input inhibitsentry of the new data, and resets the first flip-flop to the lowlevel at the next clock pulse, thus providing complete controlover incoming data. A high logic level on either input enablesthe other input, which will then determine the state of the firstflip-flop. Data at the serial inputs may be changed while theclock is high or low, but only information meeting the setupand hold time requirements will be entered. Clocking occurs
on the low-to-high level transition of the clock input. All inputsare diode-clamped to minimize transmission-line effects.
Featuresn Gated (enable/disable) serial inputsn Fully buffered clock and serial inputsn Asynchronous clearn Typical clock frequency 36 MHzn Typical power dissipation 80 mW
Connection Diagram Function TableInputs Outputs
Clear Clock A B QA QB ... QHL X X X L L ... LH L X X QA0 QB0 ... QH0H ! H H H QAn ... QGnH ! L X L QAn ... QGnH ! X L L QAn ... QGn
H = High Level (steady state), L = Low Level (steady state)X = Don’t Care (any input, including transitions)! = Transition from low to high levelQA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indi-cated steady-state input conditions were established.QAn, QGn = The level of QA or QG before the most recent ! transition of theclock; indicates a one-bit shift.
Logic Diagram
Dual-In-Line Package
DS006398-1
Order Number 54LS164DMQB, 54LS164FMQB,54LS164LMQB, DM54LS164J, DM54LS164W,
DM74LS164M or DM74LS164NSee Package Number E20A,J14A, M14A, N14A or W14B
DS006398-2
March 1998
DM74LS164
8-BitSerialIn/ParallelOutShiftRegister
© 1998 Fairchild Semiconductor Corporation DS006398 www.fairchildsemi.com
As with all integrated circuits, this chip is powered by two pins, Vcc and GND. The pins A and B are typically wiredtogether1 and provide ‘shift in’ bits: every bit that appears on these pins is captured when the clock goes high.Next, the outputs are labeled QA through QH. The standard for labeling pins in 7400 series of devices is, at best,inconsistent; in general you need to scour the TTL product description pages to learn about these details. Here, theQA pin is the least significant bit in the stored byte. Be careful: some devices do not have Vcc and GND in the cornersor take ordered bits out of order. Reading the device documentation will save you time and reduce your sorrow.
The CLOCK line works exactly as CLK described above: the A/B lines are strobed into the device on the rising
edge of this signal. This edge-based triggering is always indicated by a little triangle at the entrance of the signal.If the TTL picture does not have that triangle, the action happens as long as the clock is high; it is level-triggered .Finally, an appropriate signal on the CLEAR will clear the internal memory to zeros. Because there is an ‘inverterbubble’ on the pin, we say the signal is active low : the clear will happen as long as the CLEAR pin is grounded.2 Ileave it to you to determine if the register starts up in a cleared state.
The 8-bit Linear Feedback Shift Register. Ideally, our 8-bit number generator would present an orbit of 256random values3 before any value is repeated. The linear feedback approach takes several bits from the serial shift
1This is strange. You might read the device documentation to discover other ways the designers imagined this device would be used.
2If you see both a inverter bubble and a edge-trigger triangle, the action occurs during the 1 to 0 or falling edge transition.
3These values are not random, of course (the circuit is deterministic, after all), but for many purposes they su�ciently unpredictable.
register at positions called taps and computes a mod-2 sum (think: XOR) to generate the next bit to be shiftedin. (We should begin our worrying now: if the register ever contained a zero, it would could never change. Why?Because there are no 1’s to generate a non-zero value. This configuration is said to lock up the device. Worry on.)It turns out that, starting with a non-zero value, four tap bits will support an orbit of 255 distinct values before thedevice again returns the first value. The location of the tap bits (as always, 0 is least significant) for registers with8 or fewer bits is given in the following table:
LFSR Tap Bits for Maximal Orbitsn taps n taps n taps n taps
1 0 2 1 0 3 2 1 4 3 25 4 2 6 5 4 7 6 5 8 7 5 4 3
Procedure. I would like you to build an 8-bit linear feedback shift register whose lock up configuration is all 1’s(as opposed to all 0’s).
1. Build a circuit that will allow you to fully control the 74-164 shift register. All inputs should be sourced bypower, ground, or switches. All outputs should be visible through the LED’s.
2. Determine, as best you can, whether the device powers up in an all-zero state. If not, your final circuit shouldprobably have a button that allows you to clear the register in case it gets locked up.
3. Clear your register and attempt to shift in a single one. You may observe that the slide switches on your benchare not debounced . Mechanical switching devices frequently make many momentary contacts before they settleinto position. This might result in your device strobing in several ones before the clock switch settles. Thisbehavior can be avoided by using debouncing circuitry present in the ‘momentary’ pushbuttons, A and B.
4. Design a network of taps that maximizes the orbit of the generator. I expect you to use one or two more chipsfrom your initial set. If necessary, you can borrow parts from our common supply cabinet but be aware thatthe 7400-family of devices does not include every kind of gate you might want. It is likely (nay, certain) thatthe devices I have already given you are su�cient for your purposes.
5. Implement the circuit and verify that it is working correctly. When you are satisfied with your generator drawthe logical network (ie. the gates, not the chips) you used, and report the first 16 decimal values your circuitgenerates. The first should be zero, of course.
6. Consider answering one or more of the extra credit questions, below.
7. After sending a picture of your circuit to your mother (she will be proud), tear down your circuit.
8. Turn in your written answers by noon next Tuesday.
Extra credit:
1. Notice that the tap bits always include the most significant bit. For example, bit 7 is needed for an 8 bit LFSRand bit 3 is needed for a 4 bit version. Explain why this must be true.
2. It would be much nicer if we could automate the generation of CLOCK signal. This is easily accomplished byrunning a wire from the function generator to the CLOCK line of your 74-164. (Try it!) Indeed, the circuit canbe driven quite quickly (Try it!). Unfortunately, the slowest square wave generated is 1 Hz (yeah, sure, try it.).Can you, based on a 1 Hz setting of the function generator and one or two additional chips, arrange for yourcircuit to deliver new random values every 5 seconds? Explain how.
3. Perhaps you want it to run more slowly. Can you generate a new random value every 10 seconds? Keep thesquare wave frequency at 1 Hz and try to avoid going to the parts cabinet. Explain your logic.
Part No. Product No. Pins Description 1 10 10049648 74160 16 Decade counter with asynch. clear ................... $.35 $.29 $.1949664 74161 16 Synchronous 4-bit counter ................................. .39 .35 .2549672 74163 16 Synchronous 4-bit counter ................................. .29 .22 .1249681 74164 14 8-bit serial shift register ...................................... .35 .29 .2549699 74165 16 8-bit serial shift register, parallel load ................. .49 .45 .2949779 74174 16 Hex D-type flip-flop with clear ............................ .49 .45 .3549795 74175 16 Quad D-type flip-flop with clear .......................... .49 .45 .3549824 74179 16 4-bit parallel-access shift register ....................... .13 .11 .0949832 74180 14 9-bit odd/even parity generator/checker ............. .25 .23 .2149841 74181 24 Arithmetic logic unit/function generator ........... 1.95 1.75 1.5549883 74189 16 64-bit RAM tri-state (DM8599N) ...................... 3.59 3.25 2.9549904 74191 16 Binary up/down counter ..................................... .99 .89 .7949912 74192 16 Decade up/down counter with clear .................. 3.95 3.59 3.2549939 74193 16 Binary up/down counter with clear ................... 1.39 1.19 1.0949955 74194 16 4-bit bi-directional shift register ....................... 1.25 .99 .7949963 74195 16 4-bit parallel-access shift register ....................... .13 .11 .0950041 74221 16 Dual mono. multiv. Schmitt trigger ..................... .15 .13 .1150104 74259 16 8-bit addressable latch (9334) ............................ .15 .13 .1250171 74279 16 Quad set-reset latch ............................................ .39 .35 .2950286 74367 16 Hex buffer tri-state (DM8097N) .......................... .13 .11 .0988225 SDLD001A __ Texas Instruments TTL Data Book .................. 34.95 31.49 29.95
Part No. Description 1 1084953 360 pc. 7400 series IC cabinet kit ............................................................... $129.95 $116.95
74C00 SeriesPart No. Product No. Pins Description 1 1044222 74C00 14 Quad 2-input NAND gate ................................................. $.49 $.3963538 74C02 14 Quad 2-input NOR gate ..................................................... .24 .2244231 74C04 14 Hex inverter (CD4069) ....................................................... .39 .3544257 74C14 14 Hex inverter Schmitt trigger (CD40106) ............................ .39 .3544441 74C74 14 Dual D flip-flop ................................................................ 1.29 1.1944329 74C174 16 Hex flip-flop (CD40174/MC14174BPC) ............................. .19 .1544345 74C193 16 Binary up/down counter w/ clear (40193) ....................... 1.49 1.2944361 74C221 16 Dual monostable multivibrator ........................................ 3.95 3.5913469 74C367 16 Hex buffer tri-state (80C97/CD4503) ................................. .49 .4544396 74C373 20 Octal D-type flip-flop with clear tri-state .......................... 3.95 3.5944409 74C374 20 Octal D flip-flop tri-state (INS82C06N) ............................ 1.49 1.2544564 74C922 18 16-key keyboard encoder (INS8245N) ............................ 6.95 6.2544572 74C923 20 20-key keyboard encoder (INS8246N) ............................ 6.95 6.2544581 74C925 16 4-digit CTR with MUX D segment driver .......................... 6.95 5.9544599 74C926 18 4-digit CTR with MUX D segment driver .......................... 7.95 6.95
74LS00 SeriesPart No. Product No. Pins Description 1 10 10046252 74LS00 14 Quad 2-input NAND gate .................................. $.25 $.19 $.1546287 74LS02 14 Quad 2-input NOR gate ....................................... .25 .19 .1746308 74LS03 14 Quad 2-input NAND gate (O.C.) .......................... .25 .19 .1746316 74LS04 14 Hex inverter ........................................................ .29 .25 .1946341 74LS05 14 Hex inverter (O.C.) .............................................. .29 .25 .1946359 74LS06 14 Hex inverter buffer/driver (O.C.) ......................... .49 .45 .3946367 74LS07 14 Hex buffer/driver (O.C. hi-voltage) ...................... .89 .79 .6946375 74LS08 14 Quad 2-input AND gate ....................................... .29 .25 .1946391 74LS09 14 Quad 2-input AND gate (O.C.) ............................. .25 .19 .1546404 74LS10 14 Triple 3-input NAND gate .................................... .29 .25 .1946439 74LS11 14 Triple 3-input AND gate ..................................... .29 .25 .1946640 74LS14 14 Hex inverter Schmitt trigger ................................ .25 .19 .1747095 74LS20 14 Dual 4-input NAND gate ..................................... .25 .19 .1747108 74LS21 14 Dual 4-input AND gate ........................................ .25 .19 .1747378 74LS27 14 Triple 3-input NOR gate ...................................... .25 .19 .1747458 74LS30 14 8-input NAND gate .............................................. .25 .19 .1747466 74LS32 14 Quad 2-input OR gate ......................................... .25 .19 .1747597 74LS37 14 Quad 2-input NAND buffer .................................. .39 .35 .2947693 74LS38 14 Quad 2-input NAND buffer (O.C.) ....................... .29 .25 .1547773 74LS42 16 BCD-to-decimal decoder ..................................... .69 .59 .4947790 74LS47 16 BCD to 7-seg. decoder/driver (O.C.) ................... .89 .79 .6947811 74LS48 16 BCD to 7-seg. decoder/driver ........................... 4.95 4.49 3.95
Part No. Product No. Pins Description 1 10 10048979 7400 14 Quad 2-input NAND gate .................................. $.59 $.49 $.4549007 7401 14 Quad 2-input NAND gate (O.C.) .......................... .49 .45 .3949015 7402 14 Quad 2-input NOR gate ....................................... .59 .49 .4549040 7404 14 Hex inverter ........................................................ .59 .49 .4549074 7405 14 Hex inverter (O.C.) .............................................. .29 .25 .2249091 7406 14 Hex inverter buffer/driver (O.C.) ......................... .45 .39 .3549120 7407 14 Hex buffer/driver (O.C.) ...................................... .59 .49 .4549146 7408 14 Quad 2-input AND gate ....................................... .59 .49 .4549189 7410 14 Triple 3-input NAND gate .................................... .25 .22 .1549269 7411 14 Triple 3-input AND gate .................................... 3.95 3.59 3.2549402 7413 14 Dual 4-input NAND gate Schmitt trigger ............. .29 .25 .1949437 7414 14 Hex inverter Schmitt trigger ................................ .45 .39 .3549630 7416 14 Hex inverter buffer/driver (O.C.) ......................... .25 .19 .1049728 7417 14 Hex buffer/driver (O.C. hi-voltage) ...................... .79 .69 .5950008 7420 14 Dual 4-input NAND gate ...................................... .49 .45 .3950024 7421 14 Dual 4-input AND gate ...................................... 2.95 2.75 2.4950083 7425 14 Dual 4-input NOR gate with strobe ................... 1.09 .99 .8950139 7427 14 Triple 3-input NOR gate ...................................... .49 .45 .3950198 7428 14 Quad 2-input NOR buffer .................................... .39 .35 .2550227 7430 14 8-input NAND gate .............................................. .25 .22 .1250235 7432 14 Quad 2-input OR gate ......................................... .59 .49 .4550315 7438 14 Quad 2-input NAND buffer (O.C.) ....................... .35 .29 .2550358 7440 14 Dual 4-input NAND buffer ................................... .13 .11 .0950374 7442 16 BCD-to-decimal decoder ..................................... .89 .79 .6950403 7445 16 BCD-to-decimal decoder/driver (30V) ................. .99 .89 .7950411 7446 16 BCD-to-7 segment decoder/driver (30V) .......... 1.29 1.19 1.0950420 7447 16 BCD-to-7 segment decoder/driver (15V) .......... 1.09 .99 .8950518 7470 14 Edge-triggered JK flip-flop .................................. .49 .45 .3550526 7472 14 AND gated JK master/slave flip-flop ................... .49 .45 .3550534 7473 14 Dual JK flip-flop with clear .................................. .99 .89 .7950551 7474 14 Dual D flip-flop ................................................... .45 .39 .2950577 7475 16 4-bit bi-stable latch ........................................... 2.95 2.75 2.4950593 7476 16 Dual JK flip-flop with preset and clear .............. 1.19 1.09 .9950631 7483 16 4-bit binary full adder ......................................... .89 .79 .6950657 7485 16 4-bit magnitude comp. ....................................... .39 .29 .2250665 7486 14 Quad EXCLUSIVE-OR gate .................................. .79 .69 .5950681 7489 16 64-bit RAM P 50ns ........................................... 2.95 2.75 2.4950690 7490 14 Decade counter ................................................... .89 .79 .6950737 7492 14 Divide-by-12 counter .........................................1.19 1.09 .8950745 7493 14 4-bit binary counter .......................................... 1.29 1.19 1.0950770 7495 14 4-bit parallel-access shift register (K155N) ........ .69 .59 .3950788 7496 16 5-bit parallel-in, parallel-out shift register ........... .49 .39 .2950796 7497 16 Synch. 6-bit binary rate multipliers ................... 3.49 3.29 2.9549234 74107 14 Dual JK flip-flop with clear .................................. .39 .35 .2549251 74109 16 Dual positive edge triggered JK flip-flop ............. .37 .34 .3149293 74116 24 Dual 4-bit latches with clear ............................... .99 .89 .7949322 74121 14 Monostable multivibrator .................................... .99 .89 .7949349 74122 14 Retriggerable mono. multivibrator with clear ...... .69 .59 .4549357 74123 16 Dual retriggerable mono. multivibrator ............... .89 .79 .6949373 74125 14 Quad bus buffer tri-state (DM8093N) ................. .99 .89 .7949381 74126 14 Quad bus buffer tri-state (DM8094N) ................. .79 .69 .5949411 74132 14 Quad 2-input NAND Schmitt trigger ................... .69 .59 .3549496 74148 16 8 to 3 line octal priority encoder ......................... .89 .79 .6949509 74150 24 16 to 1 line multiplexer ..................................... 1.95 1.75 1.5549525 74151 16 8-input multiplexer ............................................. .29 .25 .1549550 74153 16 Dual 4/1 data selector/multiplexer ...................... .25 .22 .1549568 74154 24 4 to16 line decoder/demultiplexer .................... 2.25 1.95 1.7549605 74157 16 Quad 2/1 data selector ........................................ .39 .35 .29
7
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Part Number Color Code Legend
DM74LS00Quad 2-Input NAND GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic NAND function.
Featuresn Alternate Military/Aerospace device (54LS00) isavailable. Contact a Fairchild Semiconductor SalesOffice/Distributor for specifications.
Connection Diagram
Function Table
Y = ABInputs Output
A B YL L HL H HH L HH H L
H = High Logic LevelL = Low Logic Level
Dual-In-Line Package
DS006439-1
Order Number 54LS00DMQB, 54LS00FMQB, 54LS00LMQB, DM54LS00J, DM54LS00W, DM74LS00M or DM74LS00NSee Package Number E20A, J14A, M14A, N14A or W14B
March 1998
DM74LS00
Quad
2-InputNANDGates
© 1998 Fairchild Semiconductor Corporation DS006439 www.fairchildsemi.com
DM74LS04Hex Inverting GatesGeneral DescriptionThis device contains six independent gates each of whichperforms the logic INVERT function.
Featuresn Alternate Military/Aerospace device (54LS04) isavailable. Contact a Fairchild Semiconductor SalesOffice/Distributor for specifications.
Connection Diagram
Function Table
Y = AInput OutputA YL HH L
H = High Logic LevelL = Low Logic Level
Dual-In-Line Package
DS006345-1
Order Number 54LS04DMQB, 54LS04FMQB, 54LS04LMQB, DM54LS04J, DM54LS04W, DM74LS04M or DM74LS04NSee Package Number E20A, J14A, M14A, N14A or W14B
March 1998
DM74LS04
HexInverting
Gates
© 1998 Fairchild Semiconductor Corporation DS006345 www.fairchildsemi.com
DM74LS86Quad 2-Input Exclusive-OR GatesGeneral DescriptionThis device contains four independent gates each of whichperforms the logic exclusive-OR function.
Connection Diagram
Function Table
Y = A % B = A B + ABInputs Output
A B YL L LL H HH L HH H L
H = High Logic LevelL = Low Logic Level
Dual-In-Line Package
DS006380-1
Order Number DM54LS86J, DM54LS86W, DM74LS86M or DM74LS86NSee Package Number J14A, M14A, N14A or W14B
March 1998
DM74LS86
Quad
2-InputExclusive-ORGates
© 1998 Fairchild Semiconductor Corporation DS006380 www.fairchildsemi.com
DM74LS1648-Bit Serial In/Parallel Out Shift RegisterGeneral DescriptionThese 8-bit shift registers feature gated serial inputs and anasynchronous clear. A low logic level at either input inhibitsentry of the new data, and resets the first flip-flop to the lowlevel at the next clock pulse, thus providing complete controlover incoming data. A high logic level on either input enablesthe other input, which will then determine the state of the firstflip-flop. Data at the serial inputs may be changed while theclock is high or low, but only information meeting the setupand hold time requirements will be entered. Clocking occurs
on the low-to-high level transition of the clock input. All inputsare diode-clamped to minimize transmission-line effects.
Featuresn Gated (enable/disable) serial inputsn Fully buffered clock and serial inputsn Asynchronous clearn Typical clock frequency 36 MHzn Typical power dissipation 80 mW
Connection Diagram Function TableInputs Outputs
Clear Clock A B QA QB ... QHL X X X L L ... LH L X X QA0 QB0 ... QH0H ↑ H H H QAn ... QGnH ↑ L X L QAn ... QGnH ↑ X L L QAn ... QGn
H = High Level (steady state), L = Low Level (steady state)X = Don’t Care (any input, including transitions)↑ = Transition from low to high levelQA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indi-cated steady-state input conditions were established.QAn, QGn = The level of QA or QG before the most recent ↑ transition of theclock; indicates a one-bit shift.
Logic Diagram
Dual-In-Line Package
DS006398-1
Order Number 54LS164DMQB, 54LS164FMQB,54LS164LMQB, DM54LS164J, DM54LS164W,
DM74LS164M or DM74LS164NSee Package Number E20A,J14A, M14A, N14A or W14B
DS006398-2
March 1998
DM74LS164
8-BitSerialIn/ParallelOutShiftRegister
© 1998 Fairchild Semiconductor Corporation DS006398 www.fairchildsemi.com
